| Title | Low Cost PLD with High Speed Partial Reconfiguration |
| Author | *Naoki Hirakawa, Masanori Yoshihara (Hiroshima City Univ., Japan), Masayuki Sato (Tokyo Metropolitan Univ., Japan), Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ., Japan) |
| Page | pp. 557 - 560 |
| Detailed information (abstract, keywords, etc) | |
| Title | High Performance Level-Converting Flip-Flop with a Simple Pulse Generator and a Fast Latch |
| Author | *Hyoun Soo Park, Hong Bo Che, Wook Kim, Young Hwan Kim (Pohang Univ. of Science and Tech., Republic of Korea) |
| Page | pp. 561 - 564 |
| Detailed information (abstract, keywords, etc) | |
| Title | On Analog Circuit Design Methodology via Multi-Objective Geometric Programming |
| Author | *Theerachet Soorapanth (National Electronics and Computer Technology Center, Thailand) |
| Page | pp. 565 - 568 |
| Detailed information (abstract, keywords, etc) | |
| Title | On Objective Functions for Fixed-Outline Floorplanning |
| Author | *Lu Wang, Xiaolin Zhang, Song Chen, Takeshi Yoshimura (Waseda Univ., Japan) |
| Page | pp. 569 - 572 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Design of Low Power MAC Operator with Fault Tolerance |
| Author | *Han-Sam Jung, Sung-Kwan Ku, Ki-Seok Chung (Hanyang Univ., Republic of Korea) |
| Page | pp. 573 - 576 |
| Detailed information (abstract, keywords, etc) | |