| Title | Low Cost PLD with High Speed Partial Reconfiguration |
| Author | *Naoki Hirakawa, Masanori Yoshihara (Graduate School of Information Sciences, Hiroshima City University, Japan), Masayuki Sato (Graduate School of Engineering, Tokyo Metropolitan University, Japan), Kazuya Tanigawa, Tetsuo Hironaka (Graduate School of Information Sciences, Hiroshima City University, Japan) |
| Page | pp. 557 - 560 |
| Keyword | FPGA, reconfigurable system, memory, partial reconfiguration, LUT |
| Abstract | Field Programmable Gate Arrays (FPGAs) have been used for implementing various applications. But the switch matrix occupies a significantly large area in FPGA. And configuration speed of FPGA is slow. So, we proposed MPLD as a new Programmable Logic Device (PLD). MPLD has no switch matrix, and partial reconfiguration is easy and fast because configuration method is same as write access of the conventional parallel memory. In this paper, we present MPLD and evaluation results of the prototype MPLD chip. |
| Title | High Performance Level-Converting Flip-Flop with a Simple Pulse Generator and a Fast Latch |
| Author | *Hyoun Soo Park, Hong Bo Che, Wook Kim, Young Hwan Kim (Pohang University of Science and Technology, Republic of Korea) |
| Page | pp. 561 - 564 |
| Keyword | Multi-VDD system, level conversion, flip-flop, pulse generator |
| Abstract | This paper proposes a high-performance level-converting flip-flop (LCFF) for multi-VDD systems, called the explicit pulse-triggered dual-pass-transistor flip-flop (EPDFF). The proposed EPDFF provides both low power and high speed operations through the use of a simple pulse generator and a simple latch with a short signal propagation path. In experiments, EPDFF outperformed six existing LCFFs in both power consumption and delay in its operating range. After optimization for the minimum power-delay product (PDP), EPDFF had 19.4~52.6% less PDP than existing LCFFs, and had the smallest transistor area among the seven LCFFs we compared. |
| Title | On Analog Circuit Design Methodology via Multi-Objective Geometric Programming |
| Author | *Theerachet Soorapanth (National Electronics and Computer Technology Center, Thailand) |
| Page | pp. 565 - 568 |
| Keyword | optimization, analog circuit design, computer-aided design, geometric programming |
| Abstract | This paper concerns a design methodology for analog circuit problems, which is based on formulating the problem as a multi-objective geometric program (GP). Multiple objectives are combined into a scalar objective thru certain convex functions and thus can be solved using regular GP algorithms. In contrast to single-objective optimization, simultaneous consideration of all objectives yields a compromising solution among objectives. By varying individual objective’s weight factor, a Pareto (or trade-off) curve can be constructed, providing designers with a useful decision-making information. |
| Title | On Objective Functions for Fixed-Outline Floorplanning |
| Author | *Lu Wang, Xiaolin Zhang, Song Chen, Takeshi Yoshimura (Graduate School of Information, Production and System, Waseda University, Japan) |
| Page | pp. 569 - 572 |
| Keyword | Floorplanning, Fixed-Outline constraints, Simulated Annealing, Objective Functions |
| Abstract | Fixed-outline floorplanning enables multilevel hierarchical design, where aspect ratios and area of floorplans are usually imposed by higher level floorplanning and must be satisfied. Simulated Annealing is widely used in the floorplanning problem. It is well-known that the solution space, solution perturbation, and objective function are very important for Simulated Annealing. In this paper, we focus on the objective functions used in FOFP problem. Up to now, many kinds of objective functions were proposed in the existing researches, but those objective functions had many limitations, and the applicable situation is not clearly. We summarize and analyze the existing objective functions used in Fixed-Outline floorplanning methods, and then suggest some new objective functions respectively used in the fixed-oultine floorplanning with and without wire-length optimization, respectively. |
| Title | A Design of Low Power MAC Operator with Fault Tolerance |
| Author | *Han-Sam Jung, Sung-Kwan Ku, Ki-Seok Chung (Hanyang University, Republic of Korea) |
| Page | pp. 573 - 576 |
| Keyword | Low Power, MAC, Fault Tolerance |
| Abstract | As more DSP functionalities are integrated into an embedded mobile device, power consumption and device reliability have emerged as crucial issues. As the complexity of mobile embedded designs increases very rapidly, verifying the functionality of the mobile devices completely has become extremely difficult. Therefore, designs with error (fault) tolerance are often required since these capabilities will enable the design to operate properly even with some existence of errors. However, designs with fault tolerance may suffer from significant power overhead since fault tolerance is often achieved by resource replication. In this paper, we propose a low power and fault tolerant MAC (multiply-and-accumulate) design. The proposed MAC design is based on multiple barrel shifters since MAC designs with barrel-shifters and adders are known to be excellent in terms of power consumption. |