The 26th Asia and South Pacific Design Automation Conference
Technical Program

Remark:

Presentations and chat Q&A are available from Jan. 12 to 29.
Before the live chat Q&A sessions, the videos are broadcasted via Zoom for mainly mainland China on the same day.
Live chat Q&A sessions, which all the speakers and session chairs in each session are attending, are held according to "Live Tutorial / Live Q&A Session Schedule".
Tutorials are given live on Zoom according to the time table, and later the videos will be available.
Time zone is JST (=UTC+9:00)
The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Live Tutorial / Live Q&A Session Schedule

Monday, January 18, 2021

Room T1, T4	Room T2, T5	Room T3
T1 (Room T1) Tutorial-1 (live session and its video) 9:00 - 12:00	T2 (Room T2) Tutorial-2 (live session and its video) 9:00 - 12:00	T3 (Room T3) Tutorial-3 (live session and its video) 9:00 - 12:00
T4 (Room T4) Tutorial-4 (live session and its video) 14:00 - 17:00	T5 (Room T5) Tutorial-5 (live session and its video) 14:00 - 17:00

Tuesday, January 19, 2021

Room 1A - 3A	Room 1B - 3B	Room 1C - 3C	Room 1D - 3D	Room 1E - 3E
1K (Room K) Opening and Keynote Session I (video and its broadcast via Zoom)
1A (Room 1A) University Design Contest I 15:00 - 15:30	1B (Room 1B) Accelerating Design and Simulation 15:00 - 15:30	1C (Room 1C) Process-in-Memory for Efficient and Robust AI 15:00 - 15:30	1D (Room 1D) Validation and Verification 15:00 - 15:30	1E (Room 1E) Design Automation Methods for Various Microfluidic Platforms 15:00 - 15:30
2A (Room 2A) University Design Contest II 15:30 - 16:00	2B (Room 2B) Emerging Non-Volatile Processing-In-Memory for Next Generation Computing 15:30 - 16:00	2C (Room 2C) (SS-1) Emerging Trends for Cross-Layer Co-Design: From Device, Circuit, to Architecture, Application 15:30 - 16:00	2D (Room 2D) Machine Learning Techniques for EDA in Analog/Mixed-Signal ICs 15:30 - 16:00	2E (Room 2E) Innovating Ideas in VLSI Routing Optimization 15:30 - 16:00
3A (Room 3A) (SS-2) ML-Driven Approximate Computing 16:00 - 16:30	3B (Room 3B) Architecture-Level Exploration 16:00 - 16:30	3C (Room 3C) Core Circuits for AI Accelerators 16:00 - 16:30	3D (Room 3D) Stochastic and Approximate Computing 16:00 - 16:30	3E (Room 3E) Timing Analysis and Timing-Aware Design 16:00 - 16:30

Wednesday, January 20, 2021

Room 4A - 6A	Room 4B - 6B	Room 4C - 6C	Room 4D - 6D	Room 4E - 6E
2K (Room K) Keynote Session II (video and its broadcast via Zoom)
4A (Room 4A) (SS-3) Technological Advancements inside the AI chips, and using the AI Chips 15:00 - 15:30	4B (Room 4B) System-Level Modeling, Simulation, and Exploration 15:00 - 15:30	4C (Room 4C) Neural Network Optimizations for Compact AI Inference 15:00 - 15:30	4D (Room 4D) Brain-Inspired Computing 15:00 - 15:30	4E (Room 4E) Cross-Layer Hardware Security 15:00 - 15:30
5A (Room 5A) (DF-1): New-Principle Computer 15:30 - 16:00	5B (Room 5B) Embedded Operating Systems and Information Retrieval 15:30 - 16:00	5C (Room 5C) (SS-4) Security Issues in AI and Their Impacts on Hardware Security 15:30 - 16:00	5D (Room 5D) Advances in Logic and High-level Synthesis 15:30 - 16:00	5E (Room 5E) Hardware-Oriented Threats and Solutions in Neural Networks 15:30 - 16:00
6A (Room 6A) (DF-2): Advanced Sensing Technology and Automotive Application 16:00 - 16:30	6B (Room 6B) Advanced Optimizations for Embedded Systems 16:00 - 16:30	6C (Room 6C) Design and Learning of Logic Circuits and Systems 16:00 - 16:30	6D (Room 6D) Hardware Locking and Obfuscation 16:00 - 16:30	6E (Room 6E) Efficient Solutions for Emerging Technologies 16:00 - 16:30

Thursday, January 21, 2021

Room 7A - 9A	Room 7B - 9B	Room 7C - 9C	Room 7D - 9D	Room 7E - 9E
3K (Room K) Keynote Session III (video and its broadcast via Zoom)
7A (Room 7A) (SS-5) Platform-Specific Neural Network Acceleration 15:00 - 15:30	7B (Room 7B) Toward Energy-Efficient Embedded Systems 15:00 - 15:30	7C (Room 7C) Software and System Support for Nonvolatile Memory 15:00 - 15:30	7D (Room 7D) Learning-Driven VLSI Layout Automation Techniques 15:00 - 15:30	7E (Room 7E) DNN-Based Physical Analysis and DNN Accelerator Design 15:00 - 15:30
8A (Room 8A) (DF-3): Emerging Open Design Platform 15:30 - 16:00	8B (Room 8B) Embedded Neural Networks and File Systems 15:30 - 16:00	8C (Room 8C) (SS-6) Design Automation for Future Autonomy 15:30 - 16:00	8D (Room 8D) Emerging Hardware Verification 15:30 - 16:00	8E (Room 8E) Optimization and Mapping Methods for Quantum Technologies 15:30 - 16:00
9A (Room 9A) (DF-4): Technological Utilization in COVID-19 Pandemic 16:00 - 16:30	9B (Room 9B) Emerging System Architectures for Edge-AI 16:00 - 16:30	9C (Room 9C) (SS-7) Cutting-Edge EDA Techniques for Advanced Process Technologies 16:00 - 16:30	9D (Room 9D) (SS-8) Robust and Reliable Memory Centric Computing at Post-Moore 16:00 - 16:30	9E (Room 9E) Design for Manufacturing and Soft Error Tolerance 16:00 - 16:30

DF: Designers' Forum, SS: Special Session

List of papers

Remark:

Presentations and chat Q&A are available from Jan. 12 to 29.
Before the live chat Q&A sessions, the videos are broadcasted via Zoom for mainly mainland China on the same day.
Live chat Q&A sessions, which all the speakers and session chairs in each session are attending, are held according to "Live Tutorial / Live Q&A Session Schedule".
Tutorials are given live on Zoom according to the time table, and later the videos will be available.
Time zone is JST (=UTC+9:00)
The presenter of each paper is marked with "*".

Monday, January 18, 2021

[To Session Table]

Session T1 Tutorial-1 (live session and its video)
Time: 9:00 - 12:00, Monday, January 18, 2021
Location: Room T1

T1-1

Title	(Tutorial) Achieving Quantum Computing's Disruptive Capabilities through Error-Mitigating Software
Author	Joseph Emerson (Quantum Benchmark/Univ. of Waterloo, Canada)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session T2 Tutorial-2 (live session and its video)
Time: 9:00 - 12:00, Monday, January 18, 2021
Location: Room T2

T2-1

Title	(Tutorial) Reliability and Availability of Hardware-Software Systems — Stochastic Reliability Models of Real Systems
Author	Kishor S. Trivedi (Duke Univ., USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session T3 Tutorial-3 (live session and its video)
Time: 9:00 - 12:00, Monday, January 18, 2021
Location: Room T3

T3-1

Title	(Tutorial) Machine Learning in EDA Tutorial: Approaches, Advantages, Challenges and Examples
Author	Elias Fallon (Cadence Design Systems, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session T4 Tutorial-4 (live session and its video)
Time: 14:00 - 17:00, Monday, January 18, 2021
Location: Room T4

T4-1

Title	(Tutorial) The Latest Heterogenous Integration Packaging Trends for 5G, Artificial Intelligence, Automotive Electronics, and High Performance Computing
Author	Henry H. Utsunomiya (Interconnection Technologies, Japan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session T5 Tutorial-5 (live session and its video)
Time: 14:00 - 17:00, Monday, January 18, 2021
Location: Room T5

T5-1

Title	(Tutorial) Emerging Devices from Manufacturing Point of View: 3D NAND Flash Memory, PCRAM and Carbon Nanotube
Author	Koukou Suu (Ulvac Technologies, USA), Yoshihiro Hirota (Tokyo Electron, Japan), Shigemi Murakawa (Zeon, Japan)
Detailed information (abstract, keywords, etc)

Tuesday, January 19, 2021

[To Session Table]

Session 1K Opening and Keynote Session I (video and its broadcast via Zoom)
Location: Room K

1K-1

Title

Opening:
1. Welcome by GC (Mr. Hattori)
2. Welcome by SC-Chair (Prof. Onodera)
3. Program Report by TPC Chair (Prof. Tan)
    3-1. Best Paper Award Presentation (Prof. Hashimoto)
    3-2. 10-Year Retrospective Most Influential Paper Award Presentation (Prof. Hashimoto)
4. Designers' Forum Report by DF Chair (Mr. Yamashita)
5. Design Contest Report by UDC Co-Chair (Prof. Tsuchiya)
    5.1 UDC Award Presentation (Prof. Tsuchiya)
6. Student Research Forum Report by SRF Chair (Prof. Weichen Liu)
7. IEEE CEDA Awards by CEDA Award Chair (Prof. Wakabayashi)
    7.1 CEDA outstanding service award (Prof. Wakabayashi)
8. Welcome message for ASP-DAC 2022 by 2022GC (Prof. Ting-Chi Wang)

Detailed information (keywords, etc)

1K-2

Title	Introduction of Prof. Kaushik Roy by Toshihiro Hattori (Renesas Electronics, Japan)
Detailed information (keywords, etc)

1K-3

Title	(Keynote Address) Re-Engineering Computing with Neuro-Inspired Learning: Devices, Circuits, and Systems
Author	Kaushik Roy (Purdue Univ., USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1A University Design Contest I
Time: 15:00 - 15:30, Tuesday, January 19, 2021
Location: Room 1A
Chairs: Kousuke Miyaji (Shinshu Univ., Japan), Akira Tsuchiya (Univ. of Shiga Prefecture, Japan)

Best Design Award
1A-1

Title	A DSM-based Polar Transmitter with 23.8% System Efficiency
Author	*Yuncheng Zhang, Bangan Liu, Xiaofan Gu, Chun Wang, Atsushi Shirane, Kenichi Okada (Tokyo Inst. of Tech., Japan)
Page	pp. 1 - 2
Detailed information (abstract, keywords, etc)

1A-2

Title	A 0.41W 34Gb/s 300GHz CMOS Wireless Transceiver
Author	*Ibrahim Abdo, Takuya Fujimura, Tsuyoshi Miura, Korkut K. Tokgoz, Atsushi Shirane, Kenichi Okada (Tokyo Inst. of Tech., Japan)
Page	pp. 3 - 4
Detailed information (abstract, keywords, etc)

1A-3

Title	Capacitive Sensor Circuit with Relative Slope-Boost Method Based on a Relaxation Oscillator
Author	*Ryo Onishi, Koki Miyamoto, Korkut Kaan Tokgoz, Noboru Ishihara, Hiroyuki Ito (Tokyo Inst. of Tech., Japan)
Page	pp. 5 - 6
Detailed information (abstract, keywords, etc)

1A-4

Title	28GHz Phase Shifter with Temperature Compensation for 5G NR Phased-array Transceiver
Author	*Yi Zhang, Jian Pang, Kiyoshi Yanagisawa, Atsushi Shirane, Kenichi Okada (Tokyo Inst. of Tech., Japan)
Page	pp. 7 - 8
Detailed information (abstract, keywords, etc)

1A-5

Title	An up to 35 dBc/Hz Phase Noise Improving Design Methodology for Differential-Ring-Oscillators Applied in Ultra-Low Power Systems
Author	*Peter Toth, Hiroki Ishikuro (Keio Univ., Japan)
Page	pp. 9 - 10
Detailed information (abstract, keywords, etc)

1A-6

Title	Gate Voltage Optimization in Capacitive DC-DC Converters for Thermoelectric Energy Harvesting
Author	*Yi Tan, Yohsuke Shiiki, Hiroki Ishikuro (Keio Univ., Japan)
Page	pp. 11 - 12
Detailed information (abstract, keywords, etc)

1A-7

Title	An 0.57 GOPS/DSP Object Detection PIM Accelerator on FPGA
Author	*Bo Jiao, Jinshan Zhang, Yuanyuan Xie, Shunli Wang, Haozhe Zhu, Xiaoyang Kang, Zhiyan Dong, Lihua Zhang, Chixiao Chen (Fudan Univ., China)
Page	pp. 13 - 14
Detailed information (abstract, keywords, etc)

1A-8

Title	Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers
Author	Shinya Tanimura, *Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (Univ. of Shiga Prefecture, Japan)
Page	pp. 15 - 16
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1B Accelerating Design and Simulation
Time: 15:00 - 15:30, Tuesday, January 19, 2021
Location: Room 1B
Chairs: Chien-Chung Ho (National Chung Cheng Univ., Taiwan), Chun-Yi Lee (National Tsing Hua Univ., Taiwan)

1B-1

Title	A Fast Yet Accurate Message-level Communication Bus Model for Timing Prediction of SDFGs on MPSoC
Author	*Hai-Dang Vu, Sebastien Le Nours, Sebastien Pillement (Univ. of Nantes, France), Ralf Stemmer, Kim Gruettner (OFFIS, Germany)
Page	pp. 17 - 22
Detailed information (abstract, keywords, etc)

1B-2

Title	Simulation of Ideally Switched Circuits in SystemC
Author	*Breytner Joseph Fernandez-Mesa, Liliana Andrade, Frédéric Pétrot (Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, France)
Page	pp. 23 - 28
Detailed information (abstract, keywords, etc)

1B-3

Title	HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks
Author	*Soowang Park (Univ. of Southern California, USA), Jae-Won Nam (Seoul National Univ. of Science and Tech., Republic of Korea), Sandeep K. Gupta (Univ. of Southern California, USA)
Page	pp. 29 - 34
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1C Process-in-Memory for Efficient and Robust AI
Time: 15:00 - 15:30, Tuesday, January 19, 2021
Location: Room 1C
Chairs: Shouzhen Gu (Eastern China Normal Univ., China), Weiwen Jiang (Univ. of Notre Dame, USA)

1C-1

Title	A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs
Author	*Chirag Sudarshan (Tech. Univ. Kaiserslautern, Germany), Taha Soliman, Cecilia De la Parra (Robert Bosch GmbH – Corporate Research, Germany), Christian Weis (Tech. Univ. Kaiserslautern, Germany), Leonardo Ecco (Robert Bosch GmbH – Corporate Research, Germany), Matthias Jung (Fraunhofer IESE, Germany), Norbert Wehn (Tech. Univ. Kaiserslautern, Germany), Andre Guntoro (Robert Bosch GmbH – Corporate Research, Germany)
Page	pp. 35 - 42
Detailed information (abstract, keywords, etc)

1C-2

Title	A Quantized Training Framework for Robust and Accurate ReRAM-based Neural Network Accelerators
Author	*Chenguang Zhang, Pingqiang Zhou (ShanghaiTech Univ., China)
Page	pp. 43 - 48
Detailed information (abstract, keywords, etc)

1C-3

Title	Attention-in-Memory for Few-Shot Learning with Configurable Ferroelectric FET Arrays
Author	*Dayane Reis, Ann Franchesca Laguna, Michael Niemier, X. Sharon Hu (Univ. of Notre Dame, USA)
Page	pp. 49 - 54
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1D Validation and Verification
Time: 15:00 - 15:30, Tuesday, January 19, 2021
Location: Room 1D
Chairs: Seetal Potluri (NC State Univ., USA), He Li (Univ. of Cambridge, UK)

1D-1

Title	Mutation-based Compliance Testing for RISC-V
Author	Vladimir Herdt (DFKI GmbH, Germany), *Sören Tempel (Univ. of Bremen, Germany), Daniel Große (Johannes Kepler Univ. Linz, Austria), Rolf Drechsler (Univ. of Bremen & DFKI GmbH, Germany)
Page	pp. 55 - 60
Detailed information (abstract, keywords, etc)

1D-2

Title	A General Equivalence Checking Framework for Multivalued Logic
Author	*Chia-Chun Lin, Hsin-Ping Yen, Sheng-Hsiu Wei, Pei-Pei Chen (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (Yuan Ze Univ., Taiwan), Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 61 - 66
Detailed information (abstract, keywords, etc)

1D-3

Title	ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs
Author	*Mehran Goli, Rolf Drechsler (Univ. of Bremen/DFKI, Germany)
Page	pp. 67 - 72
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1E Design Automation Methods for Various Microfluidic Platforms
Time: 15:00 - 15:30, Tuesday, January 19, 2021
Location: Room 1E
Chairs: Tsun-Ming Tseng (Tech. Univ. of Munich, Germany), Yamashita Shigeru (Ritsumeikan Univ., Japan)

1E-1

Title	A multi-commodity network flow based routing algorithm for paper-based digital microfluidic biochips
Author	*Nai-Ren Shih, Tsung-Yi Ho (National Tsing Hua Univ., Taiwan)
Page	pp. 73 - 78
Detailed information (abstract, keywords, etc)

1E-2

Title	Interference-free Design Methodology for Paper-Based Digital Microfluidic Biochips
Author	*Yun-Chen Lo (National Tsing Hua Univ., Taiwan), Bing Li (Tech. Univ. München, Germany), Sooyong Park, Kwanwoo Shin (Sogang Univ., Republic of Korea), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan)
Page	pp. 79 - 84
Detailed information (abstract, keywords, etc)

1E-3

Title	Accurate and Efficient Simulation of Microfluidic Networks
Author	*Gerold Fink, Philipp Ebner, Medina Hamidović, Werner Haselmayr, Robert Wille (Johannes Kepler Univ., Austria)
Page	pp. 85 - 90
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2A University Design Contest II
Time: 15:30 - 16:00, Tuesday, January 19, 2021
Location: Room 2A
Chairs: Kousuke Miyaji (Shinshu Univ., Japan), Akira Tsuchiya (Univ. of Shiga Prefecture, Japan)

Special Feature Award
2A-1

Title	A 65nm CMOS Process Li-ion Battery Charging Cascode SIDO Boost Converter with 89% Maximum Efficiency for RF Wireless Power Transfer Receiver
Author	*Yasuaki Isshiki, Dai Suzuki, Ryo Ishida, Kousuke Miyaji (Shinshu Univ., Japan)
Page	pp. 91 - 92
Detailed information (abstract, keywords, etc)

2A-2

Title	A High Accuracy Phase and Amplitude Detection Circuit for Calibration of 28GHz Phased Array Beamformer System
Author	*Joshua Alvin, Jian Pang, Atsushi Shirane, Kenichi Okada (Tokyo Inst. of Tech., Japan)
Page	pp. 93 - 94
Detailed information (abstract, keywords, etc)

2A-3

Title	A Highly Integrated Energy-efficient CMOS Millimeter-wave Transceiver with Direct-modulation Digital Transmitter, Quadrature Phased-coupled Frequency Synthesizer and Substrate-Integrated Waveguide E-shaped Patch Antenna
Author	*Wei Deng, Zheng Song, Ruichang Ma, Haikun Jia, Baoyong Chi (Tsinghua Univ., China)
Page	pp. 95 - 96
Detailed information (abstract, keywords, etc)

2A-4

Title	A 3D-Stacked SRAM Using Inductive Coupling Technology for AI Inference Accelerator in 40-nm CMOS
Author	*Kota Shiba, Tatsuo Omori, Mototsugu Hamada, Tadahiro Kuroda (Univ. of Tokyo, Japan)
Page	pp. 97 - 98
Detailed information (abstract, keywords, etc)

2A-5

Title	Sub-10-μm Coil Design for Multi-Hop Inductive Coupling Interface
Author	*Tatsuo Omori, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda (Univ. of Tokyo, Japan)
Page	pp. 99 - 100
Detailed information (abstract, keywords, etc)

2A-6

Title	Current-Starved Chaotic Oscillator Over Multiple Frequency Decades on Low-Cost CMOS
Author	*Korkut Kaan Tokgoz, Ludovico Minati, Hiroyuki Ito (Tokyo Inst. of Tech., Japan)
Page	pp. 101 - 102
Detailed information (abstract, keywords, etc)

2A-7

Title	TCI tester: Tester for Through Chip Interface
Author	*Hideto Kayashima, Hideharu Amano (Keio Univ., Japan)
Page	pp. 103 - 104
Detailed information (abstract, keywords, etc)

2A-8

Title	An 18 Bit Time-to-Digital Converter Design with Large Dynamic Range and Automated Multi-Cycle Concept
Author	*Peter Toth, Hiroki Ishikuro (Keio Univ., Japan)
Page	pp. 105 - 106
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2B Emerging Non-Volatile Processing-In-Memory for Next Generation Computing
Time: 15:30 - 16:00, Tuesday, January 19, 2021
Location: Room 2B
Chairs: Md Tanvir Arafin (Morgan State Univ., USA), Tae Hyoung (Tony) Kim (Nanyang Technological Univ., Singapore)

Best Paper Award
2B-1

Title	Connection-based Processing-In-Memory Engine Design Based on Resistive Crossbars
Author	*Shuhang Zhang (Tech. Univ. of Munich, Germany), Hai Li (Duke Univ., USA), Ulf Schlichtmann (Tech. Univ. of Munich, Germany)
Page	pp. 107 - 113
Detailed information (abstract, keywords, etc)

2B-2

Title	FePIM: Contention-Free In-Memory Computing Based on Ferroelectric Field-Effect Transistors
Author	*Xiaoming Chen, Yuping Wu, Yinhe Han (Chinese Academy of Sciences, China)
Page	pp. 114 - 119
Detailed information (abstract, keywords, etc)

2B-3

Title	RIME: A Scalable and Energy-Efficient Processing-In-Memory Architecture for Floating-Point Operations
Author	*Zhaojun Lu (Univ. of Maryland, USA), Md Tanvir Arafin (Morgan State Univ., USA), Gang Qu (Univ. of Maryland, USA)
Page	pp. 120 - 125
Detailed information (abstract, keywords, etc)

2B-4

Title	A Non-Volatile Computing-In-Memory Framework With Margin Enhancement Based CSA and Offset Reduction Based ADC
Author	*Yuxuan Huang, Yifan He, Jinshan Yue, Huazhong Yang, Yongpan Liu (Tsinghua Univ., China)
Page	pp. 126 - 131
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2C (SS-1) Emerging Trends for Cross-Layer Co-Design: From Device, Circuit, to Architecture, Application
Time: 15:30 - 16:00, Tuesday, January 19, 2021
Location: Room 2C
Chairs: Xunzhao Yin (Zhejiang Univ., China), Mohsen Imani (Univ. of California, Irvine, USA)

2C-1

Title	(Invited Paper) Cross-layer Design for Computing-in-Memory: From Devices, Circuits, to Architectures and Applications
Author	Hussam Amrouch (Univ. of Stuttgart, Germany), Xiaobo Sharon Hu (Univ. of Notre Dame, USA), Mohsen Imani (Univ. of California, Irvine, USA), Ann Franchesca Laguna, Michael Niemier (Univ. of Notre Dame, USA), Simon Thomann (Karlsruhe Inst. of Tech., Germany), Xunzhao Yin, Cheng Zhuo (Zhejiang Univ., China)
Page	pp. 132 - 139
Detailed information (keywords, etc)

2C-2

Title	(Invited Paper) Impact of Emerging Devices on Future Computing
Author	Hussam Amrouch (Univ. of Stuttgart, Germany)
Detailed information (keywords, etc)

2C-3

Title	(Invited Paper) SaVI: Seed-and-Vote based In-Memory Accelerator for DNA Read Mapping
Author	*Ann Franchesca Laguna, Xiaobo Sharon Hu (Univ. of Notre Dame, USA)
Detailed information (keywords, etc)

2C-4

Title	(Invited Paper) Digital-based Processing In-Memory for Acceleration of Unsupervised Learning
Author	Mohsen Imani (Univ. of California, Irvine, USA)
Detailed information (keywords, etc)

[To Session Table]

Session 2D Machine Learning Techniques for EDA in Analog/Mixed-Signal ICs
Time: 15:30 - 16:00, Tuesday, January 19, 2021
Location: Room 2D
Chairs: Chien-Nan Jimmy Liu (National Chiao Tung Univ., Taiwan), Fan Yang (Fudan Univ., China)

Best Paper Candidate
2D-1

Title	Automatic Surrogate Model Generation and Debugging of Analog/Mixed-Signal Designs Via Collaborative Stimulus Generation and Machine Learning
Author	*Jun Yang Lei, Abhijit Chatterjee (Georgia Tech, USA)
Page	pp. 140 - 145
Detailed information (abstract, keywords, etc)

2D-2

Title	A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization
Author	*Jiangli Huang, Fan Yang, Changhao Yan (Fudan Univ., China), Dian Zhou (UT Dallas, USA), Xuan Zeng (Fudan Univ., China)
Page	pp. 146 - 151
Detailed information (abstract, keywords, etc)

2D-3

Title	Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks
Author	*Xiaohan Gao (Peking Univ., China), Chenhui Deng (Cornell Univ., USA), Mingjie Liu (Univ. of Texas, Austin, USA), Zhiru Zhang (Cornell Univ., USA), David Z. Pan (Univ. of Texas, Austin, USA), Yibo Lin (Peking Univ., China)
Page	pp. 152 - 157
Detailed information (abstract, keywords, etc)

2D-4

Title	Fast and Efficient Constraint Evaluation of Analog Layout using Machine Learning Models
Author	*Tonmoy Dhar, Jitesh Poojary (Univ. of Minnesota, Twin Cities, USA), Yaguang Li (Texas A&M Univ., USA), Kishor Kunal, Meghna Madhusudan, Arvind Kumar Sharma, Susmita Dey Manasi (Univ. of Minnesota, Twin Cities, USA), Jiang Hu (Texas A&M Univ., USA), Ramesh Harjani, Sachin Sapatnekar (Univ. of Minnesota, Twin Cities, USA)
Page	pp. 158 - 163
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2E Innovating Ideas in VLSI Routing Optimization
Time: 15:30 - 16:00, Tuesday, January 19, 2021
Location: Room 2E
Chairs: Yibo Lin (Peking Univ., China), Gengjie Chen (Giga Design Automation, Hong Kong)

Best Paper Award
2E-1

Title	TreeNet: Deep Point Cloud Embedding for Routing Tree Construction
Author	*Wei Li, Yuxiao Qu (Chinese Univ. of Hong Kong, Hong Kong), Gengjie Chen (Giga Design Automation, China), Yuzhe Ma, Bei Yu (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 164 - 169
Detailed information (abstract, keywords, etc)

2E-2

Title	A Unified Printed Circuit Board Routing Algorithm With Complicated Constraints and Differential Pairs
Author	*Ting-Chou Lin, Devon Merrill, Yen-Yi Wu, Chester Holtz, Chung-Kuan Cheng (Univ. of California, San Diego, USA)
Page	pp. 170 - 175
Detailed information (abstract, keywords, etc)

2E-3

Title	Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment
Author	Xiaopeng Zhang, *Dan Zheng, Chak-Wa Pui, Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 176 - 182
Detailed information (abstract, keywords, etc)

2E-4

Title	Boosting Pin Accessibility Through Cell Layout Topology Diversification
Author	*Suwan Kim, Kyeongrok Jo, Taewhan Kim (Seoul National Univ., Republic of Korea)
Page	pp. 183 - 188
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 3A (SS-2) ML-Driven Approximate Computing
Time: 16:00 - 16:30, Tuesday, January 19, 2021
Location: Room 3A
Chairs: Hussam Amrouch (Karlsruhe Inst. of Tech., Germany), Jörg Henkel (Karlsruhe Inst. of Tech., Germany)

3A-1

Title	(Invited Paper) Approximate Computing for ML: State-of-the-art, Challenges and Visions
Author	Georgios Zervakis (Karlsruhe Inst. of Tech.), Hassaan Saadat (Univ. of New South Wales, Austria), Hussam Amrouch (Karlsruhe Inst. of Tech., Germany), Andreas Gerstlauer (Univ. of Texas, Austin, USA), Sri Parameswaran (Univ. of New South Wales, Australia), Jörg Henkel (Karlsruhe Inst. of Tech., Germany)
Page	pp. 189 - 196
Detailed information (keywords, etc)

3A-2

Title	(Invited Paper) ML-Driven Run-time Configurable Approximate circuits
Author	*Georgios Zervakis, Hussam Amrouch, Jörg Henkel (Karlsruhe Inst. of Tech., Germany)
Detailed information (keywords, etc)

3A-3

Title	(Invited Paper) The Art of Creating Approximate Components for Machine Learning
Author	Sri Parameswaran (Univ. of New South Wales, Australia)
Detailed information (keywords, etc)

3A-4

Title	(Invited Paper) Approximate High-Level Synthesis
Author	Seogoo Lee (Cadence, USA), Andreas Gerstlauer (Univ. of Texas, Austin, USA)
Detailed information (keywords, etc)

[To Session Table]

Session 3B Architecture-Level Exploration
Time: 16:00 - 16:30, Tuesday, January 19, 2021
Location: Room 3B
Chairs: Raymond RuiRui Huang (Alibaba Cloud, China), Vassos Soteriou (Cyprus Univ. of Tech., Cyprus)

Best Paper Candidate
3B-1

Title	Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures
Author	*Jan Moritz Joseph (RWTH Aachen Univ., Germany), Lennart Bamberg (GrAI Matter Labs, Netherlands), Geonhwa Jeong, Ruei-Ting Chien (Georgia Tech, USA), Rainer Leupers (RWTH Aachen Univ., Germany), Alberto Garía-Ortiz (Univ. of Bremen, Germany), Tushar Krishna (Georgia Tech, USA), Thilo Pionteck (Otto-von-Guericke Univ. Magdeburg, Germany)
Page	pp. 197 - 203
Detailed information (abstract, keywords, etc)

3B-2

Title	Combining Memory Partitioning and Subtask Generation for Parallel Data Access on CGRAs
Author	*Cheng Li, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei (Tsinghua Univ., China)
Page	pp. 204 - 209
Detailed information (abstract, keywords, etc)

3B-3

Title	A Dynamic Link-latency Aware Cache Replacement Policy (DLRP)
Author	*Yen-Hao Chen, Allen Wu, TingTing Hwang (National Tsing Hua Univ., Taiwan)
Page	pp. 210 - 215
Detailed information (abstract, keywords, etc)

3B-4

Title	Prediction of Register Instance Usage and Time-sharing Register for Extended Register Reuse Scheme
Author	*Shuxin Zhou (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China), Huandong Wang (Loongson, China), Dong Tong (Peking Univ., China)
Page	pp. 216 - 221
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 3C Core Circuits for AI Accelerators
Time: 16:00 - 16:30, Tuesday, January 19, 2021
Location: Room 3C
Chairs: Cheng Zhuo (Zhejiang Univ., China), Grace Li Zhang (Tech. Univ. of Munich, Germany)

3C-1

Title	Residue-Net: Multiplication-free Neural Network by In-situ, No-loss Migration to Residue Number Systems
Author	*Sahand Salamat, Sumiran Shubhi, Behnam Khaleghi, Tajana Rosing (Univ. of California, San Diego, USA)
Page	pp. 222 - 228
Detailed information (abstract, keywords, etc)

3C-2

Title	A Multiple-Precision Multiply and Accumulation Design with Multiply-Add Merged Strategy for AI Accelerating
Author	*Song Zhang, Jiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei (Tsinghua Univ., China)
Page	pp. 229 - 234
Detailed information (abstract, keywords, etc)

3C-3

Title	DeepOpt: Optimized Scheduling of CNN Workloads for ASIC-based Systolic Deep Learning Accelerators
Author	*Susmita Dey Manasi, Sachin S. Sapatnekar (Univ. of Minnesota, Twin Cities, USA)
Page	pp. 235 - 241
Detailed information (abstract, keywords, etc)

3C-4

Title	Value-Aware Error Detection and Correction for SRAM Buffers in Low-Bitwidth, Floating-Point CNN Accelerators
Author	*Jun-Shen Wu, Chi-En Wang, Ren-Shuo Liu (National Tsing Hua Univ., Taiwan)
Page	pp. 242 - 247
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 3D Stochastic and Approximate Computing
Time: 16:00 - 16:30, Tuesday, January 19, 2021
Location: Room 3D
Chairs: Georgios Zervakis (Karlsruhe Inst. of Tech., Germany), Iraklis Anagnostopoulos (Southern Illinois Univ., USA)

3D-1

Title	MIPAC: Dynamic Input-Aware Accuracy Control for Dynamic Auto-Tuning of Iterative Approximate Computing
Author	*Taylor Kemp, Yao Yao, Younghyun Kim (Univ. of Wisconsin-Madison, USA)
Page	pp. 248 - 253
Detailed information (abstract, keywords, etc)

3D-2

Title	Normalized Stability: A Cross-Level Design Metric for Early Termination in Stochastic Computing
Author	*Di Wu, Ruokai Yin, Joshua San Miguel (Univ. of Wisconsin-Madison, USA)
Page	pp. 254 - 259
Detailed information (abstract, keywords, etc)

3D-3

Title	Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing
Author	*Hsuan Hsiao (Univ. of Toronto, Canada), Joshua San Miguel (Univ. of Wisconsin-Madison, USA), Yuko Hara-Azumi (Tokyo Inst. of Tech., Japan), Jason Anderson (Univ. of Toronto, Canada)
Page	pp. 260 - 265
Detailed information (abstract, keywords, etc)

3D-4

Title	An Efficient Approximate Node Merging with an Error Rate Guarantee
Author	Kit Seng Tam, *Chia-Chun Lin (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (Yuan Ze Univ., Taiwan), Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 266 - 271
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 3E Timing Analysis and Timing-Aware Design
Time: 16:00 - 16:30, Tuesday, January 19, 2021
Location: Room 3E
Chairs: Sabya Das (Synopsys Inc, USA), Wenjian Yu (Tsinghua Univ., China)

Best Paper Candidate
3E-1

Title	An Adaptive Delay Model for Timing Yield Estimation under Wide-Voltage Range
Author	*Hao Yan (South-east Univ., China), Xiao Shi (Southeast Univ., USA), Chengzhen Xuan, Peng Cao, Longxing Shi (South-east Univ., China)
Page	pp. 272 - 277
Detailed information (abstract, keywords, etc)

3E-2

Title	ATM: A High Accuracy Extracted Timing Model for Hierarchical Timing Analysis
Author	*Kuan-Ming Lai (NTHU, Taiwan), Tsung-Wei Huang (Univ. of Utah, USA), Pei-Yu Lee (MaxEDA, Taiwan), Tsung-Yi Ho (NTHU, Taiwan)
Page	pp. 278 - 283
Detailed information (abstract, keywords, etc)

3E-3

Title	Mode-wise Voltage-scalable Design with Activation-aware Slack Assignment for Energy Minimization
Author	*TaiYu Cheng (Osaka Univ., Japan), Yutaka Masuda (Nagoya Univ., Japan), Jun Nagayama, Yoichi Momiyama (Socionext, Japan), Jun Chen, Masanori Hashimoto (Osaka Univ., Japan)
Page	pp. 284 - 290
Detailed information (abstract, keywords, etc)

3E-4

Title	A Timing Prediction Framework for Wide Voltage Design with Data Augmentation Strategy
Author	*Peng Cao, Wei Bao, Kai Wang, Tai Yang (Southeast Univ., China)
Page	pp. 291 - 296
Detailed information (abstract, keywords, etc)

Wednesday, January 20, 2021

[To Session Table]

Session 2K Keynote Session II (video and its broadcast via Zoom)
Location: Room K

2K-1

Title	Introduction of Prof. Krishnendu Chakrabarty by Toshihiro Hattori (Renesas Electronics, Japan)
Detailed information (keywords, etc)

2K-2

Title	(Keynote Address) Secure and Trustworthy Microfluidic Biochips: Protecting Medical Diagnostics, Bioassay IP, and DNA Forensics
Author	Krishnendu Chakrabarty (Duke Univ., USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 4A (SS-3) Technological Advancements inside the AI chips, and using the AI Chips
Time: 15:00 - 15:30, Wednesday, January 20, 2021
Location: Room 4A
Chair: Ravikumar Chakaravarthy (Xilinx, USA)

4A-1

Title	(Invited Paper) Energy-Efficient Deep Neural Networks with Mixed-Signal Neurons and Dense-Local and Sparse-Global Connectivity
Author	Baibhab Chatterjee, *Shreyas Sen (Purdue Univ., USA)
Page	pp. 297 - 304
Detailed information (abstract, keywords, etc)

4A-2

Title	(Invited Paper) Merged Logic and Memory Fabrics for AI Workloads
Author	Brian Crafton, Samuel Spetalnick, *Arjit Raychowdhury (Georgia Tech, USA)
Page	pp. 305 - 310
Detailed information (abstract, keywords, etc)

4A-3

Title	(Invited Paper) Vision Control Unit in Fully Self Driving Vehicles using Xilinx MPSoC and Opensource Stack
Author	*Ravikumar Chakaravarthy, Hyun Kwon, Hua Jiang (Xilinx Inc, USA)
Page	pp. 311 - 317
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 4B System-Level Modeling, Simulation, and Exploration
Time: 15:00 - 15:30, Wednesday, January 20, 2021
Location: Room 4B
Chairs: Lei Yang (Univ. of New Mexico, USA), Yaoyao Ye (Shanghai Jiao Tong Univ., China)

4B-1

Title	Constrained Conservative State Symbolic Co-analysis for Ultra-low-power Embedded Systems
Author	*Shashank Hegde, Subhash Sethumurugan (Univ. of Minnesota, USA), Hari Cherupalli (Synopsys, USA), Henry Duwe (Iowa State Univ., USA), John Sartori (Univ. of Minnesota, USA)
Page	pp. 318 - 324
Detailed information (abstract, keywords, etc)

4B-2

Title	Arbitrary and Variable Precision Floating Point Arithmetic Support in Dynamic Binary Translation
Author	*Marie Badaroux, Frédéric Pétrot (Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, France)
Page	pp. 325 - 330
Detailed information (abstract, keywords, etc)

4B-3

Title	Optimizing Temporal Decoupling using Event Relevance
Author	*Lukas Jünger (Institute for Communication Technologies and Embedded Systems, RWTH Aachen, Germany), Carmine Bianco, Kristof Niederholtmeyer, Dietmar Petras (Synopsys GmbH, Germany), Rainer Leupers (Institute for Communication Technologies and Embedded Systems, RWTH Aachen, Germany)
Page	pp. 331 - 337
Detailed information (abstract, keywords, etc)

4B-4

Title	Design Space Exploration of Heterogeneous-Accelerator SoCs with Hyperparameter Optimization
Author	*Thanh Cong (Univ. Rennes, Inria, IRISA, France), François Charot (Inria, Univ. Rennes, IRISA, France)
Page	pp. 338 - 343
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 4C Neural Network Optimizations for Compact AI Inference
Time: 15:00 - 15:30, Wednesday, January 20, 2021
Location: Room 4C
Chairs: Ngai Wong (HKU, Hong Kong), Hai-Bao Chen (Shanghai Jiao Tong Univ., China)

4C-1

Title	DNR: A Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNs
Author	*Souvik Kundu, Mahdi Nazemi, Peter A. Beerel, Massoud Pedram (Univ. of Southern California, USA)
Page	pp. 344 - 350
Detailed information (abstract, keywords, etc)

4C-2

Title	Dynamic Programming Assisted Quantization Approaches for Compressing Normal and Robust DNN Models
Author	*Dingcheng Yang, Wenjian Yu, Haoyuan Mu (Tsinghua Univ., China), Gary Yao (Case Western Reserve Univ., USA)
Page	pp. 351 - 357
Detailed information (abstract, keywords, etc)

4C-3

Title	Accelerate Non-unit Stride Convolutions with Winograd Algorithms
Author	*Junhao Pan, Deming Chen (Univ. of Illinois, Urbana-Champaign, USA)
Page	pp. 358 - 364
Detailed information (abstract, keywords, etc)

4C-4

Title	Efficient Accuracy Recovery in Approximate Neural Networks by Systematic Error Modelling
Author	*Cecilia De la Parra, Andre Guntoro (Robert Bosch GmbH, Germany), Akash Kumar (Technical Univ. of Dresden, Germany)
Page	pp. 365 - 371
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 4D Brain-Inspired Computing
Time: 15:00 - 15:30, Wednesday, January 20, 2021
Location: Room 4D
Chairs: Hussam Amrouch (Karlsruhe Inst. of Tech., Germany), Xunzhao Yin (Zhejiang Univ., China)

Best Paper Candidate
4D-1

Title	Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators
Author	*Sitao Huang (Univ. of Illinois, Urbana-Champaign, USA), Aayush Ankit (Purdue Univ., USA), Plinio Silveira, Rodrigo Antunes (Hewlett Packard Enterprise, Brazil), Sai Rahul Chalamalasetti (Hewlett Packard Enterprise, USA), Izzat El Hajj (American Univ. of Beirut, Lebanon), Dong-Eun Kim (Purdue Univ., USA), Glaucimar Aguiar (Hewlett Packard Enterprise, Brazil), Pedro Bruel (Univ. of São Paulo, Brazil), Sergey Serebryakov, Cong Xu, Can Li, Paolo Faraboschi, John Paul Strachan (Hewlett Packard Enterprise, USA), Deming Chen (Univ. of Illinois, Urbana-Champaign, USA), Kaushik Roy (Purdue Univ., USA), Wen-mei Hwu (Univ. of Illinois, Urbana-Champaign, USA), Dejan Milojicic (Hewlett Packard Enterprise, USA)
Page	pp. 372 - 377
Detailed information (abstract, keywords, etc)

4D-2

Title	A reduced-precision streaming SpMV architecture for Personalized PageRank on FPGA
Author	*Alberto Parravicini, Francesco Sgherzi, Marco Domenico Santambrogio (Politecnico di Milano, Italy)
Page	pp. 378 - 383
Detailed information (abstract, keywords, etc)

4D-3

Title	HyperRec: Efficient Recommender Systems with Hyperdimensional Computing
Author	Yunhui Guo, Mohsen Imani, *Jaeyoung Kang, Sahand Salamat, Justin Morris, Baris Aksanli, Yeseong Kim, Tajana Rosing (UCSD, USA)
Page	pp. 384 - 389
Detailed information (abstract, keywords, etc)

4D-4

Title	Efficient Techniques for Training the Memristor-based Spiking Neural Networks Targeting Better Speed, Energy and Lifetime
Author	*Yu Ma, Pingqiang Zhou (ShanghaiTech Univ., China)
Page	pp. 390 - 395
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 4E Cross-Layer Hardware Security
Time: 15:00 - 15:30, Wednesday, January 20, 2021
Location: Room 4E
Chairs: Song Bian (Kyoto Univ., Japan), Gang Qu (Univ. of Maryland, USA)

Best Paper Candidate
4E-1

Title	PCBench: Benchmarking of Board-Level Hardware Attacks and Trojans
Author	*Huifeng Zhu (Washington Univ. in St.Louis, USA), Xiaolong Guo (Kansas State Univ., USA), Yier Jin (Univ. of Florida, USA), Xuan Zhang (Washington Univ. in St.Louis, USA)
Page	pp. 396 - 401
Detailed information (abstract, keywords, etc)

4E-2

Title	Cache-Aware Dynamic Skewed Tree for Fast Memory Authentication
Author	*Saru Vig (Nanyang Technological Univ., Singapore), Rohan Juneja (Qualcomm, India), Siew-Kei Lam (Nanyang Technological Univ., Singapore)
Page	pp. 402 - 407
Detailed information (abstract, keywords, etc)

4E-3

Title	Automated Test Generation for Hardware Trojan Detection using Reinforcement Learning
Author	*Zhixin Pan, Prabhat Mishra (Univ. of Florida, USA)
Page	pp. 408 - 413
Detailed information (abstract, keywords, etc)

4E-4

Title	On the Impact of Aging on Power Analysis Attacks Targeting Power-Equalized Cryptographic Circuits
Author	*Md Toufiq Hasan Anik (Univ. of Maryland Baltimore County (UMBC), USA), Bijan Fadaeinia, Amir Moradi (Ruhr Univ. Bochum, Germany), Naghmeh Karimi (Univ. of Maryland Baltimore County (UMBC), USA)
Page	pp. 414 - 420
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 5A (DF-1): New-Principle Computer
Time: 15:30 - 16:00, Wednesday, January 20, 2021
Location: Room 5A
Organizer/Chair: Chihiro Yoshimura (Hitachi, Japan), Organizer: Noriyuki Miura (Osaka Univ., Japan)

5A-1

Title	(Designers' Forum) Challenges in Ultra-High-Performance Low-Power Computing towards the Post Moore Era ~ A Computer Architecture Perspective ~
Author	Koji Inoue (Kyushu Univ., Japan)
Detailed information (abstract, keywords, etc)

5A-2

Title	(Designers' Forum) CMOS Annealing Machine for Combinatorial Optimization Problems
Author	Masanao Yamaoka (Hitachi, Japan)
Detailed information (abstract, keywords, etc)

5A-3

Title	(Designers' Forum) Massively Parallel Noisy Intermediate Scale Quantum Computer
Author	Ryuta Tsuchiya (Hitachi, Japan)
Detailed information (abstract, keywords, etc)

5A-4

Title	(Designers' Forum) Designing Functional Neuronal Networks with Living Cells
Author	Hideaki Yamamoto, Ayumi Hirano-Iwata, Shigeo Sato (Tohoku Univ., Japan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 5B Embedded Operating Systems and Information Retrieval
Time: 15:30 - 16:00, Wednesday, January 20, 2021
Location: Room 5B
Chairs: Tony Givargis (Univ. of California, Irvine, USA), Chengmo Yang (Univ. of Delaware, USA)

5B-1

Title	Energy-Performance Co-Management of Mixed-Sensitivity Workloads on Heterogeneous Multi-core Systems
Author	*Elham Shamsa, Anil Kanduri (Univ. of Turku, Finland), Amir M. Rahmani (Univ. of California, USA), Pasi Liljeberg (Univ. of Turku, Finland)
Page	pp. 421 - 427
Detailed information (abstract, keywords, etc)

5B-2

Title	Optimizing Inter-Core Data-Propagation Delays in Industrial Embedded Systems under Partitioned Scheduling
Author	Lamija Hasanagić, *Tin Vidović, Saad Mubeen, Mohammad Ashjaei (Mälardalen Univ., Sweden), Matthias Becker (Royal Inst. of Tech., Sweden)
Page	pp. 428 - 434
Detailed information (abstract, keywords, etc)

5B-3

Title	LiteIndex: Memory-Efficient Schema-Agnostic Indexing for JSON documents in SQLite
Author	*Siqi Shang, Qihong Wu, Tianyu Wang, Zili Shao (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 435 - 440
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 5C (SS-4) Security Issues in AI and Their Impacts on Hardware Security
Time: 15:30 - 16:00, Wednesday, January 20, 2021
Location: Room 5C
Chairs: Jiliang ZHANG (Hunan Univ., China), Lingjuan Wu (Huazhong Agricultural Univ., China)

5C-1

Title	(Invited Paper) Micro-architectural Cache Side-Channel Attacks and Countermeasures
Author	*Chaoqun Shen, Congcong Chen, Jiliang Zhang (Hunan Univ., China)
Page	pp. 441 - 448
Detailed information (abstract, keywords, etc)

5C-2

Title	(Invited Paper) Security of Neural Networks from Hardware Perspective: A Survey and Beyond
Author	*Qian Xu (Univ. of Maryland College Park, USA), Md Tanvir Arafin (Morgan State Univ., USA), Gang Qu (Univ. of Maryland College Park, USA)
Page	pp. 449 - 454
Detailed information (abstract, keywords, etc)

5C-3

Title	(Invited Paper) Learning Assisted Side Channel Delay Test for Detection of Recycled ICs
Author	*Ashkan Vakil (George Mason Univ., USA), Farzad Niknia (Univ. of Maryland Baltimore County, USA), Ali Mirzaeian, Avesta Sasan (George Mason Univ., USA), Naghmeh Karimi (Univ. of Maryland Baltimore County, USA)
Page	pp. 455 - 462
Detailed information (abstract, keywords, etc)

5C-4

Title	(Invited Paper) ML-augmented Methodology for Fast Thermal Side-Channel Emission Analysis
Author	*Norman Chang, Deqi Zhu, Lang Lin, Dinesh Selvakumaran, Jimin Wen, Stephen Pan, Wenbo Xia, Hua Chen, Calvin Chow (Ansys, USA), Gary Chen (National Taiwan Univ., Taiwan)
Page	pp. 463 - 468
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 5D Advances in Logic and High-level Synthesis
Time: 15:30 - 16:00, Wednesday, January 20, 2021
Location: Room 5D
Chairs: Jun Zhou (Univ. of Electronic Science and Tech. of China, China), Grace Li Zhang (Tech. Univ. of Munich, Germany)

Best Paper Candidate
5D-1

Title	1^st-Order to 2^nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method
Author	*Li-Cheng Zheng (National Central Univ., Taiwan), Hao-Ju Chang, Yung-Chih Chen (Yuan Ze Univ., Taiwan), Jing-Yang Jou (National Central Univ., Taiwan)
Page	pp. 469 - 474
Detailed information (abstract, keywords, etc)

5D-2

Title	A Novel Technology Mapper for Complex Universal Gates
Author	Meng-Che Wu, *Ai Quoc Dao (National Chung Cheng Univ., Taiwan), Mark Po-Hung Lin (National Chiao Tung Univ., Taiwan)
Page	pp. 475 - 480
Detailed information (abstract, keywords, etc)

5D-3

Title	High-Level Synthesis of Transactional Memory
Author	*Omar Ragheb, Jason H. Anderson (Univ. of Toronto, Canada)
Page	pp. 481 - 486
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 5E Hardware-Oriented Threats and Solutions in Neural Networks
Time: 15:30 - 16:00, Wednesday, January 20, 2021
Location: Room 5E
Chairs: Jiaji He (Tsinghua Univ., China), Tanvir Arafin (Morgan State Univ., USA)

5E-1

Title	VADER: Leveraging the Natural Variation of Hardware to Enhance Adversarial Attack
Author	*Hao Lv (Chinese Academy of Sciences, China), Bing Li (Capital Normal Univ., China), Ying Wang, Cheng Liu, Lei Zhang (Chinese Academy of Sciences, China)
Page	pp. 487 - 492
Detailed information (abstract, keywords, etc)

5E-2

Title	Entropy-Based Modeling for Estimating Adversarial Bit-flip Attack Impact on Binarized Neural Network
Author	*Navid Khoshavi (Florida Polytechnic Univ., USA), Saman Sargolzaei (Univ. of Tennessee at Martin, USA), Yu Bi (Univ. of Rhode Island, USA), Arman Roohi (UNIVERSITY of NEBRASKA–LINCOLN, USA)
Page	pp. 493 - 498
Detailed information (abstract, keywords, etc)

5E-3

Title	A Low Cost Weight Obfuscation Scheme for Security Enhancement of ReRAM Based Neural Network Accelerators
Author	Yuhang Wang, *Song Jin (North China Electric Power Univ., China), Tao Li (Univ. of Florida, USA)
Page	pp. 499 - 504
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 6A (DF-2): Advanced Sensing Technology and Automotive Application
Time: 16:00 - 16:30, Wednesday, January 20, 2021
Location: Room 6A
Organizer/Chair: Masaki Sakakibara (Sony Semiconductor Solutions, Japan), Organizer: Yuji Ishikawa (Toshiba, Japan)

6A-1

Title	(Designers' Forum) A 32x32-Pixel Global Shutter CMOS THz Imager with VCO-Based ADC
Author	Yuri Kanazawa (Hokkaido Univ., Japan)
Detailed information (abstract, keywords, etc)

6A-2

Title	(Designers' Forum) Design Strategies of a Vertical Avalanche Photodiode (VAPD), Photon Count Equalizer (PCE) and Subrange Codes (SRC) for an Ultra-long Range (>250 m) Direct-/indirect Mixed Time-of-Flight (TOF) System with Reconfigurable Resolution
Author	T. Okino, M. Ishii, Y. Sakata, S. Yamada, A. Inoue, S. Kasuga, M. Takemoto, M. Tamaru, H. Koshida, M. Usuda, T. Kunikyo, Y. Yuasa, T. Kabe, S. Saito, Y. Sugiura, K. Nakanishi, N. Torazawa, T. Shirono, Y. Nose, S. Koyama, M. Mori, Y. Hirose, M. Sawada, A. Odagawa, T. Tanaka (Panasonic, Japan)
Detailed information (abstract, keywords, etc)

6A-3

Title	(Designers' Forum) A 240×192-Pixel 225m-Range Automotive LiDAR SoC Using a 40ch Voltage/Time Dual-Data-Converter-Based AFE
Author	Satoshi Kondo (Toshiba, Japan)
Detailed information (abstract, keywords, etc)

6A-4

Title	(Designers' Forum) Visconti^TM: Edge AI Processor for Automotive Application
Author	Yutaka Yamada (Toshiba, Japan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 6B Advanced Optimizations for Embedded Systems
Time: 16:00 - 16:30, Wednesday, January 20, 2021
Location: Room 6B
Chairs: Qi Zhu (Northwestern Univ., USA), Xiaolin Xu (Northeastern Univ., USA)

6B-1

Title	Puncturing the memory wall: Joint optimization of network compression with approximate memory for ASR application
Author	*Qin Li (Tsinghua Univ., China), Peiyan Dong (Northeastern Univ., USA), Zijie Yu, Changlu Liu, Fei Qiao (Tsinghua Univ., China), Yanzhi Wang (Northeastern Univ., USA), Huazhong Yang (Tsinghua Univ., China)
Page	pp. 505 - 511
Detailed information (abstract, keywords, etc)

6B-2

Title	Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays
Author	*Satyabrata Sarangi, Bevan Baas (Univ. of California, Davis, USA)
Page	pp. 512 - 517
Detailed information (abstract, keywords, etc)

6B-3

Title	A Decomposition-Based Synthesis Algorithm for Sparse Matrix-Vector Multiplication in Parallel Communication Structure
Author	*Mingfei Yu, Ruitao Gao, Masahiro Fujita (Univ. of Tokyo, Japan)
Page	pp. 518 - 523
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 6C Design and Learning of Logic Circuits and Systems
Time: 16:00 - 16:30, Wednesday, January 20, 2021
Location: Room 6C
Chairs: Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong), Yung-Chih Chen (Yuan Ze Univ. Taiwan, Taiwan)

6C-1

Title	Learning Boolean Circuits from Examples for Approximate Logic Synthesis
Author	*Sina Boroumand, Christos-Savvas Bouganis, George Constantinides (Imperial College London, UK)
Page	pp. 524 - 529
Detailed information (abstract, keywords, etc)

6C-2

Title	Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization
Author	*Walter Lau Neto (Univ. of Utah, USA), Matheus Trevisan Moreira (Chronos Tech, USA), Luca Amaru (Synopsys, USA), Cunxi Yu, Pierre-Emmanuel Gaillardon (Univ. of Utah, USA)
Page	pp. 530 - 535
Detailed information (abstract, keywords, etc)

6C-3

Title	Exploiting HLS-Generated Multi-Version Kernels to Improve CPU-FPGA Cloud Systems
Author	Bernardo Neuhaus Lignati, Michael Guilherme Jordan, Guilherme Korol (Institute of Informatics - Federal Univ. of Rio Grande do Sul (UFRGS), Brazil), Mateus Beck Rutzig (Electronics and Computing Department - Federal Univ. of Santa Maria (UFSM), Brazil), *Antonio Carlos Schneider Beck (Institute of Informatics - Federal Univ. of Rio Grande do Sul (UFRGS), Brazil)
Page	pp. 536 - 541
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 6D Hardware Locking and Obfuscation
Time: 16:00 - 16:30, Wednesday, January 20, 2021
Location: Room 6D
Chairs: Xueyan Wang (Beihang Univ., China), Yier Jin (Univ. of Florida, USA)

6D-1

Title	Area Efficient Functional Locking through Coarse Grained Runtime Reconfigurable Architectures
Author	*Jianqi Chen, Benjamin Carrion Schafer (Univ. of Texas, Dallas, USA)
Page	pp. 542 - 547
Detailed information (abstract, keywords, etc)

6D-2

Title	ObfusX: Routing Obfuscation with Explanatory Analysis of a Machine Learning Attack
Author	*Wei Zeng, Azadeh Davoodi (Univ. of Wisconsin-Madison, USA), Rasit Onur Topaloglu (IBM, USA)
Page	pp. 548 - 554
Detailed information (abstract, keywords, etc)

6D-3

Title	Breaking Analog Biasing Locking Techniques via Re-Synthesis
Author	*Julian Leonhard, Mohamed Elshamy, Marie-Minerve Louërat, Haralampos-G. Stratigopoulos (Sorbonne Université, CNRS, LIP6, France)
Page	pp. 555 - 560
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 6E Efficient Solutions for Emerging Technologies
Time: 16:00 - 16:30, Wednesday, January 20, 2021
Location: Room 6E
Chairs: Xueqing Li (Tsinghua Univ., China), Sangyoung Park (TU Berlin, Germany)

6E-1

Title	Energy and QoS-Aware Dynamic Reliability Management of IoT Edge Computing Systems
Author	*Kazim Ergun (Univ. of California, San Diego, USA), Raid Ayoub, Pietro Mercati (Intel, USA), Dan Liu, Tajana Rosing (Univ. of California, San Diego, USA)
Page	pp. 561 - 567
Detailed information (abstract, keywords, etc)

6E-2

Title	Light: A Scalable and Efficient Wavelength-Routed Optical Networks-On-Chip Topology
Author	*Zhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann (Tech. Univ. of Munich, Germany)
Page	pp. 568 - 573
Detailed information (abstract, keywords, etc)

Best Paper Candidate
6E-3

Title	One-Pass Synthesis for Field-coupled Nanocomputing Technologies
Author	*Marcel Walter (Univ. of Bremen, Germany), Winston Haaswijk (Cadence Design Systems, USA), Robert Wille (Johannes Kepler Univ. Linz, Austria), Frank Sill Torres (Department for the Resilience of Maritime Systems, DLR, Germany), Rolf Drechsler (Univ. of Bremen, Germany)
Page	pp. 574 - 580
Detailed information (abstract, keywords, etc)

Thursday, January 21, 2021

[To Session Table]

Session 3K Keynote Session III (video and its broadcast via Zoom)
Location: Room K

3K-1

Title	Introduction of Prof. Jun Mitani by Toshihiro Hattori (Renesas Electronics, Japan)
Detailed information (keywords, etc)

3K-2

Title	(Keynote Address) The Frontier of Origami Science
Author	Jun Mitani (Univ. of Tsukuba, Japan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 7A (SS-5) Platform-Specific Neural Network Acceleration
Time: 15:00 - 15:30, Thursday, January 21, 2021
Location: Room 7A
Chair: Yanzhi Wang (Northeastern Univ., USA)

7A-1

Title	(Invited Paper) Real-Time Mobile Acceleration of DNNs: From Computer Vision to Medical Applications
Author	*Hongjia Li, Geng Yuan (Northeastern Univ., USA), Wei Niu (College of William and Mary, USA), Yuxuan Cai, Mengshu Sun, Zhengang Li (Northeastern Univ., USA), Bin Ren (College of William and Mary, USA), Xue Lin, Yanzhi Wang (Northeastern Univ., USA)
Page	pp. 581 - 586
Detailed information (abstract, keywords, etc)

7A-2

Title	(Invited Paper) Dynamic Neural Network to Enable Run-Time Trade-off between Accuracy and Latency
Author	*Li Yang, Deliang Fan (Arizona State Univ., USA)
Page	pp. 587 - 592
Detailed information (abstract, keywords, etc)

7A-3

Title	(Invited Paper) When Machine Learning Meets Quantum Computer: Network-Circuit Co-Design via Quantum-Aware Neural Architecture Search
Author	*Weiwen Jiang (Univ. of Notre Dame, USA), Jinjun Xiong (IBM, USA), Yiyu Shi (Univ. of Notre Dame, USA)
Page	pp. 593 - 598
Detailed information (abstract, keywords, etc)

7A-4

Title	(Invited Paper) Improving Efficiency in Neural Network Acceleration using Operands Hamming Distance Optimization
Author	*Meng Li, Yilei Li, Vikas Chandra (Facebook, USA)
Page	pp. 599 - 604
Detailed information (abstract, keywords, etc)

7A-5

Title	(Invited Paper) Lightweight Run-Time Working Memory Compression for Deployment of Deep Neural Networks on Resource-Constrained MCUs
Author	*Zhepeng Wang, Yawen Wu, Zhenge Jia (Univ. of Pittsburgh, USA), Yiyu Shi (Univ. of Notre Dame, USA), Jingtong Hu (Univ. of Pittsburgh, USA)
Page	pp. 607 - 614
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 7B Toward Energy-Efficient Embedded Systems
Time: 15:00 - 15:30, Thursday, January 21, 2021
Location: Room 7B
Chairs: Shiyan Hu (Univ. of Southampton, UK), Xiang Chen (George Mason Univ., USA)

7B-1

Title	EHDSktch: A Generic Low Power Architecture for Sketching in Energy Harvesting Devices
Author	*Priyanka Singla (Indian Inst. of Tech. Delhi, India), Chandran Goodchild (Univ. of Freiburg, Germany), Smruti R. Sarangi (Indian Inst. of Tech. Delhi, India)
Page	pp. 615 - 620
Detailed information (abstract, keywords, etc)

7B-2

Title	Energy-Aware Design Methodology for Myocardial Infarction Detection on Low-Power Wearable Devices
Author	*Mohanad Odema, Nafiul Rashid, Mohammad Abdullah Al Faruque (Univ. of California, Irvine, USA)
Page	pp. 621 - 626
Detailed information (abstract, keywords, etc)

7B-3

Title	Power-Efficient Layer Mapping for CNNs on Integrated CPU and GPU Platforms: A Case Study
Author	*Tian Wang (Nanjing Univ. of Science and Tech., China), Kun Cao (Jinan Univ., China), Junlong Zhou, Gongxuan Zhang, Xiji Wang (Nanjing Univ. of Science and Tech., China)
Page	pp. 627 - 632
Detailed information (abstract, keywords, etc)

7B-4

Title	A Write-friendly Arithmetic Coding Scheme for Achieving Energy-Efficient Non-Volatile Memory Systems
Author	*Yi-Shen Chen (National Taiwan Univ., Taiwan), Chun-Feng Wu (National Taiwan Univ./Academia Sinica, Taiwan), Yuan-Hao Chang (Academia Sinica, Taiwan), Tei-Wei Kuo (National Taiwan Univ./City Univ. of Hong Kong, Taiwan)
Page	pp. 633 - 638
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 7C Software and System Support for Nonvolatile Memory
Time: 15:00 - 15:30, Thursday, January 21, 2021
Location: Room 7C
Chairs: Zhaoyan Shen (Shandong Univ., China), In-chao Lin (National Cheng Kung Univ., Taiwan)

7C-1

Title	DP-Sim: A Full-stack Simulation Infrastructure for Digital Processing In-Memory Architectures
Author	*Minxuan Zhou (Univ. of California, San Diego, USA), Mohsen Imani (Univ. of California, Irvine, USA), Yeseong Kim (Daegu Gyeongbuk Inst. of Science and Tech., Republic of Korea), Saransh Gupta, Tajana Rosing (Univ. of California, San Diego, USA)
Page	pp. 639 - 644
Detailed information (abstract, keywords, etc)

7C-2

Title	SAC: A Stream Aware Write Cache Scheme for Multi-Streamed Solid State Drives
Author	*Bo Zhou, Chuanming Ding, Yina Lv (East China Normal Univ., China), Chun Xue (City Univ. of Hong Kong, Hong Kong), Qingfeng Zhuge, Edwin Sha, Liang Shi (East China Normal Univ., China)
Page	pp. 645 - 650
Detailed information (abstract, keywords, etc)

7C-3

Title	Providing Plug N' Play for Processing-in-Memory Accelerators
Author	Paulo Cesar Santos, Bruno E. Forlin, *Luigi Carro (Federal Univ. of Rio Grande do Sul, Brazil)
Page	pp. 651 - 656
Detailed information (abstract, keywords, etc)

7C-4

Title	Aging Aware Request Scheduling for Non-Volatile Main Memory
Author	Shihao Song, *Anup Das (Drexel Univ., USA), Onur Mutlu (ETH Zurich, Switzerland), Nagarajan Kandasamy (Drexel Univ., USA)
Page	pp. 657 - 664
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 7D Learning-Driven VLSI Layout Automation Techniques
Time: 15:00 - 15:30, Thursday, January 21, 2021
Location: Room 7D
Chairs: Jinwook Jung (IBM Research, USA), Daijoon Hyun (Cheongju Univ., Republic of Korea)

7D-1

Title	Placement for Wafer-Scale Deep Learning Accelerator
Author	*Benzheng Li, Qi Du, Dingcheng Liu, Jingchong Zhang (Xidian Univ., China), Gengjie Chen (Giga Design Automation, China), Hailong You (Xidian Univ., China)
Page	pp. 665 - 670
Detailed information (abstract, keywords, etc)

7D-2

Title	Net²: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation
Author	*Zhiyao Xie (Duke Univ., USA), Rongjian Liang (Texas A&M Univ., USA), Xiaoqing Xu (ARM Inc, USA), Jiang Hu (Texas A&M Univ., USA), Yixiao Duan, Yiran Chen (Duke Univ., USA)
Page	pp. 671 - 677
Detailed information (abstract, keywords, etc)

7D-3

Title	Machine Learning-based Structural Pre-route Insertability Prediction and Improvement with Guided Backpropagation
Author	*Tao-Chun Yu, Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan), Hsien-Shih Chiu, Kai-Shun Hu, Chin-Hsiung Hsu (Synopsys Taiwan, Taiwan), Philip Hui-Yuh Tai (Synopsys, USA), Cindy Chin-Fang Shen (Synopsys Taiwan, Taiwan)
Page	pp. 678 - 683
Detailed information (abstract, keywords, etc)

7D-4

Title	Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes
Author	*Haoxing Ren, Matthew Fojtik (Nvidia, USA)
Page	pp. 684 - 689
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 7E DNN-Based Physical Analysis and DNN Accelerator Design
Time: 15:00 - 15:30, Thursday, January 21, 2021
Location: Room 7E
Chairs: Fan Yang (Fudan Univ., China), Zuochang Ye (Tsinghua Univ., China)

7E-1

Title	Thermal and IR Drop Analysis Using Convolutional Encoder-Decoder Networks
Author	*Vidya A. Chhabria (Univ. of Minnesota, USA), Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain (Qualcomm Technologies Inc, India), Sachin S. Sapatnekar (Univ. of Minnesota, USA)
Page	pp. 690 - 696
Detailed information (abstract, keywords, etc)

7E-2

Title	GRA-LPO: Graph Convolution Based Leakage Power Optimization
Author	*Uday Mallappa, Chung-Kuan Cheng (Univ. of California, San Diego, USA)
Page	pp. 697 - 702
Detailed information (abstract, keywords, etc)

7E-3

Title	DEF: Differential Encoding of Featuremaps for Low Power Convolutional Neural Network Accelerators
Author	*Alexander Montgomerie-Corcoran, Christos-Savvas Bouganis (Imperial College London, UK)
Page	pp. 703 - 708
Detailed information (abstract, keywords, etc)

7E-4

Title	Temperature-Aware Optimization of Monolithic 3D Deep Neural Network Accelerators
Author	*Prachi Shukla, Sean S. Nemtzow (Boston Univ., USA), Vasilis F. Pavlidis (Univ. of Manchester, UK), Emre Salman (Stony Brook Univ., USA), Ayse K. Coskun (Boston Univ., USA)
Page	pp. 709 - 714
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 8A (DF-3): Emerging Open Design Platform
Time: 15:30 - 16:00, Thursday, January 21, 2021
Location: Room 8A
Organizer/Chair: Yuji Ishikawa (Toshiba, Japan), Organizer: Noriyuki Miura (Osaka Univ., Japan)

8A-1

Title	(Designers' Forum) Impact of Open Source and NDA-free on LSI Design and Fabrication
Author	Junichi Akita (Kanazawa Univ., Japan)
Detailed information (abstract, keywords, etc)

8A-2

Title	(Designers' Forum) Simulated Bifurcation Algorithm for Large-scale Combinatorial Optimization
Author	Hayato Goto (Toshiba, Japan)
Detailed information (abstract, keywords, etc)

8A-3

Title	(Designers' Forum) Towards a Hardware Synthesis Environment from the Functional Language Elixir
Author	Hideki Takase (Kyoto Univ./JST PRESTO, Japan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 8B Embedded Neural Networks and File Systems
Time: 15:30 - 16:00, Thursday, January 21, 2021
Location: Room 8B
Chairs: Zili Shao (Chinese Univ. of Hong Kong, Hong Kong), Mohammad Al Faruque (Univ. of California, Irvine, USA)

Best Paper Candidate
8B-1

Title	Gravity: An Artificial Neural Network Compiler for Embedded Applications
Author	*Tony Givargis (Univ. of California, Irvine, USA)
Page	pp. 715 - 721
Detailed information (abstract, keywords, etc)

8B-2

Title	A Self-Test Framework for Detecting Fault-induced Accuracy Drop in Neural Network Accelerators
Author	*Fanruo Meng, Fateme Hosseini, Chengmo Yang (Univ. of Delaware, USA)
Page	pp. 722 - 727
Detailed information (abstract, keywords, etc)

8B-3

Title	Facilitating the Efficiency of Secure File Data and Metadata Deletion on SMR-based Ext4 File System
Author	*Ping-Xiang Chen (National Tsing Hua Univ., Taiwan), Shuo-Han Chen (National Taipei Univ. of Tech., Taiwan), Yuan-Hao Chang, Yu-Pei Liang (Academia Sinica, Taiwan), Wei-Kuan Shih (National Tsing Hua Univ., Taiwan)
Page	pp. 728 - 733
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 8C (SS-6) Design Automation for Future Autonomy
Time: 15:30 - 16:00, Thursday, January 21, 2021
Location: Room 8C
Chair: Qi Zhu (Northwestern Univ., USA)

8C-1

Title	(Invited Paper) Efficient Computing Platform Design for Autonomous Driving Systems
Author	*Shuang Liang, Xuefei Ning, Jincheng Yu, Kaiyuan Guo (Tsinghua Univ., China), Tianyi Lu, Changcheng Tang (Novauto, China), Shulin Zeng, Yu Wang, Diange Yang, Huazhong Yang (Tsinghua Univ., China)
Page	pp. 734 - 741
Detailed information (abstract, keywords, etc)

8C-2

Title	(Invited Paper) On Designing Computing Systems for Autonomous Vehicles: a PerceptIn Case Study
Author	*Bo Yu (PerceptIn, USA), Jie Tang (South China Univ. of Tech., China), Shaoshan Liu (PerceptIn, USA)
Page	pp. 742 - 747
Detailed information (abstract, keywords, etc)

8C-3

Title	(Invited Paper) Runtime Software Selection for Adaptive Automotive Systems
Author	Chia-Ching Fu, Ben-Hau Chia, *Chung-Wei Lin (National Taiwan Univ., Taiwan)
Page	pp. 748 - 752
Detailed information (abstract, keywords, etc)

8C-4

Title	(Invited Paper) Safety-Assured Design and Adaptation of Learning-Enabled Autonomous Systems
Author	*Qi Zhu, Chao Huang, Ruochen Jiao, Shuyue Lan, Hengyi Liang, Xiangguo Liu, Yixuan Wang, Zhilu Wang, Shichao Xu (Northwestern Univ., USA)
Page	pp. 753 - 760
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 8D Emerging Hardware Verification
Time: 15:30 - 16:00, Thursday, January 21, 2021
Location: Room 8D
Chairs: He Li (Univ. of Cambridge, UK), Daniel Grosse (Johannes Kepler Univ. Linz, Austria)

8D-1

Title	System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations
Author	*Muhammad Hassan (Univ. of Bremen, Germany), Daniel Große (Johannes Kepler Univ. Linz / DFKI GmbH, Austria), Rolf Drechsler (Univ. of Bremen / DFKI GmbH, Germany)
Page	pp. 761 - 766
Detailed information (abstract, keywords, etc)

8D-2

Title	Random Stimuli Generation for the Verification of Quantum Circuits
Author	*Lukas Burgholzer, Richard Kueng, Robert Wille (Johannes Kepler Univ. Linz, Austria)
Page	pp. 767 - 772
Detailed information (abstract, keywords, etc)

8D-3

Title	Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models
Author	Chrysostomos Chatzigeorgiou, Dimitrios Garyfallou, *George Floros, Nestor Evmorfopoulos, George Stamoulis (Univ. of Thessaly, Greece)
Page	pp. 773 - 778
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 8E Optimization and Mapping Methods for Quantum Technologies
Time: 15:30 - 16:00, Thursday, January 21, 2021
Location: Room 8E
Chairs: Debjyoti Bhattacharjee (imec, Belgium), Rudy Raymond H.P. (IBM Research - Tokyo, Japan)

8E-1

Title	Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits
Author	*Eleonora Testa, Siang-Yun Lee, Heinz Riener, Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 779 - 785
Detailed information (abstract, keywords, etc)

8E-2

Title	Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures
Author	*Atsushi Matsuo (IBM Research - Tokyo/Ritsumeikan Univ., Japan), Wakaki Hattori, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Page	pp. 786 - 791
Detailed information (abstract, keywords, etc)

8E-3

Title	Exploiting Quantum Teleportation in Quantum Circuit Mapping
Author	*Stefan Hillmich, Alwin Zulehner, Robert Wille (Johannes Kepler Univ. Linz, Austria)
Page	pp. 792 - 797
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 9A (DF-4): Technological Utilization in COVID-19 Pandemic
Time: 16:00 - 16:30, Thursday, January 21, 2021
Location: Room 9A
Organizer/Chair: Koichiro Yamashita (Fujitsu R&D Center, Japan)

9A-1

Title	(Designers' Forum) ToF 3D Object Detection: Crowd Status Monitoring with Protected Privacy
Author	Wang Weihang, Ge Hao (Data Miracle Intelligent Technology, China), Liu Peilin (Shanghai Jiao Tong Univ., China)
Detailed information (abstract, keywords, etc)

9A-2

Title	(Designers' Forum) Smartphone App to Support Team Communication in Remote Work
Author	Satomi Tsuji (Hitachi, Japan)
Detailed information (abstract, keywords, etc)

9A-3

Title	(Designers' Forum) Re-ID Technology: Chase of the Contact Person with Protected Privacy
Author	Chang Zhigang, Zheng Shibao (Shanghai Jiao Tong Univ., China)
Detailed information (abstract, keywords, etc)

9A-4

Title	(Designers' Forum) Actlyzer :Video-based Behavior Analysis Technology
Author	Toshiaki Wakama, Sho Iwasaki (Fujitsu Labs., Japan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 9B Emerging System Architectures for Edge-AI
Time: 16:00 - 16:30, Thursday, January 21, 2021
Location: Room 9B
Chairs: Sai Manoj Pudukotai Dinakarrao (George Mason Univ., USA), Shinya Takamaeda-Yamazaki (Univ. of Tokyo, Japan)

Best Paper Candidate
9B-1

Title	Hardware-Aware NAS Framework with Layer Adaptive Scheduling on Embedded System
Author	*Chuxi Li, Xiaoya Fan, Shengbing Zhang (Northwestern Polytechnical Univ./Engineering Research Center of Embedded System Integration, Ministry of Education, China), Zhao Yang, Miao Wang (Northwestern Polytechnical Univ., China), Danghui Wang, Meng Zhang (Northwestern Polytechnical Univ./Engineering Research Center of Embedded System Integration, Ministry of Education, China)
Page	pp. 798 - 805
Detailed information (abstract, keywords, etc)

9B-2

Title	Dataflow-Architecture Co-Design for 2.5D DNN Accelerators using Wireless Network-on-Package
Author	*Robert Guirado (Univ. Politècnica de Catalunya, Spain), Hyoukjun Kwon (Georgia Tech, USA), Sergi Abadal, Eduard Alarcon (Univ. Politècnica de Catalunya, Spain), Tushar Krishna (Georgia Tech, USA)
Page	pp. 806 - 812
Detailed information (abstract, keywords, etc)

9B-3

Title	Block-Circulant Neural Network Accelerator Featuring Fine-Grained Frequency-Domain Quantization and Reconfigurable FFT Modules
Author	*Yifan He, Jinshan Yue, Yongpan Liu, Huazhong Yang (Tsinghua Univ., China)
Page	pp. 813 - 818
Detailed information (abstract, keywords, etc)

9B-4

Title	BatchSizer: Power-Performance Trade-off for DNN Inference
Author	*Seyed Morteza Nabavinejad (Institute for Research in Fundamental Sciences (IPM), Iran), Sherief Reda (Brown Univ., USA), Masoumeh Ebrahimi (Royal Inst. of Tech., Sweden)
Page	pp. 819 - 824
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 9C (SS-7) Cutting-Edge EDA Techniques for Advanced Process Technologies
Time: 16:00 - 16:30, Thursday, January 21, 2021
Location: Room 9C
Chairs: Wenjian Yu (Tsinghua Univ., China), Lifeng Wu (Huada Empyrean, China)

9C-1

Title	(Invited Paper) Deep Learning for Mask Synthesis and Verification: A Survey
Author	*Yibo Lin (Peking Univ., China)
Page	pp. 825 - 832
Detailed information (abstract, keywords, etc)

9C-2

Title	(Invited Paper) Physical Synthesis for Advanced Neural Network Processors
Author	*Zhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma (Chinese Univ. of Hong Kong, Hong Kong), Yibo Lin (Peking Univ., China), Bei Yu (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 833 - 840
Detailed information (abstract, keywords, etc)

9C-3

Title	(Invited Paper) Advancements and Challenges on Parasitic Extraction for Advanced Process Technologies
Author	*Wenjian Yu, Mingye Song, Ming Yang (Tsinghua Univ., China)
Page	pp. 841 - 846
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 9D (SS-8) Robust and Reliable Memory Centric Computing at Post-Moore
Time: 16:00 - 16:30, Thursday, January 21, 2021
Location: Room 9D
Chairs: Grace Li Zhang (Tech. Univ. of Munich, Germany), Cheng Zhuo (Zhejiang Univ., China)

9D-1

Title	(Invited Paper) Reliability-Aware Training and Performance Modeling for Processing-In-Memory Systems
Author	*Hanbo Sun, Zhenhua Zhu, Yi Cai, Shulin Zeng, Kaizhong Qiu, Yu Wang, Huazhong Yang (Tsinghua Univ., China)
Page	pp. 847 - 852
Detailed information (abstract, keywords, etc)

9D-2

Title	(Invited Paper) Robustness of Neuromorphic Computing with RRAM-based Crossbars and Optical Neural Networks
Author	*Grace Li Zhang, Bing Li, Ying Zhu (Tech. Univ. of Munich, Germany), Tianchen Wang, Yiyu Shi (Univ. of Notre Dame, USA), Xunzhao Yin, Cheng Zhuo (Zhejiang Univ., China), Huaxi Gu (Xidian Univ., China), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Ulf Schlichtmann (Tech. Univ. of Munich, Germany)
Page	pp. 853 - 858
Detailed information (abstract, keywords, etc)

9D-3

Title	(Invited Paper) Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search
Author	*Zheyu Yan (Univ. of Notre Dame, USA), Da-Cheng Juan (National Tsing Hua Univ., Taiwan), Xiaobo Juan, Yiyu Shi (Univ. of Notre Dame, USA)
Page	pp. 859 - 864
Detailed information (abstract, keywords, etc)

9D-4

Title	(Invited Paper) A Physical-Aware Framework for Memory Network Design Space Exploration
Author	Tianhao Shen, Di Gao, Li Zhang (Zhejiang Univ., China), Jishen Zhao (Univ. of California, San Diego, USA), *Cheng Zhuo (Zhejiang Univ., China)
Page	pp. 865 - 871
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 9E Design for Manufacturing and Soft Error Tolerance
Time: 16:00 - 16:30, Thursday, January 21, 2021
Location: Room 9E
Chairs: Yongfu Li (Shanghai Jiao Tong Univ., China), Muhammad Shafique (NYU Abu Dhabi, United Arab Emirates)

9E-1

Title	Manufacturing-Aware Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement Refinement
Author	*Yu-Jin Xie, Kuan-Yu Chen, Wai-Kei Mak (National Tsing Hua Univ., Taiwan)
Page	pp. 872 - 877
Detailed information (abstract, keywords, etc)

9E-2

Title	A Hierarchical Assessment Strategy on Soft Error Propagation in Deep Learning Controller
Author	*Ting Liu, Yuzhuo Fu, Yan Zhang, Bin Shi (Shanghai Jiao Tong Univ., China)
Page	pp. 878 - 884
Detailed information (abstract, keywords, etc)

9E-3

Title	Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method
Author	*Haoyu Yang, Shifan Zhang (Chinese Univ. of Hong Kong, Hong Kong), Kang Liu (New York Univ., USA), Siting Liu (Chinese Univ. of Hong Kong, Hong Kong), Benjamin Tan, Ramesh Karri, Siddharth Garg (New York Univ., USA), Bei Yu, Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 885 - 891
Detailed information (abstract, keywords, etc)

9E-4

Title	Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated Circuits
Author	*Zhengqi Gao, Zihao Chen, Jun Tao, Yangfeng Su (Fudan Univ., China), Dian Zhou (Univ. of Texas, Dallas, USA), Xuan Zeng (Fudan Univ., China)
Page	pp. 892 - 897
Detailed information (abstract, keywords, etc)

9E-5

Title	Analog IC Aging-induced Degradation Estimation via Heterogeneous Graph Convolutional Networks
Author	*Tinghuan Chen, Qi Sun (Chinese Univ. of Hong Kong, Hong Kong), Canhui Zhan, Changze Liu, Huatao Yu (Hisilicon Technologies Co., China), Bei Yu (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 898 - 903
Detailed information (abstract, keywords, etc)

The 26th Asia and South Pacific Design Automation Conference Technical Program

Live Tutorial / Live Q&A Session Schedule

List of papers

The 26th Asia and South Pacific Design Automation Conference
Technical Program