(Go to Top Page)

The 20th Workshop on Synthesis And System Integration of Mixed Information Technologies
Technical Program

Remark: The presenter of each paper is marked with "*".
Technical Program:   SIMPLE version   DETAILED version with abstract
Author Index:   HERE

Session Schedule

Monday, October 24, 2016

- 9:00
9:00 - 9:20
K  Keynote Speech
9:20 - 10:20
10:20 - 11:50
11:50 - 13:20
I1  Invited Talk
13:20 - 14:10
14:10 - 15:40
20th Memorial Ceremony
15:40 - 15:55
D  Panel
15:55 - 17:40

Tuesday, October 25, 2016

I2  Invited Talk
9:10 - 10:00
10:00 - 11:50
11:50 - 13:20
I3  Invited Talk
13:20 - 14:10
14:10 - 16:00
I4  Invited Talk
16:00 - 16:50
16:50 - 17:00

List of papers

Remark: The presenter of each paper is marked with "*".

Monday, October 24, 2016

Keynote Speech
Time: 9:20 - 10:20 Monday, October 24, 2016
Chair: Nagisa Ishiura (Kwansei Gakuin Univ., Japan)

K-1 (Time: 9:20 - 10:20)
TitleCyber-Medical Systems: Requirements, Components and Design
Author*Giovanni De Micheli (EPFL, Switzerland)
Pagep. 1
Detailed information (abstract, keywords, etc)

Time: 10:20 - 11:50 Monday, October 24, 2016
Chairs: Yoshinori Takeuchi (Osaka Univ., Japan), Kazuya Tanigawa (Hiroshima City Univ., Japan)

R1-1 (Time: 10:20 - 10:22)
TitleDetecting Missed Arithmetic Optimization in C Compilers by Differential Random Testing
Author*Mitsuyoshi Iwatsuji, Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Pagepp. 2 - 3
Detailed information (abstract, keywords, etc)

R1-2 (Time: 10:22 - 10:24)
TitleSymmetric Segmented Delta Encoding for Wireless Sensor Data Compression
Author*Shu-Ping Liang, Yi-Yu Liu (Yuan Ze Univ., Taiwan)
Pagepp. 4 - 9
Detailed information (abstract, keywords, etc)

R1-3 (Time: 10:24 - 10:26)
TitleRegister-Bridge Architecture and its Application to Multiprocessor Systems
Author*Takafumi Fujii, Shinichi Nishizawa, Kazuhito Ito (Saitama Univ., Japan)
Pagepp. 10 - 15
Detailed information (abstract, keywords, etc)

R1-4 (Time: 10:26 - 10:28)
TitleHardware Accelerator of Convolutional Neural Network for Image Recognition and its Performance Evaluation Platform
Author*Takayuki Ujiie, Masayuki Hiromoto, Takashi Sato (Kyoto Univ., Japan)
Pagepp. 16 - 17
Detailed information (abstract, keywords, etc)

R1-5 (Time: 10:28 - 10:30)
TitleOn a Radiation Resistant Data-Path and Controller Synthesis
Author*Keisuke Inoue (Kanazawa Technical College, Japan)
Pagepp. 18 - 22
Detailed information (abstract, keywords, etc)

R1-6 (Time: 10:30 - 10:32)
TitleA Heuristic Decompositions Index Generation Functions with Many Variables
AuthorTsutomu Sasao, *Kyu Matsuura, Yukihiro Iguchi (Meiji Univ., Japan)
Pagepp. 23 - 28
Detailed information (abstract, keywords, etc)

R1-7 (Time: 10:32 - 10:34)
TitleDebugging of Reconfigurable Single-Electron Transistor Arrays
AuthorWen-Chun Zeng, *Shih-Hsiang Liu, Yu-Da Chen, Yung-Chih Chen (Yuan Ze Univ., Taiwan)
Pagepp. 29 - 30
Detailed information (abstract, keywords, etc)

R1-8 (Time: 10:34 - 10:36)
TitleLayer Assignment for Multi-Power-Mode 3D IC Designs with Power Distribution Networks Considered
Author*Shih-Hsu Huang, Jian-Zhi Shen, Chun-Hua Cheng (Chung Yuan Christian Univ., Taiwan)
Pagepp. 31 - 35
Detailed information (abstract, keywords, etc)

R1-9 (Time: 10:36 - 10:38)
TitleA Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory
Author*Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ., Japan)
Pagepp. 36 - 41
Detailed information (abstract, keywords, etc)

R1-10 (Time: 10:38 - 10:40)
TitleCORP: Control Routing for Paper-Based Digital Microfluidic Biochips
AuthorQin Wang, Hailong Yao (Tsinghua Univ., China), *Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Yici Cai (Tsinghua Univ., China)
Pagepp. 42 - 47
Detailed information (abstract, keywords, etc)

R1-11 (Time: 10:40 - 10:42)
TitleAnalysis of Body Bias Control for Real Time Systems
Author*Carlos Cesar Cortes Torres, Hayate Okuhara, Akram Ben Ahmed, Nobuyuki Yamasaki, Hideharu Amano (Keio Univ., Japan)
Pagepp. 48 - 53
Detailed information (abstract, keywords, etc)

R1-12 (Time: 10:42 - 10:44)
TitlePerformance-Driven Multi-Layer OARST Construction with Steiner-Point Pre-Selection and Bounded Maze Routing
Author*Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li (National Chiao Tung Univ., Taiwan), Rung-Bin Lin (Yuan Ze Univ., Taiwan), Wen-Hao Liu (Cadence Design Systems, U.S.A.)
Pagepp. 54 - 59
Detailed information (abstract, keywords, etc)

R1-13 (Time: 10:44 - 10:46)
TitlePerformance Improvement of General-Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection
Author*Shimpei Sato, Hiroshi Nakatsuka, Atsushi Takahashi (Tokyo Inst. of Tech., Japan)
Pagepp. 60 - 65
Detailed information (abstract, keywords, etc)

R1-14 (Time: 10:46 - 10:48)
TitleFPGA Prototyping of a Smart Card Platform for Evaluating Tamper Resistance of Cryptographic Circuits
Author*Hiroyuki Kanbara (ASTEM RI, Japan), Naoya Ito, Hinata Takebayashi (Kwansei Gakuin Univ., Japan), Muneyuki Takenae (Ritsumeikan Univ., Japan), Takashi Tsukamoto (Information-technology Promotion Agency, Japan)
Pagepp. 66 - 70
Detailed information (abstract, keywords, etc)

R1-15 (Time: 10:48 - 10:50)
TitleConvolutional Neural Network Layer Reordering for Acceleration
Author*Vijay Daultani, Subhajit Chaudhury, Kazuhisa Ishizaka (NEC, Japan)
Pagepp. 71 - 76
Detailed information (abstract, keywords, etc)

R1-16 (Time: 10:50 - 10:52)
TitleSystem Design of Vision-based Framework for Senior Driver Assistance
Author*Eric Aliwarga, Koichi Mitsunari, Jaehoon Yu, Takao Onoye (Osaka Univ., Japan), Toshitaka Azuma, Mitsuhiko Koga (Vehicle Information and Communication System Center, Japan)
Pagepp. 77 - 80
Detailed information (abstract, keywords, etc)

R1-17 (Time: 10:52 - 10:54)
TitleAn FPGA Implementation of SVM for Type Identification with Colorectal Endoscopic Images
Author*Takumi Okamoto, Tetsushi Koide, Anh-Tuan Hoang, Tatsuya Shimizu, Koki Sugi, Toru Tamaki, Tsubasa Hirakawa, Bisser Raytchev, Kazufumi Kaneda (Hiroshima Univ., Japan), Shigeto Yoshida, Hiroshi Mieno (Hiroshima General Hospital of West Japan Railway Company, Japan), Shinji Tanaka (Hiroshima Univ. Hospital, Japan)
Pagepp. 81 - 86
Detailed information (abstract, keywords, etc)

Invited Talk
Time: 13:20 - 14:10 Monday, October 24, 2016
Chair: Mineo Kaneko (JAIST, Japan)

I1-1 (Time: 13:20 - 14:10)
TitleComputing in the IoT Era, Opportunities and Challenges
Author*David Chen (ARM, China)
Pagep. 87
Detailed information (abstract, keywords, etc)

Time: 14:10 - 15:40 Monday, October 24, 2016
Chairs: Masato Inagi (Hiroshima City Univ., Japan), Seiya Shibata (NEC, Japan)

R2-1 (Time: 14:10 - 14:12)
TitleRandom Testing of Back-end of Compiler Infrastructure LLVM
Author*Kenji Tanaka, Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Masanari Nishimura, Akiya Fukui (Renesas System Design, Japan)
Pagepp. 88 - 89
Detailed information (abstract, keywords, etc)

R2-2 (Time: 14:12 - 14:14)
TitleRetention-aware Refresh Techniques for DRAM Refresh Power Reduction
Author*Wei-Kai Cheng, Po-Yuan Shen (Chung Yuan Christian Univ., Taiwan)
Pagepp. 90 - 93
Detailed information (abstract, keywords, etc)

R2-3 (Time: 14:14 - 14:16)
TitleStochastic Number Generation with Internal Signals of Logic Circuits
Author*Naoya Kubota, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ., Japan)
Pagepp. 94 - 95
Detailed information (abstract, keywords, etc)

R2-4 (Time: 14:16 - 14:18)
TitleA Branch-and-Bound Algorithm for Scheduling of Data-Parallel Tasks
Author*Yang Liu, Lin Meng, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ., Japan)
Pagepp. 96 - 100
Detailed information (abstract, keywords, etc)

R2-5 (Time: 14:18 - 14:20)
TitleAutomatic Enable Candidate Extraction for Backward Sequential Clock Gating
Author*Shinji Kimura, Tomoya Goto, Masao Yanagisawa (Waseda Univ., Japan)
Pagepp. 101 - 106
Detailed information (abstract, keywords, etc)

R2-6 (Time: 14:20 - 14:22)
TitleA Decision Diagram to Analyze Probabilistic Behavior of Circuits
Author*Kodai Abe, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Pagepp. 107 - 112
Detailed information (abstract, keywords, etc)

R2-7 (Time: 14:22 - 14:24)
TitleRandom Delay Elements for Tamper Resistant Asynchronous Circuits based on 2-phase Handshaking Protocol
Author*Daiki Toyoshima, Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai (Hirosaki Univ., Japan)
Pagepp. 113 - 118
Detailed information (abstract, keywords, etc)

R2-8 (Time: 14:24 - 14:26)
TitleOptimization of Temperature Dependent Intentional Skew for Temperature Aware Timing Design
Author*Makoto Soga, Mineo Kaneko (JAIST, Japan)
Pagepp. 119 - 124
Detailed information (abstract, keywords, etc)

R2-9 (Time: 14:26 - 14:28)
TitlePerformance Evaluation Platform for Programmable Interconnect Architecture Exploration
AuthorKohei Yamamoto, Toshiki Morioka, Tomoya Inoue, *Masataka Mori, Yukio Mitsuyama (Kochi Univ. of Tech., Japan)
Pagepp. 125 - 128
Detailed information (abstract, keywords, etc)

R2-10 (Time: 14:28 - 14:30)
TitleEfficient Standard Cell Layout Synthesis Algorithm Considering Various Driving Strengths
Author*Hong-Yan Su, Bo-Shung Wang, Sin-Ye Hsieh, Yih-Lang Li (National Chiao Tung Univ., Taiwan), I-Hsun Wu, Chang-Chung Wu, Wei-Chiang Shih (M31 Technology, Taiwan), Hidetoshi Onodera (Kyoto Univ., Japan), Masanori Hashimoto (Osaka Univ., Japan)
Pagepp. 129 - 134
Detailed information (abstract, keywords, etc)

R2-11 (Time: 14:30 - 14:32)
TitleFast Length-Matching Routing for Rapid Single Flux Quantum Circuits
Author*Nobutaka Kito (Chukyo Univ., Japan), Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ., Japan)
Pagepp. 135 - 140
Detailed information (abstract, keywords, etc)

R2-12 (Time: 14:32 - 14:34)
TitleA Comparative Study on Multisource Clock Network Synthesis
AuthorWen-Hsin Chen, Chun-Kai Wang, *Hung-Ming Chen (NCTU Taiwan, Taiwan), Yih-Chih Chen, Cheng-Hong Tsai (Global Unichip, Taiwan)
Pagepp. 141 - 145
Detailed information (abstract, keywords, etc)

R2-13 (Time: 14:34 - 14:36)
TitleTarget Concentration Exploration for Reactant Minimization on Digital Microfluidic Biochips
AuthorYi-Ling Chen, Yung-Chun Lei, *Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)
Pagepp. 146 - 151
Detailed information (abstract, keywords, etc)

R2-14 (Time: 14:36 - 14:38)
TitlePractical and Accurate SOC Estimation System for Lithium-Ion Batteries by EKF with Adaptive Noise Covariance Estimation
Author*Lei Lin, Kiyotsugu Takaba, Masahiro Fukui (Ritsumeikan Univ., Japan)
Pagepp. 152 - 157
Detailed information (abstract, keywords, etc)

R2-15 (Time: 14:38 - 14:40)
TitleTrue Random-Bit Generation Using a Continuous-Time Chaotic Oscillator
Author*Chatchai Wannaboon, Masayoshi Tachibana (Kochi Univ. of Tech., Japan)
Pagepp. 158 - 161
Detailed information (abstract, keywords, etc)

R2-16 (Time: 14:40 - 14:42)
TitleHardware Acceleration Technique for Radio-resource Scheduler in Ultra-high-density Distributed Antenna Systems
Author*Yuki Arikawa, Hiroyuki Uzawa, Takeshi Sakamoto, Satoshi Shigematsu (NTT, Japan)
Pagepp. 162 - 163
Detailed information (abstract, keywords, etc)

R2-17 (Time: 14:42 - 14:44)
TitleAn Overlay Architecture for FPGA-Based Industrial Control Systems Designed with Functional Block Diagrams
Author*Taisei Segawa, Yuichiro Shibata, Yudai Shirakura, Kenichi Morimoto, Hidenori Maruta, Fujio Kurokawa (Nagasaki Univ., Japan), Masaharu Tanaka (Mitsubishi Heavy Industries, Japan), Masanori Nobe (Mitsubishi Hitachi Power Systems, Japan)
Pagepp. 164 - 169
Detailed information (abstract, keywords, etc)

Time: 15:55 - 17:40 Monday, October 24, 2016

D-1 (Time: 15:55 - 17:25)
TitlePast and Future 25 Years of Synthesis and System Integration
AuthorModerator: Isao Shirakawa (Univ. of Hyogo, Japan), Panelists: Giovanni De Micheli (EPFL, Switzerland), Youn-Long Lin, Ren-Song Tsay (National Tsing Hua Univ., Taiwan), Peter Marwedel (Technical Univ. of Dortmund, Germany), Organizer: Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Pagep. 170
Detailed information (abstract, keywords, etc)

Tuesday, October 25, 2016

Invited Talk
Time: 9:10 - 10:00 Tuesday, October 25, 2016
Chair: Kiyoharu Hamaguchi (Shimane Univ., Japan)

I2-1 (Time: 9:10 - 10:00)
TitleWide Bandgap Analog and Mixed-signal IC Design for Advanced Power Electronics
Author*Alan Mantooth (Univ. of Arkansas, U.S.A.)
Pagep. 171
Detailed information (abstract, keywords, etc)

Time: 10:00 - 11:50 Tuesday, October 25, 2016
Chairs: Wenxing Zhu (Fuzhou Univ., China), Hideki Takase (Kyoto Univ., Japan)

R3-1 (Time: 10:00 - 10:02)
TitleExtending Distributed Control for High-Level Synthesis beyond Borders of Basic Blocks
Author*Miho Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Pagepp. 172 - 177
Detailed information (abstract, keywords, etc)

R3-2 (Time: 10:02 - 10:04)
TitleProposal of an Efficient Clock-Gating Mechanism for Multi-Core Processors to Reduce Power Supply Noise
Author*Jun Kawabe, Yoshinori Takeuchi, Jaehoon Yu, Masaharu Imai (Osaka Univ., Japan)
Pagepp. 178 - 183
Detailed information (abstract, keywords, etc)

R3-3 (Time: 10:04 - 10:06)
TitleAutomatic Netlist Transformation for WDF-Based Analog Emulator
AuthorHsu-Ping Yang, *Hsin-Ju Hsu, Chun Wang, Chien-Nan Jimmy Liu, Jing-Yang Jou (National Central Univ., Taiwan)
Pagepp. 184 - 189
Detailed information (abstract, keywords, etc)

R3-4 (Time: 10:06 - 10:08)
TitleNonlinear Optimization Solver with Multiple Precision Arithmetic
Author*Yuya Matsumoto, Hiroshige Dan (Kansai Univ., Japan)
Pagepp. 190 - 194
Detailed information (abstract, keywords, etc)

R3-5 (Time: 10:08 - 10:10)
TitleHigh Speed Cycle-Accurate Processor Simulation Through Ahead of Time Compilation
Author*Lovic Gauthier (National Inst. of Tech., Ariake College, Japan)
Pagepp. 195 - 200
Detailed information (abstract, keywords, etc)

R3-6 (Time: 10:10 - 10:12)
TitlePrototype Speed Limit Sign Recognition System Implementation on Rapid Prototyping Platform
Author*Anh-Tuan Hoang, Takumi Okamoto, Tetsushi Koide (Hiroshima Univ., Japan)
Pagepp. 201 - 202
Detailed information (abstract, keywords, etc)

R3-7 (Time: 10:12 - 10:14)
TitleReconfigurable Processor Array Architecture for Deep Convolutional Neural Networks
Author*Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura (Hokkaido Univ., Japan)
Pagepp. 203 - 204
Detailed information (abstract, keywords, etc)

R3-8 (Time: 10:14 - 10:16)
TitleOn Component Ratio of RECON Spare Cells for ECO-Friendly Design Style
Author*Takeshi Sawai, Ayano Takezaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 205 - 210
Detailed information (abstract, keywords, etc)

R3-9 (Time: 10:16 - 10:18)
TitleTheorem-proving Verification of Multi-clock Synchronous Circuits on Multimodal Logic
Author*Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ., Japan)
Pagepp. 211 - 212
Detailed information (abstract, keywords, etc)

R3-10 (Time: 10:18 - 10:20)
TitleHardware Trojan Insertion Difficulties into Synchronous and Asynchronous Circuits
Author*Masashi Imai (Hirosaki Univ., Japan), Tomohiro Yoneda (NII, Japan)
Pagepp. 213 - 218
Detailed information (abstract, keywords, etc)

R3-11 (Time: 10:20 - 10:22)
TitleA Delay Adjustment Method for Asynchronous Circuits with Bundled-data Implementation Considering a Latency Constraint
Author*Kazumasa Yoshimi, Hiroshi Saito (Univ. of Aizu, Japan)
Pagepp. 219 - 224
Detailed information (abstract, keywords, etc)

R3-12 (Time: 10:22 - 10:24)
TitlePath Grouping Approach for Efficient Candidate Selection of Replacing NBTI Mitigation Logic
Author*Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato (Kyoto Univ., Japan)
Pagepp. 225 - 230
Detailed information (abstract, keywords, etc)

R3-13 (Time: 10:24 - 10:26)
TitleSemi-Automated Analog Placement based on Margin Tolerances
Author*Eric Lao, Marie-Minerve LouŽrat, Jean-Paul Chaput (Laboratoire d'informatique de Paris 6, France)
Pagepp. 231 - 235
Detailed information (abstract, keywords, etc)

R3-14 (Time: 10:26 - 10:28)
TitleAn Efficient Gaussian Mixture Reduction to Two Components
AuthorNaoya Yokoyama, *Daiki Azuma, Shuji Tsukiyama (Chuo Univ., Japan), Masahiro Fukui (Ritsumeikan Univ., Japan)
Pagepp. 236 - 241
Detailed information (abstract, keywords, etc)

R3-15 (Time: 10:28 - 10:30)
TitleThermal Circuit Identification of Power MOSFETs through In-Situ Channel Temperature Estimation
Author*Kazuki Oishi, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato (Kyoto Univ., Japan)
Pagepp. 242 - 247
Detailed information (abstract, keywords, etc)

R3-16 (Time: 10:30 - 10:32)
TitleEvaluation of PLL Layouts based on Transistor Array-style
Author*Atsushi Nanri, Bo Liu, Yuki Miura, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)
Pagepp. 248 - 251
Detailed information (abstract, keywords, etc)

R3-17 (Time: 10:32 - 10:34)
TitleSingle Row Cell Placement Considering Self-aligned Double Patterning
AuthorYe-Hong Chen, *Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Pagepp. 252 - 257
Detailed information (abstract, keywords, etc)

R3-18 (Time: 10:34 - 10:36)
TitleA Lithium Ion Battery Aging Simulator with Calibration Functions
Author*Yukinori Hayakawa, Lei Lin, Masahiro Fukui (Ritsumeikan Univ., Japan)
Pagepp. 258 - 263
Detailed information (abstract, keywords, etc)

R3-19 (Time: 10:36 - 10:38)
TitleA Full Charge Capacity Estimation Algorithm for Li-ion Batteries Based on Recursive Least-Squares Identification with Adaptive Forgetting Factor Tuning
Author*Hironori Ono, Lei Lin, Masahiro Fukui, Kiyotsugu Takaba (Ritsumeikan Univ., Japan)
Pagepp. 264 - 267
Detailed information (abstract, keywords, etc)

R3-20 (Time: 10:38 - 10:40)
TitleA Hardware Architecture to Perform K-means Clustering for Learning-Based Super-Resolution Combining Self-Learning and Prior-Learning Dictionaries
Author*Daichi Murata, Ayumi Kiriyama, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 268 - 273
Detailed information (abstract, keywords, etc)

R3-21 (Time: 10:40 - 10:42)
TitleOn-Chip Temperature Sensing using a Reconfigurable Ring Oscillator
Author*Tadashi Kishimoto, Hidetoshi Onodera (Kyoto Univ., Japan)
Pagepp. 274 - 279
Detailed information (abstract, keywords, etc)

R3-22 (Time: 10:42 - 10:44)
TitleA Shift HSV Algorithm for a Low-Power Monitoring System using an FPGA toward Internet of Things Agriculture
AuthorTakahisa Kurose (Ehime Univ., Japan), *Hiroki Nakahara, Shimpei Sato (Tokyo Inst. of Tech., Japan), Tetsuo Morimoto (Ehime Univ., Japan)
Pagepp. 280 - 281
Detailed information (abstract, keywords, etc)

Invited Talk
Time: 13:20 - 14:10 Tuesday, October 25, 2016
Chair: Kiyoharu Hamaguchi (Shimane Univ., Japan)

I3-1 (Time: 13:20 - 14:10)
TitleThe Challenges and Future of Electronic-System Level Design Automation
Author*Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Pagep. 282
Detailed information (abstract, keywords, etc)

Time: 14:10 - 16:00 Tuesday, October 25, 2016
Chairs: Tsuyoshi Matsumoto (Ishikawa Tech. College, Japan), Xin Jin (Tsinghua Univ., China)

R4-1 (Time: 14:10 - 14:12)
TitleMathematical Algorithm Hardware Description Languages for System Level Modeling
AuthorRyo Hikawa, *Ryuji Kishimoto, Takashi Kambe (Kindai Univ., Japan)
Pagepp. 283 - 284
Detailed information (abstract, keywords, etc)

R4-2 (Time: 14:12 - 14:14)
TitleHigh-Level Synthesis of Embedded Systems Controller from Erlang
AuthorHinata Takebayashi, Nagisa Ishiura, *Kagumi Azuma (Kwansei Gakuin Univ., Japan), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM RI, Japan)
Pagepp. 285 - 290
Detailed information (abstract, keywords, etc)

R4-3 (Time: 14:14 - 14:16)
TitleA Data Effect Aware Microcomponent-Based Estimation Approach for Accurate System-Level Memory Device Power Evaluation
Author*Chi-Kang Chen, Hsin-I Wu, Chi-Ting Hsiao, Ren-Song Tsay (National Tsing Hua Univ., Taiwan)
Pagepp. 291 - 296
Detailed information (abstract, keywords, etc)

R4-4 (Time: 14:16 - 14:18)
TitleAnalysis of Co-Controlling Voltage/Frequency of Cores and DRAMs of Chip Multi-Processors with 3D-stacked DRAMs for Thermal Management
Author*Yi-Jung Chen (National Chi Nan Univ., Taiwan), Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu (National Taiwan Univ., Taiwan)
Pagepp. 297 - 302
Detailed information (abstract, keywords, etc)

R4-5 (Time: 14:18 - 14:20)
TitleIntroducing Real Constraints in Partitioned ILP-Based Binding in High-Level Synthesis
AuthorNagisa Ishiura, *Yuuki Oosako (Kwansei Gakuin Univ., Japan)
Pagepp. 303 - 304
Detailed information (abstract, keywords, etc)

R4-6 (Time: 14:20 - 14:22)
TitleA Framework for Automatic Generation of Application-Specific FPGA-based SoC
Author*Tetsuo Miyauchi, Kiyofumi Tanaka (JAIST, Japan)
Pagepp. 305 - 310
Detailed information (abstract, keywords, etc)

R4-7 (Time: 14:22 - 14:24)
TitleFast Song Searching by Simultaneous Execution of HiFP2.0 and Staged LSH
Author*Masahiro Fukuda, Yasushi Inoguchi (JAIST, Japan)
Pagepp. 311 - 316
Detailed information (abstract, keywords, etc)

R4-8 (Time: 14:24 - 14:26)
TitleAn Error Diagnosis Technique Based on Averaged EPI Values to Extract Error Locations Sets
Author*Ayano Takezaki, Takeshi Sawai, Hiroyuki Sakamoto, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Pagepp. 317 - 322
Detailed information (abstract, keywords, etc)

R4-9 (Time: 14:26 - 14:28)
TitleMinimum Energy Point Tracking under a Wide Range of PVT Conditions
Author*Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ., Japan)
Pagepp. 323 - 328
Detailed information (abstract, keywords, etc)

R4-10 (Time: 14:28 - 14:30)
TitleComparison of Area-Delay-Energy Characteristics between General Purpose Processors and Dedicated Hardwares for Embedded Applications
Author*Kei Yoshizawa, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ., Japan)
Pagepp. 329 - 334
Detailed information (abstract, keywords, etc)

R4-11 (Time: 14:30 - 14:32)
TitleFinding Effective Simulation Patterns for Coverage-Driven Verification Using Deep Learning
Author*Mami Miyamoto, Kiyoharu Hamaguchi (Shimane Univ., Japan)
Pagepp. 335 - 340
Detailed information (abstract, keywords, etc)

R4-12 (Time: 14:32 - 14:34)
TitleStatic Timing Analysis of Rapid Single-Flux-Quantum Circuits
Author*Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ., Japan)
Pagepp. 341 - 345
Detailed information (abstract, keywords, etc)

R4-13 (Time: 14:34 - 14:36)
TitleImproved Method of Simulated Annealing for Unreachable Solution Space
Author*Hiroyuki Nakano, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Pagepp. 346 - 351
Detailed information (abstract, keywords, etc)

R4-14 (Time: 14:36 - 14:38)
TitleApplication of Monte-Carlo Tree Search to Traveling-Salesman Problem
AuthorMasato Shimomura, *Yasuhiro Takashima (Univ. of Kitakyushu, Japan)
Pagepp. 352 - 356
Detailed information (abstract, keywords, etc)

R4-15 (Time: 14:38 - 14:40)
TitleAnalog Characterization Module with D/A Converter Configuration
Author*Daishi Isogai, Bo Liu, Futa Yoshinaka, Shigetoshi Nakatake (Univ. of Kitakyushu, Japan)
Pagepp. 357 - 361
Detailed information (abstract, keywords, etc)

R4-16 (Time: 14:40 - 14:42)
TitleRange Limiter using Connection Bounding Box for SA-based Placement of Mixed-Grained Reconfigurable Architecture
Author*Takashi Kishimoto (Ritsumeikan Univ., Japan), Wataru Takahashi, Kazutoshi Wakabayashi (NEC, Japan), Hiroyuki Ochi (Ritsumeikan Univ., Japan)
Pagepp. 362 - 367
Detailed information (abstract, keywords, etc)

R4-17 (Time: 14:42 - 14:44)
TitleA Smart Hybrid Memetic Algorithm for Thermal-Aware Non-Slicing Floorplanning
Author*Jianli Chen, Yan Liu, Ziran Zhu, Wenxing Zhu (Fuzhou Univ., China)
Pagepp. 368 - 373
Detailed information (abstract, keywords, etc)

R4-18 (Time: 14:44 - 14:46)
TitleHardware Acceleration of Rate-Distortion Optimized Quantization Algorithm
Author*Yusuke Funayama, Takashi Kambe (Kindai Univ., Japan), Gen Fujita (Osaka Electro-Communication Univ., Japan)
Pagepp. 374 - 375
Detailed information (abstract, keywords, etc)

R4-19 (Time: 14:46 - 14:48)
TitleDevelopment of an Optimal Wireless Power Transfer System for Lithium-Ion Battery Charge
Author*Yuto Honda, Lei Lin, Masahiro Fukui (Ritsumeikan Univ., Japan)
Pagepp. 376 - 381
Detailed information (abstract, keywords, etc)

R4-20 (Time: 14:48 - 14:50)
TitleDesign of a Fast Lock-in and Low-Power All-Digital Frequency Synthesizer with a Wide Tuning Range
Author*Hao-Chiao Hong, Hung-Yi Wen (National Chiao Tung Univ., Taiwan), Hong-Yi Huang (National Taipei Univ., Taiwan)
Pagepp. 382 - 385
Detailed information (abstract, keywords, etc)

R4-21 (Time: 14:50 - 14:52)
TitleA Method for Recognizing a Breaking Sound of a Window Glass for Realizing a Low-power Security Surveillance System Using FPGA
Author*Ryo Terafuji, Hiroyuki Ochi (Ritsumeikan Univ., Japan)
Pagepp. 386 - 390
Detailed information (abstract, keywords, etc)

R4-22 (Time: 14:52 - 14:54)
TitleElectromagnetic Analysis for a Lightweight Block Cipher Simon
Author*Yusuke Nozaki, Yoshiya Ikezaki, Masaya Yoshikawa (Meijo Univ., Japan)
Pagepp. 391 - 396
Detailed information (abstract, keywords, etc)

Invited Talk
Time: 16:00 - 16:50 Tuesday, October 25, 2016
Chair: Mineo Kaneko (JAIST, Japan)

I4-1 (Time: 16:00 - 16:50)
TitleQualitative-Modeling-Based Design for Silicon Neuronal Networks
Author*Takashi Kohno (Univ. of Tokyo, Japan)
Pagep. 397
Detailed information (abstract, keywords, etc)