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| Monday, October 24, 2016 |
| Title | Cyber-Medical Systems: Requirements, Components and Design |
| Author | *Giovanni De Micheli (EPFL, Switzerland) |
| Page | p. 1 |
| Abstract | We are continuously witnessing a relentless growth of computing power, storage capacity and communication bandwidth as well as a major trend in biomedical sciences to become more quantitative and amenable to benefit from the support of electronic systems. Moreover, societal and economic needs push us to develop and adopt health-management approaches that are more effective, less expensive and flexible enough to be personalized to individual and community needs. Within this frame, distributed data acquisition and control systems, i.e., cyberphysical systems, start playing an important role in health care. Examples include, but are not limited to, remote patient monitoring, emergency care as well as routine care. These examples benefit from organized and optimized means to quantify clinical data, handle large data sets as well as controlling and personalizing therapy and drug administration. Current electronic devices and systems need to grow in various directions to satisfy the quality needs for health care. Current semiconductor products have to incorporate bio-chemical interfaces, such as sensors, to perform data acquisition directly. The experience in electronic semicustom design and in platform-based design can be ported successfully to integrated sensing devices, where modularity and regularity can be key to reducing non-recurrent engineering costs. The fusion of sensing and microelectronic technologies, as well as the ability of volume production of integrated sensing systems that can be personalized in the very back end of the line or after fabrication is an important scientific and commercial goal. Field-programmable sensing arrays can enable inexpensive multi-panel sensing for various medical applications. Electronic design automation is a key technology to realize cyber-medical systems. Examples of specific EDA tools and methods encompass physical design of integrated sensors and their coupling to electronics, simulation of complex systems with bio-chemical stimuli, synthesis of decision making circuitry based on plurality of inexact inputs, policies design for therapies exploiting on-line data acquisition, and verification of life-critical applications under broadly-varying and unpredictable input conditions. Overall, cyber-medical systems represent an important and large market opportunity. EDA is a necessary underlying technology to realize the promises of better and less expensive care for everyone. |
| Title | Detecting Missed Arithmetic Optimization in C Compilers by Differential Random Testing |
| Author | *Mitsuyoshi Iwatsuji, Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin University, Japan) |
| Page | pp. 2 - 3 |
| Keyword | randomtest, compiler, optimization, differential testing |
| Abstract | In addition to the correctness of the generated code, it is one of the important test goals to verify that optimization modules work as intended. Besides the existing equivalence-based method, this paper presents a method of detecting missed optimization opportunities in C compilers by differential random testing. Randomly generated test programs are compiled by different compilers and the resulting codes are compared to detect missed optimization. |
| Title | Symmetric Segmented Delta Encoding for Wireless Sensor Data Compression |
| Author | *Shu-Ping Liang, Yi-Yu Liu (Yuan Ze University, Taiwan) |
| Page | pp. 4 - 9 |
| Keyword | Delta encoding, Huffman encoding |
| Abstract | Wireless sensor networks (WSNs) are utilized for various applications such as environmental monitoring, urban surveillance, home security, etc. Ideally, the massively deployed sensor nodes should be inexpensive, power-efficient, and reliable to maximize the functional lifetime. However, the data-transmission energy consumption has become one of the most challenging issues. To minimize the data-transmission energy cost in wireless applications, we propose a lossless Symmetric Segmented Delta encoding (SSD encoding) algorithm, which exploits high similarity of environmental sensing data in a short period of time. According to the experimental results, our encoding algorithm achieves better sensor data compression ratios and at the same time requires less hardware resource for wireless sensor data. |
| Title | Register-Bridge Architecture and its Application to Multiprocessor Systems |
| Author | *Takafumi Fujii, Shinichi Nishizawa, Kazuhito Ito (Saitama University, Japan) |
| Page | pp. 10 - 15 |
| Keyword | multiprocessor, register-bridge, data communication delay, parallel processing |
| Abstract | The interconnection delay in data transfer is becoming the dominant factor to restrain the improvement of the maximum clock frequency of LSIs. The regular distributed register (RDR) architecture is proposed where data transfer between the islands is separated from the computation and local data access, and distant data transfer is done using multiple clock cycles. In this paper a novel register-bridge (RB) architecture is proposed so that data transfer between adjacent islands is done through bridge registers in between the islands, thereby the necessary number of clock cycles for data transfer would be reduced. The experimental results show about 11 % reduction in the latency on average when example procedures are implemented on a multiprocessor system based on the RB architecture. |
| Title | Hardware Accelerator of Convolutional Neural Network for Image Recognition and its Performance Evaluation Platform |
| Author | *Takayuki Ujiie, Masayuki Hiromoto, Takashi Sato (Kyoto University, Japan) |
| Page | pp. 16 - 17 |
| Keyword | Image Recognition, Embedded Systems, Low Power Design |
| Abstract | Convolutional neural network (CNN) is widely used for realizing accurate image recognition systems. However, its computational cost is extremely high, which increases power consumption of embedded computer vision systems. This paper presents a hardware accelerator for CNN and its performance evaluation platform for co-designing efficient algorithm and hardware. Through the performance evaluation of two types of CNN algorithms, we demonstrated that our proposed platform is useful for making quantitative comparison of both algorithm and hardware performance among different CNN algorithms. |
| Title | On a Radiation Resistant Data-Path and Controller Synthesis |
| Author | *Keisuke Inoue (Kanazawa Technical College, Japan) |
| Page | pp. 18 - 22 |
| Keyword | high-level synthesis, radiation resistance |
| Abstract | This paper discusses a high-level design of an application specific integrated circuit with radiation resistance. A soft error occurs when a radiation event causes enough of a charge disturbance to reverse or flip the data state of a register. We introduce Error-Correcting Code register (ECC register), a type of data storage that can detect and correct data corruption. We consider data-path synthesis with ECC register, and controller synthesis with radiation resistance. |
| Title | A Heuristic Decompositions Index Generation Functions with Many Variables |
| Author | Tsutomu Sasao, *Kyu Matsuura, Yukihiro Iguchi (Meiji University, Japan) |
| Page | pp. 23 - 28 |
| Keyword | Logic design, Functional Decomposition, Heuristic, Monte Carlo |
| Abstract | This paper shows a heuristic method to decompose index generation functions with many variables. Three different measures are used to select the bound variables. Experimental results shows that this method finds fairly good decompositions in a short time. Comparison with Monte Carlo method is presented. |
| Title | Debugging of Reconfigurable Single-Electron Transistor Arrays |
| Author | Wen-Chun Zeng, *Shih-Hsiang Liu, Yu-Da Chen, Yung-Chih Chen (Yuan Ze University, Taiwan) |
| Page | pp. 29 - 30 |
| Keyword | Debugging, Satisfiability, Single-Electron Transistor Array |
| Abstract | This paper proposes an automatic debugging method for single-electron transistor arrays. The method iteratively calls a SAT solver to find a counterexample and analyzes the counterexample to identify errors. It can fix an incorrect SET array which can be corrected by changing an edge's configuration. The experimental results show that the proposed debugging method is efficient and effective. It finds all the possible corrections for an incorrect SET array within an average of 0.021 seconds. |
| Title | Layer Assignment for Multi-Power-Mode 3D IC Designs with Power Distribution Networks Considered |
| Author | *Shih-Hsu Huang, Jian-Zhi Shen, Chun-Hua Cheng (Chung Yuan Christian University, Taiwan) |
| Page | pp. 31 - 35 |
| Keyword | Layer Assignment, Multiple Power Modes, 3D IC, Footprint Area, High-Level Design Stage |
| Abstract | The design of multiple power modes has been recognized as an effective method to reduce the power consumption. However, the layer assignment of multi-power-mode designs based on 3D IC architecture has not been well studied. In this paper, we demonstrate that the layer assignment result has a significant impact on the areas of power distribution networks. As a result, there is a demand to take the area overheads of power distribution networks into account during the layer assignment stage. Based on this observation, we present the first work to perform the layer assignment of multi-power-mode 3D IC designs with the areas of power distribution networks considered. We use an integer linear programming (ILP) approach to formally draw up this problem. Different from previous works, our approach not only considers the areas of modules and through-silicon-vias (TSVs) but also considers the areas of power distribution networks. Benchmark data show that our approach can greatly reduce the footprint area (including module areas, TSV areas, and power distribution network areas) without affecting the circuit performance. |
| Title | A Processor Architecture Integrating Voltage Scalable On-Chip Memories for Individual Tracking of Minimum Energy Points in Logic and Memory |
| Author | *Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto University, Japan) |
| Page | pp. 36 - 41 |
| Keyword | Dynamic Voltage and Frequency Scaling, Adaptive Body Basing, Minimum Energy Point Tracking, Standard-cell based memory |
| Abstract | A RISC processor with standard-cell based memories (SCMs) is designed to investigate a minimum energy point in a 65-nm FDSOI process technology. Measurement results show that the minimum operating voltage of the processor is 0.3V and the minimum energy consumption of 0.16nJ/cycle is achieved at 0.5V supply voltage. Simultaneous scaling of supply voltage and body bias is applied to a logic part and SCMs individually. As a result, the minimum energy consumption of the processor is reduced to 0.10nJ/cycle. |
| Title | CORP: Control Routing for Paper-Based Digital Microfluidic Biochips |
| Author | Qin Wang, Hailong Yao (Tsinghua University, China), *Tsung-Yi Ho (National Tsing Hua University, Taiwan), Yici Cai (Tsinghua University, China) |
| Page | pp. 42 - 47 |
| Keyword | Biochip, Paper-based, Control Routing, Microfluidic |
| Abstract | Paper-based digital microfluidic biochips (P-DMFBs) have recently emerged as a promising low-cost and fast-responsive platform for biochemical assays. In P-DMFBs, electrodes and control lines are printed on a piece of photo paper using inkjet printer and conductive ink of carbon nanotubes (CNTs). Compared with traditional digital microfluidic biochips (DMFBs), P-DMFBs enjoy notable advantages, such as much faster in-place fabrication with printer and ink, much lower costs, better disposability, etc. Because electrodes and CNT control lines are printed on the same layer of a paper, a new design challenge for P-DMFB is to prevent the unfavorable interactions between moving droplets and the voltages on CNT control lines. These interactions may result in unexpected droplet movements and thus incorrect assay outputs. This paper proposes the first COntrol line Routing method for P-DMFBs named CORP, which effectively eliminates the negative effects of control lines on droplets. Experimental results on real-life chips demonstrate the effectiveness of CORP. |
| Title | Analysis of Body Bias Control for Real Time Systems |
| Author | *Carlos Cesar Cortes Torres, Hayate Okuhara, Akram Ben Ahmed, Nobuyuki Yamasaki, Hideharu Amano (Keio University, Japan) |
| Page | pp. 48 - 53 |
| Keyword | Body-Bias, Real-Time, low-power, SOTB, Embedded |
| Abstract | In the past decade, Real-time Systems (RTSs) have been widely studied. RTSs should maintain time constraints to avoid catastrophic consequences and should also be energy efficient as it can be embedded in devices where the battery life is primordial. This paper is the first study of introducing Dynamic Body Biasing to RTSs, we investigate the energy efficiency of RTSs by analyzing the ability of BB on providing a satisfying tradeoff between performance and energy. The study was conducted using accurate parameters extracted from real chip measurements of a low-power microcontroller using Silicon On Thin Box (SOTB) technology; with such proposal we were able to achieve 46% energy reduction. |
| Title | Performance-Driven Multi-Layer OARST Construction with Steiner-Point Pre-Selection and Bounded Maze Routing |
| Author | *Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li (Institute of Computer Science and Engineering, National Chiao Tung University, Taiwan), Rung-Bin Lin (Computer Science and Engineering, Yuan Ze University, Taiwan), Wen-Hao Liu (Cadence Design Systems, U.S.A.) |
| Page | pp. 54 - 59 |
| Keyword | Steiner tree, Physical design, Obstacle-avoidance, Performance-driven, Multi-layer |
| Abstract | An algorithm for performance-driven (PD) multi-layer obstacle-avoiding rectilinear Steiner tree construction with routing constraints is presented. We develop a PD selection of Steiner points. With the proposed bounded maze routing space, we identify a set of candidates for Steiner points; then, three policies are proposed to evaluate them. Experimental results demonstrate our algorithm generates tree topologies with 56.44% improvement in the PD metrics and 41.68% improvement in delay compared with the state-of-the-art heuristic while requiring less routing cost. |
| Title | Performance Improvement of General-Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection |
| Author | *Shimpei Sato, Hiroshi Nakatsuka, Atsushi Takahashi (Tokyo Institute of Technology, Japan) |
| Page | pp. 60 - 65 |
| Keyword | general-synchronous circuit, variable latency, timing-error detection |
| Abstract | General-synchronous circuits have a better performance compared to a complete-synchronous circuit. The performance of them is expected to be further improved by allowing speculative execution. In this paper, a high performance general-synchronous circuits with speculative execution is realized as a variable latency circuit by adopting error-detection and correction mechanism. In our proposed method, a circuit is designed by combining clock scheduling, delay insertion, and speculation effectively. In experiments, we confirmed that 6.7% performance improvement is achieved compared to a general-synchronous circuit with fixed latency. |
| Title | FPGA Prototyping of a Smart Card Platform for Evaluating Tamper Resistance of Cryptographic Circuits |
| Author | *Hiroyuki Kanbara (ASTEM RI, Japan), Naoya Ito, Hinata Takebayashi (Kwansei Gakuin University, Japan), Muneyuki Takenae (Ritsumeikan University, Japan), Takashi Tsukamoto (Information-technology Promotion Agency, Japan) |
| Page | pp. 66 - 70 |
| Keyword | FPGA, Prototyping, Smart Card, Tamper Resistance, Cryptography |
| Abstract | This article presents a smart card platform to evaluate tamper resistance of cryptographic circuits. Tamper resistance means difficulty of revealing sensitive information like cryptographic keys of a cryptographic device tampered with in order to make the device behave abnormally. User of this platform can manipulate their own cryptographic circuits which are connected to a co-processor bus circuit and attempt to extract the key inside the circuit in non-invasive way called side-channel attacks. A RSA encryption/decryption Circuit, an AES encryption/decryption circuit and a random number generation circuit are designed as a reference and integrated with the platform. The platform with these circuits is implemented using Xilinx FPGA. |
| Title | Convolutional Neural Network Layer Reordering for Acceleration |
| Author | *Vijay Daultani, Subhajit Chaudhury, Kazuhisa Ishizaka (NEC, Japan) |
| Page | pp. 71 - 76 |
| Keyword | CNN, Deep learning, Activation layer, Layer Reordering, Acceleration |
| Abstract | We propose a new optimization technique to speed up performance of convolution neural networks. One of the challenges for CNN is large execution time. Many CNN models are found to have a repeatable layer pattern, i.e. convolution, activation and pooling layer in that order. We show that, for a class of functions, performed in activation layer and pooling layer, it is possible to reconfigure CNN, to reduce the number of operations performed in a network, without changing output of the network. Experimental results demonstrate that using the proposed reconfiguration, we can reduce the total time for VGG by almost 5% on CPU and time for activation layer, by almost 75% for CPU, and by a range of 20% to 67% for GPU, for 2x2 max pooling kernel. |
| Title | System Design of Vision-based Framework for Senior Driver Assistance |
| Author | *Eric Aliwarga, Koichi Mitsunari, Jaehoon Yu, Takao Onoye (Osaka University, Japan), Toshitaka Azuma, Mitsuhiko Koga (Vehicle Information and Communication System Center, Japan) |
| Page | pp. 77 - 80 |
| Keyword | image recognition, machine learning, BDT |
| Abstract | System design of a video-based framework for senior driver assistance has been constructed. By utilizing sophisticated machine-learning schemes, e.g. Aggregated Channel Features and Boosted Decision Tree, status of traffic signal, vehicles ahead and oncoming, and existence of pedestrian, are effectively recognized from driver view video stream with the use of the unified classifier. By adjusting the length of boosting classifiers from 128 to 2,048, the identical hardware can treat all types of objects. Hardware system organization of the proposed approach is also described. |
| Title | An FPGA Implementation of SVM for Type Identification with Colorectal Endoscopic Images |
| Author | *Takumi Okamoto, Tetsushi Koide, Anh-Tuan Hoang, Tatsuya Shimizu, Koki Sugi, Toru Tamaki, Tsubasa Hirakawa, Bisser Raytchev, Kazufumi Kaneda (Hiroshima University, Japan), Shigeto Yoshida, Hiroshi Mieno (Hiroshima General Hospital of West Japan Railway Company, Japan), Shinji Tanaka (Hiroshima University Hospital, Japan) |
| Page | pp. 81 - 86 |
| Keyword | Computer-Aided Diagnosis, Endoscopic Images, Type Identification, Support Vector Machine, FPGA |
| Abstract | With the increase of colorectal cancer patients in recent years, the needs of quantitative evaluation of colorectal cancer are increased, and the computer-aided diagnosis (CAD) system which supports doctor's diagnosis is essential. In this paper, a hardware design of type identification module in CAD system for colorectal endoscopic images with narrow band imaging (NBI) magnification is proposed for real-time processing of full high definition image (1920 x 1080 pixel). A pyramid style image segmentation with SVMs for multi-size scan windows, which can be implemented on an FPGA with small circuit area and achieve high accuracy, is proposed for actual complex colorectal endoscopic images. |
| Title | Computing in the IoT Era, Opportunities and Challenges |
| Author | *David Chen (ARM, China) |
| Page | p. 87 |
| Abstract | IoT or Internet of Things, there is nothing ground breaking in this definition, but why is this term gaining some much traction in the last few years? In this presentation, I will start with the plethora of architectures and technologies used in IoT, highlighting the challenges and opportunities. I will present these in the context of hardware, software and tools. And then, I will present the ARM ecosystem contribution, including these not only in the context of hardware, software and tools, but also in education which is an important element of the mix. Finally, a number of conclusions including a speculative view of the mid-to-long term future of IoT will be given. |
| Title | Random Testing of Back-end of Compiler Infrastructure LLVM |
| Author | *Kenji Tanaka, Nagisa Ishiura (Kwansei Gakuin University, Japan), Masanari Nishimura, Akiya Fukui (Renesas System Design, Japan) |
| Page | pp. 88 - 89 |
| Keyword | LLVM, LLVM IR, random test, Compiler Infrastructure |
| Abstract | This paper presents a method of directly testing back-ends of the LLVM compiler infrastructure by randomly generated LLVM IR (intermediate representation). Using LLVM, a compiler for a new target can be developed only by implementing a machine dependent back-end, then the test of the back-end become a focusing issue. The proposed method generates random LLVM IR assembly codes containing arithmetic operations which are difficult to test by C programs. |
| Title | Retention-aware Refresh Techniques for DRAM Refresh Power Reduction |
| Author | *Wei-Kai Cheng, Po-Yuan Shen (Chung Yuan Christian University, Taiwan) |
| Page | pp. 90 - 93 |
| Keyword | DRAM, Refresh |
| Abstract | DRAM circuit requires periodic refresh operations to prevent data loss. However, DRAM refresh incurs extra power consumption and degrades system performance due to delaying of memory requests service. As DRAM density increases, DRAM refresh overhead is even worsened due to the increase of refresh cycle time. To address this problem, we propose a retention-aware auto-refresh (RAAR) technique by all-bank, partial-bank, and per-bank to reduce unnecessary refresh operations according to the DRAM cells’ retention time. Experimental results show that our RAAR technique not only reduces refresh power effectively, but also improves the memory access performance. |
| Title | Stochastic Number Generation with Internal Signals of Logic Circuits |
| Author | *Naoya Kubota, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City University, Japan) |
| Page | pp. 94 - 95 |
| Keyword | Stochastic Computing, Stochastic number, chi-square-value |
| Abstract | Stochastic computing (SC) is an approximate computation with random numbers. In this study, we propose a new SC scheme in which internal signals of logic circuits are exploited for generating random numbers. This scheme can eliminate random number generators (e.g., linear-feedback shift-registers), and accordingly reduce the hardware cost for SC without losing the accuracy. |
| Title | A Branch-and-Bound Algorithm for Scheduling of Data-Parallel Tasks |
| Author | *Yang Liu, Lin Meng, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan University, Japan) |
| Page | pp. 96 - 100 |
| Keyword | task scheduling, multicore, data parallelism, branch-and-bound |
| Abstract | This paper studies a task scheduling problem which schedules a set of data-parallel tasks on multiple cores. Unlike most of previous literature where each task is assumed to run on a single core, this work allows individual tasks to run on multiple cores in a data-parallel fashion. Since the scheduling problem is NP-hard, a couple of heuristic algorithms which find near-optimal schedules in a short time were proposed so far. In some cases, however, exactly-optimal schedules are desired, for example, in order to evaluate heuristic algorithms. This paper proposes an exact algorithm to find optimal schedules in a reasonable time. The proposed algorithm is based on depth-first branch-and-bound search. In the experiments, the proposed algorithm could successfully find optimal schedules for task-sets of 50 tasks in a practical time. |
| Title | Automatic Enable Candidate Extraction for Backward Sequential Clock Gating |
| Author | *Shinji Kimura, Tomoya Goto, Masao Yanagisawa (Waseda University, Japan) |
| Page | pp. 101 - 106 |
| Keyword | CLock gating, Satisfiability |
| Abstract | Clock gating is a widely used dynamic power reduction method for LSI by stopping clock changes to registers. There needs an enable signal to apply clock gating, and automatic enable detection and selection has been worked hard. Recently clock gating considering the past or the future time steps has been paid attention as sequential clock gating. The paper proposes an automatic extraction method of candidates of backward sequential clock gating control using the satisfiability condition on time expanded circuit. The detected candidate can also be used for forward sequential clock gating. |
| Title | A Decision Diagram to Analyze Probabilistic Behavior of Circuits |
| Author | *Kodai Abe, Shigeru Yamashita (Ritsumeikan University, Japan) |
| Page | pp. 107 - 112 |
| Keyword | Decision Diagram, Probability Analysis, Binary Decision Diagram for Probabilities |
| Abstract | In near future, we may encounter serious problems in digital circuits due to probabilistic behaviors that are caused by many factors, e.g., soft-errors, variability of transistors, etc. Thus, we need to develop a good methodology to evaluate how logic circuit is dependable even in the logic design level. To do so, this paper proposes a framework to use what we call probability functions to calculate the error probability of the circuit. Then, we can naturally define an efficient data structure called Binary Decision Diagram for Probabilities (BDDP) to manipulate probability functions. To successfully utilize this new data structure, we carefully define the rule to maintain the canonical property of BDDPs, and also define recursive operations to calculate the AND/OR/NOT relations of probability functions. Our operations can be implemented efficiently as the conventional BDD operations. From our preliminary experiments we would expect a possibility of BDDPs which should be verified further in our future work. |
| Title | Random Delay Elements for Tamper Resistant Asynchronous Circuits based on 2-phase Handshaking Protocol |
| Author | *Daiki Toyoshima, Tatsuya Ishikawa, Atsushi Kurokawa, Masashi Imai (Hirosaki University, Japan) |
| Page | pp. 113 - 118 |
| Keyword | tamper resistant, asynchronous circuit, random delay, 2-phase handshaking protocol |
| Abstract | Side-channel-attacks have become one of the serious issues in the modern VLSI systems. In this paper, we propose a design method of tamper-resistant asynchronous circuits using random delay elements. We also present the circuit structure of random delay elements for asynchronous circuits based on the 2-phase handshaking protocol which does not distinguish between a rising edge and a falling edge. The delay cells are designed and evaluated using 0.18μm process technology and their characteristics are shown. |
| Title | Optimization of Temperature Dependent Intentional Skew for Temperature Aware Timing Design |
| Author | *Makoto Soga, Mineo Kaneko (Japan Advanced Institute of Science and Technology, Japan) |
| Page | pp. 119 - 124 |
| Keyword | clock skew, temperature, variation |
| Abstract | In this paper, the optimization of temperature dependent intentional skew for extending operating temperature range of LSI is proposed. Our discussion is based on the linear temperature dependency of delays, and assume a most general form of temperature dependency in intentional skews. The major contributions of this paper are (1) optimization algorithm for finding best parameter values of intentional skews, and (2) an optimum choice of temperature dependency of intentional skews for extending operating temperature range. |
| Title | Performance Evaluation Platform for Programmable Interconnect Architecture Exploration |
| Author | Kohei Yamamoto, Toshiki Morioka, Tomoya Inoue, *Masataka Mori, Yukio Mitsuyama (Kochi University of Technology, Japan) |
| Page | pp. 125 - 128 |
| Keyword | reconfigurable architecture, placement and routing, architecture exploration |
| Abstract | This paper proposed a performance evaluation platform for programmable interconnect architecture exploration. This platform enables repetitive modifications of programmable interconnect architecture, its performance evaluations based on application mapping results, and its RTL simulation with a configuration data obtained from an application mapping result, efficiently. In the platform, programmable interconnect architecture is defined by some parameters called wire-parameters, and the configuration files for placement and routing tools are automatically generated from the wire-parameters. We can evaluate the performance of reconfigurable architecture based on accurate path delay and area, which are estimated based on an application mapping result obtained by the placement and routing tools. Furthermore, this evaluation platform can generate RTL source codes of the reconfigurable array according to the wire-parameters, and enables an RTL simulation of the reconfigurable architecture with a configuration data obtained from application mapping result. |
| Title | Efficient Standard Cell Layout Synthesis Algorithm Considering Various Driving Strengths |
| Author | *Hong-Yan Su, Bo-Shung Wang, Sin-Ye Hsieh, Yih-Lang Li (Department of Computer Science, National Chiao Tung University, Taiwan), I-Hsun Wu, Chang-Chung Wu, Wei-Chiang Shih (M31 Technology Corporation, Taiwan), Hidetoshi Onodera (Dept. of Communications and Computer Engineering, Kyoto University, Japan), Masanori Hashimoto (Department of Information Systems Engineering, Osaka University, Japan) |
| Page | pp. 129 - 134 |
| Keyword | Cell layout synthesis, timing closure |
| Abstract | For reaching timing closure under distinct scenarios, such as different negative slacks, the required transistor sizes for a cell instance may not match any of the pre-designed cells in the library. In this paper we propose a timing–closure oriented cell layout synthesis algorithm to generate a high-driving cell layout accommodating demanded static folded large transistors. The proposed primitive-driving cell synthesis flow consists of two steps; (1) routability-aware dynamic-programming (DP) based transistor placement considering diffusion-shape constraint and pin-metal location for routability, and (2) resource-aware cell routing flow consisting of resource estimation scheme, simultaneous pattern routing and post-routing optimization. Higher-driving cells are synthesized based on the design of primitive-driving cells and static folded transistors with a LEGO-like assembling approach followed by the abovementioned resource-aware cell routing. Experimental results show that all the synthesized layouts have identical areas to handcrafted layouts of commercial 28nm cell library and use less metal 2 routing resource as well. Cell characterization outcome also demonstrates that the proposed cell synthesis algorithm can yield cell layouts with comparable performances to handicraft layouts of commercial cell library in terms of delay, leakage and power thanks to the proposed high-routability transistor placement and effective routing resource planning. |
| Title | Fast Length-Matching Routing for Rapid Single Flux Quantum Circuits |
| Author | *Nobutaka Kito (Chukyo University, Japan), Kazuyoshi Takagi, Naofumi Takagi (Kyoto University, Japan) |
| Page | pp. 135 - 140 |
| Keyword | routing, RSFQ circuits, simulated annealing, length-matching |
| Abstract | A fast routing method for Rapid Single Flux Quantum (RSFQ) digital circuits is proposed. The method deals with channel routing between adjacent columns of active devices. To perform routing considering difference between timing variabilities of active devices and those of passive transmission lines (PTLs) used for transmitting signals, the proposed method provides route of PTLs with specified additional length for delay insertion. The method is based on simulated annealing, and a special representation method of routing is proposed for searching solutions efficiently. |
| Title | A Comparative Study on Multisource Clock Network Synthesis |
| Author | Wen-Hsin Chen, Chun-Kai Wang, *Hung-Ming Chen (NCTU Taiwan, Taiwan), Yih-Chih Chen, Cheng-Hong Tsai (Global Unichip Corp, Taiwan) |
| Page | pp. 141 - 145 |
| Keyword | CTS, multisource, skew optimization |
| Abstract | Hybrid clock architecture offers a compromise between tree and mesh. While most of the relative works focus on tree-driven-mesh configuration, we are interested in the performance and optimization of multisource CTS flow provided by IC Compiler, which applies a coarse mesh with local sub-trees. Therefore, we analyze the QOR of conventional clock tree and multisource CTS on a real industrial design. We also propose several heuristic approaches to improving the performance of multisource CTS, especially for skew optimization. According to the experiment results, we reveal the benefits and drawbacks of each method, give some guidelines for determining the proper configuration for a design, and then summarize some future research directions. |
| Title | Target Concentration Exploration for Reactant Minimization on Digital Microfluidic Biochips |
| Author | Yi-Ling Chen, Yung-Chun Lei, *Juinn-Dar Huang (National Chiao Tung University, Taiwan) |
| Page | pp. 146 - 151 |
| Keyword | sample preparation, target concentration value determination, cost minimization, digital microfluidic biochip |
| Abstract | Lab-on-a-chip is one of the most sophisticated technologies, while sample preparation is the process that mixes buffer and reactant to achieve the desired target concentration. Since the reactant consumption takes a notable part of the total cost, minimizing its usage is preferable. Different from existing techniques, we propose two algorithms that can select a feasible concentration value within a given range for cost minimization. Experimental results show that the proposed methods can further reduce the reactant cost up to 20%. |
| Title | Practical and Accurate SOC Estimation System for Lithium-Ion Batteries by EKF with Adaptive Noise Covariance Estimation |
| Author | *Lei Lin, Kiyotsugu Takaba, Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 152 - 157 |
| Keyword | Battery Management System, Lithium-Ion Battery, SOC Estimation, extended Kalman filter |
| Abstract | In this paper, we discuss a state-of-charge (SOC) estimation system for lithium-ion batteries using an extended Kalman filter (EKF) with adaptive noise covariance estimation. The EKF can affect a highly effective state estimation using the assuming that prior information about the stochastic characteristics of the system disturbances and observation noises is known. However, it is very difficult to obtain such prior information. The stationary noise covariance estimation method must estimate the noise covariance using the examination data in advance. The noise covariance estimation must use a large examination data. To remedy this problem, we propose herein an adaptive noise covariance estimation method for accurately estimating the SOC from observation data and for verifying the accuracy by examination. However, the noise is not stationary in real system. To resolute this problem in real system, we proposed a method to estimate the noise using moving window. In our experiment, the adaptive noise covariance estimation method’s SOC estimation error can approach to the SOC estimation error using the optimal stationary noise covariance setting. |
| Title | True Random-Bit Generation Using a Continuous-Time Chaotic Oscillator |
| Author | *Chatchai Wannaboon, Masayoshi Tachibana (Kochi University of Technology, Japan) |
| Page | pp. 158 - 161 |
| Keyword | Random-Bit Generator, Chaotic Oscillator |
| Abstract | This paper presents a true random-bit generation through a continuous-time chaotic oscillator, which provides automatically chaotic signals and is fully implemented on 0.18 CMOS standard technology. Chaotic dynamics of the oscillator are exhibited in terms of chaotic strange attractor in phase-space domain. In order to achieve true-random property, a simple designed of post-processing method is utilized. Finally, the quality of randomness is analyzed through 1,000,000 binary sequences which are verified by statistical test methods and NIST standard tests suite. The proposed system has offered a cost-effective and a compact random-bit generator for computer security applications. |
| Title | Hardware Acceleration Technique for Radio-resource Scheduler in Ultra-high-density Distributed Antenna Systems |
| Author | *Yuki Arikawa, Hiroyuki Uzawa, Takeshi Sakamoto, Satoshi Shigematsu (NTT Device Innovation Center, Japan) |
| Page | pp. 162 - 163 |
| Keyword | 5G, Scheduler, Hardware acceleration |
| Abstract | This paper presents a hardware acceleration technique for the scheduling process in ultra-high-density distributed antenna systems for 5G mobile communications systems. In 5G systems, the overall system throughputs for a huge number of combinations of antennas and user equipment for communications have to be calculated in the scheduling process. In order to accelerate the calculation, the proposed technique calculates the throughputs of each UE simultaneously. Moreover, it obtains the system throughput for combinations at every clock cycle in the pipeline. Experimental results show that the proposed technique performs the calculation of system throughput 60 times faster than without the acceleration. The proposed technique enables a future practical 5G system. |
| Title | An Overlay Architecture for FPGA-Based Industrial Control Systems Designed with Functional Block Diagrams |
| Author | *Taisei Segawa, Yuichiro Shibata, Yudai Shirakura, Kenichi Morimoto, Hidenori Maruta, Fujio Kurokawa (Nagasaki University, Japan), Masaharu Tanaka (Mitsubishi Heavy Industries, Japan), Masanori Nobe (Mitsubishi Hitachi Power Systems, Japan) |
| Page | pp. 164 - 169 |
| Keyword | FPGA, HLS, FBD |
| Abstract | This paper discusses FPGA implementation of industrial control logic described in a function block diagram (FBD) language. First, we evaluate an approach where FBD descriptions are directly translated to FPGA hardware using a high level synthesis technique. Second, aiming at improving resource utilization efficiency, we proposed an overlay architecture which helps resource sharing of the same arithmetic structure utilized in different control logic sheets. Evaluation results show that the propose architecture can significantly reduce resource requirements per control logic sheet, at a cost of acceptable performance degradation. |
| Title | Past and Future 25 Years of Synthesis and System Integration |
| Author | Moderator: Isao Shirakawa (University of Hyogo, Japan), Panelists: Giovanni De Micheli (EPFL, Switzerland), Youn-Long Lin, Ren-Song Tsay (National Tsing Hua University, Taiwan), Peter Marwedel (Technical University of Dortmund, Germany), Organizer: Nagisa Ishiura (Kwansei Gakuin University, Japan) |
| Page | p. 170 |
| Abstract | Since the foundation of SASIMI in 1989, we have experienced tremendous evolutions in the area of electronic design technology, as SASIMI also evolved from “Synthesis And SImulation Meeting and International interchange,” through “The workshop on Synthesis And System Integration of MIxed technologies” to “The workshop on Synthesis And System Integration of Mixed Information technologies.” What have really happened in the last years and what will come in the next 25 years? Starting with the enlightening short talks from the distinguished panelists, we would like to discuss the future of Synthesis and System Integration. |
| Tuesday, October 25, 2016 |
| Title | Wide Bandgap Analog and Mixed-signal IC Design for Advanced Power Electronics |
| Author | *Alan Mantooth (University of Arkansas, U.S.A.) |
| Page | p. 171 |
| Abstract | Economy and performance are benefits that come with high power density power electronics, just as in the case of VLSI electronics. High density power electronics require the heterogeneous integration of disparate technologies including power semiconductor devices, driver, protection and control circuitry, passives and voltage isolation techniques into single modules. Such integration activity was central to the Google Little Box Challenge competition conducted last year. One of the keys to advancing power electronic integration has been the commercial reality of wide bandgap power semiconductor devices made from silicon carbide and gallium nitride. The ability to design and manufacture wide bandgap integrated circuits as drivers, controllers, and protection circuitry allows them to be packaged in close proximity to the power device die to minimize parasitics that would adversely impact system performance. These impacts include excessive ringing, noise generation, power loss, and, potentially, self-destruction. This talk will describe the state of the art in wide bandgap analog and mixed-signal IC design including example circuits such as amplifiers, data converters, controllers, and protection circuits and their integration into power electronic platforms. A synthesis tool under development for heterogeneous power circuit layout will be briefly described as a capstone to the application space descriptions. |
| Title | Extending Distributed Control for High-Level Synthesis beyond Borders of Basic Blocks |
| Author | *Miho Shimizu, Nagisa Ishiura (Kwansei Gakuin University, Japan) |
| Page | pp. 172 - 177 |
| Keyword | high-level synthesis, variable latency units, distributed controller |
| Abstract | This paper proposes an extension of distributed control, which enables efficient run-time scheduling of variable latency operations, to multiple dataflow graphs. Conventional high-level synthesis methods determine the execution schedule of operations statically assuming that their latencies are fixed. However, actual circuits contain so-called variable latency units whose execution cycles may vary depending on various run-time factors. Our method extends the Del Barrio's distributed control to handle multiple dataflow graphs. It enables dynamic scheduling of operations beyond the boundaries of basic blocks which results in fewer execution cycles than those by conventional centralized control with loop scheduling and trace scheduling. |
| Title | Proposal of an Efficient Clock-Gating Mechanism for Multi-Core Processors to Reduce Power Supply Noise |
| Author | *Jun Kawabe, Yoshinori Takeuchi, Jaehoon Yu, Masaharu Imai (Osaka University, Japan) |
| Page | pp. 178 - 183 |
| Keyword | multicore, reliability, clock gating, power supply noise |
| Abstract | This paper proposes an efficient clock-gating mechanism to reduce the power supply noise of multi-core processors. The intensity of power supply noise is proportional to the amount of current change and is a critical issue for multi-core processors due to the wide range of current fluctuation. The proposed mechanism is designed to suppress the current change by controlling the clock supply to each core. In experimental results, the proposed method reduced current fluctuation by 37.3% without processing performance degradation. |
| Title | Automatic Netlist Transformation for WDF-Based Analog Emulator |
| Author | Hsu-Ping Yang, *Hsin-Ju Hsu, Chun Wang, Chien-Nan Jimmy Liu, Jing-Yang Jou (National Central University, Taiwan) |
| Page | pp. 184 - 189 |
| Keyword | Wave Digital Filter, Analog Circuit Emulation |
| Abstract | System verification is still a big challenge for SOC designs with AMS circuits. Unlike well accepted FPGA emulation for digital circuits, there is still no practical solution for the emulation of mixed-signal circuits. Wave digital filter (WDF) based method is a possible approach to emulate analog circuits in digital environment [1]. Based on that technique, this paper proposes an automatic transformation flow to handle the translation from circuit netlist to its corresponding WDF structure, with optimized tree height and number of adaptors. As demonstrated in the circuit examples, the proposed algorithm is able to generate correct WDF structures and reduce the tree height, which can further increase the operation speed of the emulator. |
| Title | Nonlinear Optimization Solver with Multiple Precision Arithmetic |
| Author | *Yuya Matsumoto, Hiroshige Dan (Kansai University, Japan) |
| Page | pp. 190 - 194 |
| Keyword | Nonlinear programming, Multiple precision arithmetic |
| Abstract | Double precision arithmetic for nonlinear optimization problems (NLP) sometimes fails to solve some ill-posed problems. On the other hand, multiple precision arithmetic has attracted much attention recently as a brute-force method for avoiding numerical errors. In this research, we implemented an optimization solver for NLP by using multiple precision arithmetic and examined the advantage of multiple precision arithmetic for NLP through numerical results. |
| Title | High Speed Cycle-Accurate Processor Simulation Through Ahead of Time Compilation |
| Author | *Lovic Gauthier (National Institute of Technology, Ariake College, Japan) |
| Page | pp. 195 - 200 |
| Keyword | simulator, processor, ahead of time compilation, binary translation, just in time compilation |
| Abstract | This paper presents techniques for implementing fast cycle-accurate processor simulators based on ahead of time compilation (AoT). AoT is usually assumed to suffer from a large compilation overhead, and is difficult to implement due to the dynamic behavior of some instructions. The paper explains how to overcome these issues and presents experiments with MIPS processor simulators showing that our approach can surpass state of the art methods and can simulate more than one billion clock cycles per second. |
| Title | Prototype Speed Limit Sign Recognition System Implementation on Rapid Prototyping Platform |
| Author | *Anh-Tuan Hoang, Takumi Okamoto, Tetsushi Koide (Research Institute for Nanodevice and Bio Systems, Hiroshima University, Japan) |
| Page | pp. 201 - 202 |
| Keyword | ADAS, traffic sign recognition, FPGA, Rapid Prototyping Platform |
| Abstract | This paper introduce our prototype speed limit traffic sign recognition system implementation on Rapid Prototyping Platform. The system utilizes simple image feature such as area luminosity difference of grayscale image to detect traffic sign candidates and block histogram feature in binary image to recognize the speed. Combination of those simple traffic sign features helps our algorithm to achieve 100% of accuracy in recognizing speed limit traffic signs in daytime and over 90% in hard lightning condition such as rainy night. Simplicity in computation enables real-time processing (> 30 fps) and relatively small hardware occupied. The design occupies 11,713 slices LUTs (0.95%) and 5,060 slice registers (0.2%) of the hardware available on the Virtex xc7v2000t (1,221,600 slice LUTs and 2,443200 slice registers) on the Rapid Prototyping Platform Protium. |
| Title | Reconfigurable Processor Array Architecture for Deep Convolutional Neural Networks |
| Author | *Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura (Hokkaido University, Japan) |
| Page | pp. 203 - 204 |
| Keyword | Deep Learning, Neural Network, Reconfigurable Architecture, CNN |
| Abstract | A convolutional neural network (CNN) is a type of neural network that has achieved high accuracy on many tasks like image recognition. Because a CNN requires a large amount of computation, various types of accelerators have been invented. However, the difference between the two types of CNN layers decreases the availability of the accelerators. We propose a flexible and efficient accelerator, where the simple processing elements are parallelized and the data paths are controlled appropriately. |
| Title | On Component Ratio of RECON Spare Cells for ECO-Friendly Design Style |
| Author | *Takeshi Sawai, Ayano Takezaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe University, Japan) |
| Page | pp. 205 - 210 |
| Keyword | ECO, reconfigurable cell, error diagnosis, technology remapping |
| Abstract | This paper presents an approach to obtain suitable component ratio of 2T/4T/6T-RECON spare cells for the ECO-friendly design style in order to implement the changes caused by ECO’s suppressing increase in the maximum delay time. By using statistics on RECON cell types and logic functions to fix ECO’s, we can determine suitable component ratio of RECON spare cells. Experimental results have shown that the proposed approach is effective to fix post-mask ECO’s reducing increase in the maximum delay time. |
| Title | Theorem-proving Verification of Multi-clock Synchronous Circuits on Multimodal Logic |
| Author | *Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto University, Japan) |
| Page | pp. 211 - 212 |
| Keyword | formal method, formal verification, theorem proving, multi-clock synchronous circuit |
| Abstract | Formal verification methods for synchronous circuits are widely used, but almost all of the methods are limited to single-clock synchronous circuits. In this paper, we propose a formal verification method for multi-clock synchronous circuits. The proposed verification method is in theorem-proving manner and based on multimodal logic. We also show an example of verification of a clock switching circuit by using the method. |
| Title | Hardware Trojan Insertion Difficulties into Synchronous and Asynchronous Circuits |
| Author | *Masashi Imai (Hirosaki University, Japan), Tomohiro Yoneda (National Institute of Informatics, Japan) |
| Page | pp. 213 - 218 |
| Keyword | hardware Trojan, asynchronous circuit, majority voted-enable latch |
| Abstract | Hardware trojan threats have become one of the serious issues in the modern VLSI systems. In this paper, we discuss the differences of hardware trojan insertions between synchronous circuits and asynchronous circuits. We propose a design method to tolerate a hardware trojan insertion in asynchronous circuits using voted-enable-latches and show some evaluation results using 130nm process technology. |
| Title | A Delay Adjustment Method for Asynchronous Circuits with Bundled-data Implementation Considering a Latency Constraint |
| Author | *Kazumasa Yoshimi, Hiroshi Saito (The University of Aizu, Japan) |
| Page | pp. 219 - 224 |
| Keyword | asynchronous circuits, timing constraints, delay adjustment |
| Abstract | In this paper, we propose a delay adjustment method for asynchronous circuits with bundled-data implementation considering a latency constraint. We modify delay adjustments for hold and idle constraints for an existing method. The experimental results show that the proposed method reduces energy consumption with the reduction of the number of delay adjustments and the reduction of the number of cells used for delay elements. |
| Title | Path Grouping Approach for Efficient Candidate Selection of Replacing NBTI Mitigation Logic |
| Author | *Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato (Kyoto University, Japan) |
| Page | pp. 225 - 230 |
| Keyword | NBTI, NBTI mitigation, reliability, aging |
| Abstract | We propose a fast replacement method of the negative bias temperature instability mitigation logics. In our approach, to accelerate the exploration of a set of gates to be replaced, critical path candidates are partitioned into several groups based on similarity between paths, and only the representative paths of each group are evaluated. Experimental results show the proposed approach speeds up the computation time by 13.5 times while retaining the same level of the mitigation gain compared to the conventional approach. |
| Title | Semi-Automated Analog Placement based on Margin Tolerances |
| Author | *Eric Lao, Marie-Minerve Louërat, Jean-Paul Chaput (Laboratoire d'informatique de Paris 6, France) |
| Page | pp. 231 - 235 |
| Keyword | Analog layout, analog placement, slicing tree, analog automation |
| Abstract | Digital circuit design is extensively assisted by modern automation tool unlike analog design which is still a manual task because of the complexity of the interactions between devices. This paper presents a semi-automated analog placement based on margin tolerances controlled by the designer by creating analog circuits organized in row similar to digital circuits structure. The results show the ability of our tool at generating multiple layouts respecting designer’s constraints. |
| Title | An Efficient Gaussian Mixture Reduction to Two Components |
| Author | Naoya Yokoyama, *Daiki Azuma, Shuji Tsukiyama (Chuo University, Japan), Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 236 - 241 |
| Keyword | Gaussian Mixture reduction, Gaussian mixture model, statistical static timing analysis |
| Abstract | In statistical methods, such as statistical static timing analysis, Gaussian mixture model (GMM) is a useful tool for representing a non-Gaussian distribution and handling correlation easily. In order to repeat various statistical operations such as summation and maximum for GMMs efficiently, the number of components should be restricted around two. In this paper, we propose a method for reducing the number of components of a given GMM to two (2-GMM) such that the mean and the variance of the 2-GMM are equal to those of original GMM and the normalized integral square error of 2-GMM PDF is minimized. In order to demonstrate the performance of the proposed methods, we show some experimental results. |
| Title | Thermal Circuit Identification of Power MOSFETs through In-Situ Channel Temperature Estimation |
| Author | *Kazuki Oishi, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato (Kyoto University, Japan) |
| Page | pp. 242 - 247 |
| Keyword | thermal model, power MOSFET, device model, circuit simulation |
| Abstract | We propose a novel methodology for identifying thermal equivalent circuit of power MOSFETs. Drain current of the MOSFET is utilized to estimate channel temperature where heat actually generates. Two measurement methods, i.e., constant voltage (CV) method and constant power (CP) method, are proposed wherein waveforms of the input power for the target device are different. Through experiments using a commercial SiC power MOSFET, the accuracy of the proposed method is valideted. |
| Title | Evaluation of PLL Layouts based on Transistor Array-style |
| Author | *Atsushi Nanri, Bo Liu, Yuki Miura, Shigetoshi Nakatake (The University of Kitakyushu, Japan) |
| Page | pp. 248 - 251 |
| Keyword | Transistor array, analog layout, PLL |
| Abstract | This work proposes an analog characterization module to imitate (emulate) various analog components as essential technologies for analog-specific computation. This module converts an analog input signal into digital by an ADC circuit, makes use of digital signal processing technologies to characterize the signal as expected, and outputs the analog signal converting by a DAC. In this paper, characterizing the proposing module as a resistance, we demonstrate a use case of realizing a programmable gain amplifier by introducing the module. |
| Title | Single Row Cell Placement Considering Self-aligned Double Patterning |
| Author | Ye-Hong Chen, *Ting-Chi Wang (National Tsing Hua University, Taiwan) |
| Page | pp. 252 - 257 |
| Keyword | self-aligned double patterning, cell placement |
| Abstract | Self-aligned double patterning (SADP) has become one of the promising lithography techniques for advanced nodes. In SADP, overlay violation is a critical issue for fabrication, so how to minimize it is important. Most of existing works focus on layout decomposition and routing, while very few attempts are on placement. In this paper, we consider a single-row cell placement problem, where overlay violation is minimized by two placement techniques, white space insertion and cell flipping. Experimental results show our methods can effectively reduce overlay violation. |
| Title | A Lithium Ion Battery Aging Simulator with Calibration Functions |
| Author | *Yukinori Hayakawa, Lei Lin, Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 258 - 263 |
| Keyword | Lithium Ion Battery, Aging Simulator, Calibration |
| Abstract | This paper discusses a practical degradation simulator for assembled battery of Lithium ion batteries. The degradation simulator has calibration function. The function is used to various conditions based on the measured vales. As a result, the accuracy of degradation simulator is improved. |
| Title | A Full Charge Capacity Estimation Algorithm for Li-ion Batteries Based on Recursive Least-Squares Identification with Adaptive Forgetting Factor Tuning |
| Author | *Hironori Ono, Lei Lin, Masahiro Fukui, Kiyotsugu Takaba (Ritsumeikan University, Japan) |
| Page | pp. 264 - 267 |
| Keyword | Battery Management System, Li-ion Battery, System Identification |
| Abstract | This paper discuss an Full Charge Capacity (FCC) estimation system for lithium ion batteries based on the recursive least-squares identification. The accuracy of the estimation is depended on accuracy of the state of charge (SOC) estimation. We have newly formulated the adaptive forgetting factor for recursive least-squares identification. As the result, the error rate of the SOC estimation has been improved. The evaluation shows that the new FCC estimation system can be used for various temperature conditions. |
| Title | A Hardware Architecture to Perform K-means Clustering for Learning-Based Super-Resolution Combining Self-Learning and Prior-Learning Dictionaries |
| Author | *Daichi Murata, Ayumi Kiriyama, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe University, Japan) |
| Page | pp. 268 - 273 |
| Keyword | learning-based super-resolution, self-learning dictionaries, hardware architecture, resource sharing, hardware system design |
| Abstract | This paper presents a hardware architecture to perform K-means clustering for learning-based super-resolution combining self-learning and prior-learning dictionaries. Using PCA (Principal Component Analysis) and a k-d tree is the key to save hardware resources and processing time. Moreover, we propose a technique to save resources by sharing computing elements. Experimental results have shown that our architecture reduces 63% ALUT (Adaptive Look Up Table) area, and speeds up more than 5.8 times as fast as a conventional circuit. |
| Title | On-Chip Temperature Sensing using a Reconfigurable Ring Oscillator |
| Author | *Tadashi Kishimoto, Hidetoshi Onodera (Kyoto University, Japan) |
| Page | pp. 274 - 279 |
| Keyword | Leakage Current, on-chip sensor, temperature, reconfigurable, MOSFET |
| Abstract | This paper proposes a temperature monitoring scheme using a reconfigurable ring oscillator that has been proposed to estimate process variation. New circuit configurations, whose delay characteristics are sensitive to leakage current, are proposed to exploit the exponential dependence of the leakage current to temperature. Based on transistor-level simulation assuming a 65 nm process technology, the oscillation frequency of the proposed circuit topology shows the temperature sensitivity of 5.0 %/℃ at 20 ℃ and 2.9 %/℃ at 80 ℃ and low voltage sensitivity of 0.28 ℃/10 mV at the supply voltage of 0.9 V and the temperature of 25 ℃. |
| Title | A Shift HSV Algorithm for a Low-Power Monitoring System using an FPGA toward Internet of Things Agriculture |
| Author | Takahisa Kurose (Ehime University, Japan), *Hiroki Nakahara, Shimpei Sato (Tokyo Institute of Technology, Japan), Tetsuo Morimoto (Ehime University, Japan) |
| Page | pp. 280 - 281 |
| Keyword | FPGA, IoT, Low Power Design |
| Abstract | An agriculture monitoring system observes growth of agricultural crops. It requires high-performance with a battery drivable system. To satisfy them, we use an FPGA, and realize a shift operation based HSV converter. Although the proposed shift-based HSV converter causes 8.4\% error compared with the original HSV one, its power consumption is 26.51 times smaller than the original one. |
| Title | The Challenges and Future of Electronic-System Level Design Automation |
| Author | *Ren-Song Tsay (National Tsing Hua University, Taiwan) |
| Page | p. 282 |
| Abstract | In this talk, the speaker will introduce new concepts of software/hardware system abstractions for effective system modeling and design automation. As IC design automation reached its peak at the turn of the century, the industry unsurprisingly asks for upgrade to electronic system-level design automation. However, the complexity and diversity, particularly the inclusion of both software and hardware components, of system designs are of huge challenges. In contrast to the successful abstractions of transistor-, gate- and RTL-level designs, the traditional system-level transaction models and function-time models seem to be of limited use. It is concluded that proper characterizations of system behaviors, particularly inter-component interactions (shared-data accesses, signals, interrupts, etc.) and timing behaviors (bus contentions, cache misses, preemptions, etc.) are identified to be keys to system modeling and designs. |
| Title | Mathematical Algorithm Hardware Description Languages for System Level Modeling |
| Author | Ryo Hikawa, *Ryuji Kishimoto, Takashi Kambe (Kindai University, Japan) |
| Page | pp. 283 - 284 |
| Keyword | mathematical algorithm description language, HDLMath, System Level Modeling |
| Abstract | Mathematical modeling is an important approach for both solving problems and visualizing the abstract concepts involved in system and/or products. Thus a mathematical algorithm description language (HDLMath) should be capable of describing and verifying the entire behavior using mathematical algorithms of electronic systems. In this paper, the functional requirements of HDLMaths are proposed and several current HDLMaths are compared from a design viewpoint. |
| Title | High-Level Synthesis of Embedded Systems Controller from Erlang |
| Author | Hinata Takebayashi, Nagisa Ishiura, *Kagumi Azuma (Kwansei Gakuin University, Japan), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM RI, Japan) |
| Page | pp. 285 - 290 |
| Keyword | high-level synthesis, Erlang, embedded system |
| Abstract | This article presents a method of specifying the behavior of embedded systems by a subset of Erlang, from which RTL hardware is synthesized. Assembly codes of the BEAM virtual machine compiled from Erlang programs are converted into CDFGs (control dataflow graphs), which are synthesized into Verilog HDL by the back-end of the high-level synthesizer ACAP. A prototype system based on the proposed method implemented in Perl5 has successfully synthesized a simple two-process Erlang program into logic-synthesizable Verilog HDL codes. |
| Title | A Data Effect Aware Microcomponent-Based Estimation Approach for Accurate System-Level Memory Device Power Evaluation |
| Author | *Chi-Kang Chen (Industrial Technology Research Institute and National Tsing Hua University, Taiwan), Hsin-I Wu, Chi-Ting Hsiao, Ren-Song Tsay (National Tsing Hua University, Taiwan) |
| Page | pp. 291 - 296 |
| Keyword | Memory, Power, DRAM, Microcomponent |
| Abstract | As memory is a major power dominant, we propose a highly efficient microcomponent-based approach with data-aware refinement for accurate system-level power estimation. The proposed method pre-calibrates the power consumption pattern of each identified microcomponent for power simulation. To achieve high accuracy, the data variation effect is considered and a simple interpolation technique is proposed to further boost accuracy. The proposed approach produces accurate results of less than 2% error rate in average for system-level power analysis. |
| Title | Analysis of Co-Controlling Voltage/Frequency of Cores and DRAMs of Chip Multi-Processors with 3D-stacked DRAMs for Thermal Management |
| Author | *Yi-Jung Chen (National Chi Nan University, Taiwan), Chia-Lin Yang, Ping-Sheng Lin, Yi-Chang Lu (National Taiwan University, Taiwan) |
| Page | pp. 297 - 302 |
| Keyword | 3D-stacked DRAMs, Chip-MultiProcessors, Thermal Management |
| Abstract | Thermal control is a critical issue to Chip-Multiprocessors (CMPs) with 3D-stacked DRAMs due to its high power density. Existing thermal managements for 3D ICs all perform thermal control on cores only because lowering the power-level of cores can also lower DRAM access frequency. However, as the power consumption of single DRAM access increases with the number of DRAM stacks and the width of the vertical links, reducing the power consumption per DRAM access as well is also crucial. In this paper, we characterize the thermal and performance behavior of the target architecture when the voltage and frequency levels of cores and DRAMs are synergistically controlled. |
| Title | Introducing Real Constraints in Partitioned ILP-Based Binding in High-Level Synthesis |
| Author | Nagisa Ishiura, *Yuuki Oosako (Kwansei Gakuin University, Japan) |
| Page | pp. 303 - 304 |
| Keyword | high-level synthesis, binding, partitioned ILP, real linear constraints |
| Abstract | This paper presents an efficient ILP-based method of binding in high-level synthesis. The binding problem is formultated as partitioned ILP where linear inequations of the other unsolved portions without integer constraints are added. |
| Title | A Framework for Automatic Generation of Application-Specific FPGA-based SoC |
| Author | *Tetsuo Miyauchi, Kiyofumi Tanaka (Japan Advanced Institute of Science and Technology, Japan) |
| Page | pp. 305 - 310 |
| Keyword | real-Time, multicore, RTOS, application-specific, configuration |
| Abstract | As IoT or CPS devices/systems increase, efficient, cost effective real-time embedded systems are getting important. For providing various highly application-specific systems, we are developing a design environment based on a framework for automatic generation of application-specific FPGA-based SoC. Use of the environment makes it possible for designers to automatically generate a target system design which is highly adapted to the application. Our targets for optimization/customization are multicore processors, real-time operating systems, and acceleration hardware in FPGA. |
| Title | Fast Song Searching by Simultaneous Execution of HiFP2.0 and Staged LSH |
| Author | *Masahiro Fukuda, Yasushi Inoguchi (Japan Advanced Institute of Science and Technology, Japan) |
| Page | pp. 311 - 316 |
| Keyword | Audio Fingerprint, HiFP, Staged LSH, FPGA |
| Abstract | Fingerprinting techniques are generally used to search a song quickly. In this paper, the fingerprint generation method HiFP2.0 and the identification method Staged LSH are combined and executed almost simultaneously. This method reduced around 3600 clock cycles and was about 8.54 % faster than the sequential execution of them in the case that the song of the query was a bit distorted by the lossy compression of MP3. |
| Title | An Error Diagnosis Technique Based on Averaged EPI Values to Extract Error Locations Sets |
| Author | *Ayano Takezaki, Takeshi Sawai, Hiroyuki Sakamoto, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe University, Japan) |
| Page | pp. 317 - 322 |
| Keyword | error diagnosis, ECO, EPI, error location set |
| Abstract | This paper presents an error diagnosis technique based on averaged EPI (Error Possibility Index) values to extract error location sets. Each EPI corresponds to the controllability of a location to an inconsistent primary output for an input pattern. By averaging EPI values for each location, we can reduce the number of initial sets. Experimental results have shown that the proposed technique is effective in reducing error location sets and processing time for screening them. |
| Title | Minimum Energy Point Tracking under a Wide Range of PVT Conditions |
| Author | *Shu Hokimoto, Tohru Ishihara, Hidetoshi Onodera (Kyoto University, Japan) |
| Page | pp. 323 - 328 |
| Keyword | Minimum Energy Point Tracking, Dynamic Voltage and Frequency Scaling, Adaptive Body Basing |
| Abstract | Scaling the supply voltage (VDD) and threshold voltage (VTH) for minimizing the energy consumption of processors dynamically is highly desired for applications such as wireless sensor network and Internet of Things (IoT). In this paper, we refer to the pair of VDD and VTH , which minimizes the energy consumption of the processor under a given operating condition, as a minimum energy point (MEP in short). Since the MEP is heavily dependent on PVT (Process, Voltage and Temperature) conditions, it is not very easy to closely track the MEP at runtime. The voltage condition in this work is assumed to arise due to dynamic voltage and frequency scaling (DVFS) along with a change of the performance requirement. This paper proposes a simple but effective algorithm for dynamically tracking the MEP of a processor under a wide range of PVT conditions. Gate-level simulation for a 32-bit RISC processor designed with a 65nm process demonstrates that the proposed algorithm tracks the MEP under a situation that PVT conditions widely vary. |
| Title | Comparison of Area-Delay-Energy Characteristics between General Purpose Processors and Dedicated Hardwares for Embedded Applications |
| Author | *Kei Yoshizawa, Tohru Ishihara, Hidetoshi Onodera (Kyoto University, Japan) |
| Page | pp. 329 - 334 |
| Keyword | Dedicated hardware, General Purpose Processor, Comparison, Energy-efficiency |
| Abstract | We examine the performance difference between dedicated hardwares and a general purpose processor with respect to energy efficiency, area, and delay, using three applications. We show that the main difference comes from the number of cycles required for each application. In ADPCM, a dedicated hardware is 2,266 times energy-efficient and 2,302 times faster than a general purpose processor with a similar amount of area. However in DCT, which contains less branch codes, the advantage of a dedicated hardware in the energy efficiency and processing speed decreases to 127 times and 1,263 times, respectively. We also observed in ADPCM that the advantage of the dedicated hardware over the general purpose processor in energy efficiency and speed is reduced to 425 times and 431 times respectively if the processor is equipped with a multiplier. It is observed that the performance advantage of dedicated hardwares varies very much depends on applications and the hardware resources of a general purpose processor. Lastly, we analyze the processing cycles of the general purpose processor and it is revealed that a considerable amount of processing cycles are consumed by stalls and multiplications. For example in ADPCM, 39.7% of the processing cycles are lost by stalls and 43.4% by multiplications while the rest of 16.9% are consumed by sequential operations of the ADPCM algorithm that could be done in parallel in a dedicated hardware. |
| Title | Finding Effective Simulation Patterns for Coverage-Driven Verification Using Deep Learning |
| Author | *Mami Miyamoto, Kiyoharu Hamaguchi (Shimane University, Japan) |
| Page | pp. 335 - 340 |
| Keyword | RTL verification, Deep Learning, coverage-driven verification, automated testbench |
| Abstract | In Coverage-driven verification of RT/gate-level designs, one of important tasks is to cover each cover point with fairly a large number of new simulation patterns. We propose a method to learn features of simulation patterns by deep learning, and to find simulation patterns covering a hard-to-cover point based on reconstruction errors. The experimental results show that the proposed method is efficient in finding effective simulation patterns. |
| Title | Static Timing Analysis of Rapid Single-Flux-Quantum Circuits |
| Author | *Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi (Kyoto University, Japan) |
| Page | pp. 341 - 345 |
| Keyword | RSFQ, static timing analysis |
| Abstract | We propose a method for calculating pulse arrival timing at all gates in an RSFQ circuit and a new de nition of timing slacks of gates. In the pro- posed method, the total path delay, the total length of PTLs and the number of PTL transmitters/receivers on a path are also calculated. |
| Title | Improved Method of Simulated Annealing for Unreachable Solution Space |
| Author | *Hiroyuki Nakano, Kunihiro Fujiyoshi (Tokyo University of Agriculture and Technology, Japan) |
| Page | pp. 346 - 351 |
| Keyword | Simulated Annealing, Making Adjacent Solutions, Solution Space, Reachability |
| Abstract | Simulated Annealing is a universal probabilistic metaheuristic for optimization problems of locating a good approximation to the global minimum of given function in a large solution space. It is sometimes used for physical design problems. However, Simulated Annealing is known to be inefficient when it searches solution spaces containing infeasible solutions. In this paper, we propose two methods to make adjacent solutions for such solution spaces. Experimental comparisons indicate the effectiveness of the proposed methods. |
| Title | Application of Monte-Carlo Tree Search to Traveling-Salesman Problem |
| Author | Masato Shimomura, *Yasuhiro Takashima (University of Kitakyushu, Japan) |
| Page | pp. 352 - 356 |
| Keyword | Monte-Carlo Tree Search, Traveling-Salesman Problem, Optimization |
| Abstract | This paper shows an application of Monte-Carlo Tree Search (MCT) to Traveling-Salesman Problem (TSP). Compared with the simulated annealing, which is one of the general probabilistic optimization methods, MCT has very high ability of optimization with problem-aware implementation. Its efficiency is confirmed, empirically. |
| Title | Analog Characterization Module with D/A Converter Configuration |
| Author | *Daishi Isogai, Bo Liu, Futa Yoshinaka, Shigetoshi Nakatake (The University of Kitakyushu, Japan) |
| Page | pp. 357 - 361 |
| Keyword | FPAA, DAC, Opamp |
| Abstract | This work proposes an analog characterization module to imitate (emulate) various analog components as essential technologies for analog-specific computation. This module converts an analog input signal into digital by an ADC circuit, makes use of digital signal processing technologies to characterize the signal as expected, and outputs the analog signal converting by a DAC. In this paper, characterizing the proposing module as a resistance, we demonstrate a use case of realizing a programmable gain amplifier by introducing the module. |
| Title | Range Limiter using Connection Bounding Box for SA-based Placement of Mixed-Grained Reconfigurable Architecture |
| Author | *Takashi Kishimoto (Ritsumeikan University, Japan), Wataru Takahashi, Kazutoshi Wakabayashi (NEC Corporation, Japan), Hiroyuki Ochi (Ritsumeikan University, Japan) |
| Page | pp. 362 - 367 |
| Keyword | Simulated annealing |
| Abstract | In this paper, we propose a novel placement algorithm for mixed-grained reconfigurable architectures (MGRAs). MGRA consists of coarse-grained and fine-grained clusters, in order to implement a combined digital systems of high-speed data paths with multi-bit operands and random logic circuits for state machines and bit-wise operations. For accelerating simulated annealing based FPGA placement algorithm, range limiter has been proposed to control the distance of two blocks to be interchanged. However, it is not applicable to MGRAs due to the heterogeneous structure of MGRAs. Proposed range limiter using connection bounding box effectively keeps the size of range limiter to encourage moves across fine-grain blocks in non-adjacent clusters. From experimental results, the proposed method achieved 47.8% reduction of cost in the best case compared with conventional methods. |
| Title | A Smart Hybrid Memetic Algorithm for Thermal-Aware Non-Slicing Floorplanning |
| Author | *Jianli Chen, Yan Liu, Ziran Zhu, Wenxing Zhu (Fuzhou University, China) |
| Page | pp. 368 - 373 |
| Keyword | Floorplanning, memetic |
| Abstract | Floorplanning is a crucial design step in ASIC design flow. It provides valuable insights into the hardware decisions and estimates a floorplan with different cost metrics. In this paper, in order to handle a multi-objective non-slicing floorplanning problem efficiently, a smart hybrid memetic algorithm is presented to optimize the area, the total wirelength, and the maximum temperature and the average temperature of a chip. In the proposed method, an effective genetic algorithm is used to explore the search space, and an efficient modified hybrid simulated annealing algorithm is used to exploit information in the search region. The exploration and exploitation are balanced by a death probability strategy. In this strategy, according to the natural mechanisms, each individual in the population is endowed with an actual age and a dynamic survival age. Experimental results on the standard tested benchmarks show that the proposed algorithm is efficient to obtain floorplans, with decreasing the average and the peak temperature. |
| Title | Hardware Acceleration of Rate-Distortion Optimized Quantization Algorithm |
| Author | *Yusuke Funayama, Takashi Kambe (Kindai University, Japan), Gen Fujita (Osaka Electro-Communication University, Japan) |
| Page | pp. 374 - 375 |
| Keyword | Rate-distortion optimized quantization, Hardware Acceleration, video coding, high-level synthesis |
| Abstract | Rate-distortion optimized quantization (RDOQ) is an important technology for improving video coding performance. RDOQ is able to determine the optimal value among multiple quantization candidates based on rate-distortion (RD). We propose a hardware acceleration method to the algorithm to reduce its complexity by changing the bit-rate estimation method and by excluding low scored quantization candidates. The hardware design results are also evaluated. |
| Title | Development of an Optimal Wireless Power Transfer System for Lithium-Ion Battery Charge |
| Author | *Yuto Honda, Lei Lin, Masahiro Fukui (Ritsumeikan University, Japan) |
| Page | pp. 376 - 381 |
| Keyword | Wireless power transmission, charging, Lithium-ion battery |
| Abstract | We describe the development of the optimal wireless power transfer system for the Lithium-Ion battery charge. The proposed system has the DC-DC converter on both of the primary side and the secondary side. This system improves the transmission efficiency when the duty ration of the DC-DC converter on the primary side. This is because the value of the pretense load is optimum value. In addition, the DC-DC converter on the secondary side optimizes the charging current and voltage according to the state of the battery. Thus, this system can establish both of the improvement of transmission efficiency and optimum charging for the lithium-ion battery. |
| Title | Design of a Fast Lock-in and Low-Power All-Digital Frequency Synthesizer with a Wide Tuning Range |
| Author | *Hao-Chiao Hong, Hung-Yi Wen (National Chiao Tung University, Taiwan), Hong-Yi Huang (National Taipei University, Taiwan) |
| Page | pp. 382 - 385 |
| Keyword | ADFLL, Frequency synthesizer, DCO |
| Abstract | This paper presents the design of a low-power and fast-locking all-digital frequency lock loop (ADFLL) with a wide tuning range. The ADFLL adopts the Regula Falsi method to conduct the frequency acquisition to achieve a short lock-in time. The digitally control oscillator (DCO) comprises of an R-2R DAC driving a voltage-controlled ring oscillator to save the power consumption and to achieve a linear transfer function to facilitate the short lock-in time requirement of the Regula Falsi method. A test chip has been fabricated in 90-nm CMOS. Measurement results show that the output frequency of the ADFLL ranges from 1.20 GHz to 6.95 GHz. At an output frequency of 5.00 GHz, the frequency acquisition process takes only five reference clock cycles. Meanwhile, the measured rms and pk-pk jitters are 1.5 ps and 15 ps, respectively. The proposed ADFLL achieves a power efficiency of 1.88 mW/GHz at 5.00 GHz and 1 V. |
| Title | A Method for Recognizing a Breaking Sound of a Window Glass for Realizing a Low-power Security Surveillance System Using FPGA |
| Author | *Ryo Terafuji, Hiroyuki Ochi (Ritsumeikan University, Japan) |
| Page | pp. 386 - 390 |
| Keyword | sound recognition, wavelet transform, support vector machine, low power design, FPGA implementation |
| Abstract | This paper proposes a sound recognition method specialized to a breaking sound of a window glass to realize a security surveillance system that operates for a long time with battery. Our method analyzes the input sound using wavelet transform, and recognizes the sound using linear SVM. From simulation experiments, 90 % recognition ratio is achieved. We also propose an FPGA implementation of wavelet transform which enables us real-time processing at 3.3 MHz clock frequency using 6k-words ROM and 17 multipliers. |
| Title | Electromagnetic Analysis for a Lightweight Block Cipher Simon |
| Author | *Yusuke Nozaki, Yoshiya Ikezaki, Masaya Yoshikawa (Meijo University, Japan) |
| Page | pp. 391 - 396 |
| Keyword | Security, Electromagnetic analysis, Lightweight block cipher, Simon, Tamper resistance |
| Abstract | Lightweight block ciphers, which are suitable for IoT devices, have attracted attention. Regarding the security of cryptographic circuit, the risk of electromagnetic analysis is pointed out. However, electromagnetic analysis of lightweight block ciphers has barely been studied. Therefore, this study proposes a new dedicated electromagnetic analysis for Simon which is one of the most popular lightweight block ciphers. Experiments using a FPGA prove the validity of the proposed method and the vulnerability of Simon against electromagnetic analysis. |
| Title | Qualitative-Modeling-Based Design for Silicon Neuronal Networks |
| Author | *Takashi Kohno (The University of Tokyo, Japan) |
| Page | p. 397 |
| Abstract | Silicon neuronal network is a bottom-up approach to the neuro-mimetic systems, which are gaining prominence as a new approach to realize power-efficient, adaptive, and intelligent information processing systems with massively parallel architecture. It is a network of silicon neuron circuits which emulate the electrophysiological activities in neuronal cells in real time. A variety of neuronal cells with complex activities is observed in the nervous system. A class of neuron models that describes the dynamics of ionic particles near the cell membrane can precisely model these activities, but it is described by multivariable nonlinear differential equations. To realize power-efficient and simple silicon neuron circuits that reproduce the nonlinearity in these equations, we developed a new circuit design approach on the basis of nonlinear mathematical techniques that have been utilized in the qualitative neuronal modeling. This approach can also be applied to tune the dynamical properties of the neuronal activities after circuit fabrication and support a variety of neuronal activities. |