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The 21st Asia and South Pacific Design Automation Conference

Session 3S  (Special Session) High-Level Synthesis – Now, the Future, and the "Dark Secrets"
Time: 15:50 - 17:30 Tuesday, January 26, 2016
Location: TF4303
Organizer: Deming Chen (UIUC, U.S.A.), Chair: Eric Yun Liang (Peking Univ., China)

3S-1 (Time: 15:50 - 16:15)
Title(Invited Paper) Design and Verification Using High-Level Synthesis
Author*Andres Takach (Mentor Graphics, U.S.A.)
Pagepp. 198 - 203
Detailed information (abstract, keywords, etc)

3S-2 (Time: 16:15 - 16:40)
Title(Invited Paper) High-Level Synthesis of Accelerators in Embedded Scalable Platforms
AuthorPaolo Mantovani, Giuseppe Di Guglielmo, *Luca P. Carloni (Columbia Univ., U.S.A.)
Pagepp. 204 - 211
Detailed information (abstract, keywords, etc)

3S-3 (Time: 16:40 - 17:05)
Title(Invited Paper) High Quality IP Design using High-Level Synthesis Design Flow
Author*Qiang Zhu (Cadence Design Systems, Japan), Masato Tatsuoka (Socionext, Japan)
Pagepp. 212 - 217
Detailed information (abstract, keywords, etc)

3S-4 (Time: 17:05 - 17:30)
Title(Invited Paper) Designing High-Quality Hardware on a Development Effort Budget: A Study of the Current State of High-Level Synthesis
AuthorZelei Sun, Keith Campbell, Wei Zuo (UIUC, U.S.A.), Kyle Rupnow, Swathi Gurumani (ADSC, Singapore), Frederic Doucet (Qualcomm, U.S.A.), *Deming Chen (UIUC, U.S.A.)
Pagepp. 218 - 225
Detailed information (abstract, keywords, etc)