| Title | (Invited Paper) High-Level Synthesis of Accelerators in Embedded Scalable Platforms |
| Author | Paolo Mantovani, Giuseppe Di Guglielmo, *Luca P. Carloni (Columbia University, U.S.A.) |
| Page | pp. 204 - 211 |
| Keyword | SoC, system-level design, high-level synthesis, accelerators, embedded scalable plaftorms |
| Abstract | Embedded scalable platforms combine a flexible socketed architecture for heterogeneous system-on-chip (SoC) design and a companion system-level design methodology. The architecture supports the rapid integration of processor cores with many specialized hardware accelerators. The methodology simplifies the design, integration, and programming of the heterogeneous components in the SoC. In particular, it raises the level of abstraction in the design process and guides designers in the application of high-level synthesis (HLS) tools. HLS enables a more efficient design of accelerators with a focus on their algorithmic properties, a broader exploration of their design space, and a more productive reuse across many different SoC projects. |
| Title | (Invited Paper) High Quality IP Design using High-Level Synthesis Design Flow |
| Author | *Qiang Zhu (Cadence Design Systems, Japan), Masato Tatsuoka (Socionext Inc., Japan) |
| Page | pp. 212 - 217 |
| Keyword | High Level Synthesis, IP designs, Physically Aware |
| Abstract | In this paper we will describe practical experiences about the use of high-level synthesis technologies to achieve higher performance, higher quality, and lower power for IP designs as compared to traditional RTL design. We will demonstrate how the introduction of three key techniques, interface-based design, architectural exploration and congestion-aware high-level synthesis, were utilized to achieve higher quality IP designs. In real application results, we will show significantly better QoR (Quality-of-Results) using high-level synthesis than the traditional RTL design flow by utilizing the above three key technologies. |
| Title | (Invited Paper) Designing High-Quality Hardware on a Development Effort Budget: A Study of the Current State of High-Level Synthesis |
| Author | Zelei Sun, Keith Campbell, Wei Zuo (UIUC, U.S.A.), Kyle Rupnow, Swathi Gurumani (ADSC, Singapore), Frederic Doucet (Qualcomm, U.S.A.), *Deming Chen (UIUC, U.S.A.) |
| Page | pp. 218 - 225 |
| Keyword | High-level synthesis, evaluation, coding guidances, optimization, hardware design |
| Abstract | High-level synthesis (HLS) promises high-quality hardware with minimal development effort. In this paper, we evaluate the current state-of-the-art in HLS and design techniques based on software references and architecture references. We present a software reference study developing a JPEG encoder from pre-existing software, and an architecture reference study developing an AES block encryption module from scratch in SystemC and SystemVerilog based on a desired architecture. Additionally, we develop micro-benchmarks to demonstrate best-practices in C coding styles that produce high-quality hardware with minimal development effort. Finally, we suggest language, tool, and methodology improvements to improve upon the current state-of-the-art in HLS. |