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The 21st Asia and South Pacific Design Automation Conference

Session 3B  Low Power in Deep Sub-Micro: From Architecture to Physical Design
Time: 15:50 - 17:30 Tuesday, January 26, 2016
Location: TF4304
Chairs: Takashi Sato (Kyoto Univ., Japan), Pingqiang Zhou (ShanghaiTech Univ., China)

3B-1 (Time: 15:50 - 16:15)
TitleA Novel Low-Cost Dynamic Logic Reconfigurable Structure Strategy for Low Power Optimization
Author*Yu-Guang Chen, Wan-Yu Wen, Yun-Ting Wang, You-Luen Lee, Shih-Chieh Chang (National Tsing Hua Univ., Taiwan)
Pagepp. 250 - 255
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3B-2 (Time: 16:15 - 16:40)
TitleAn Energy-Efficient Random Number Generator for Stochastic Circuits
Author*Kyounghoon Kim (Seoul National Univ., Republic of Korea), Jongeun Lee (UNIST, Republic of Korea), Kiyoung Choi (Seoul National Univ., Republic of Korea)
Pagepp. 256 - 261
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3B-3 (Time: 16:40 - 17:05)
TitleDesign of an All-Digital Temperature Sensor in 28 nm CMOS Using Temperature-Sensitive Delay Cells and Adaptive-1P Calibration for Error Reduction
AuthorShang-Yi Li, *Pei-Yuan Chou, Jinn-Shyan Wang (Chung-Cheng Univ., Taiwan)
Pagepp. 262 - 267
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3B-4 (Time: 17:05 - 17:30)
TitleDesign and Allocation of Loosely Coupled Multi-bit Flip-flops for Power Reduction in Post-Placement Optimization
Author*Hyoungseok Moon, Taewhan Kim (Seoul National Univ., Republic of Korea)
Pagepp. 268 - 273
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