| Title | A Novel Low-Cost Dynamic Logic Reconfigurable Structure Strategy for Low Power Optimization |
| Author | *Yu-Guang Chen, Wan-Yu Wen, Yun-Ting Wang, You-Luen Lee, Shih-Chieh Chang (National Tsing Hua University, Taiwan) |
| Page | pp. 250 - 255 |
| Keyword | DVFS, Low Power Design, Dynamic Logic Reconfigurable Structure |
| Abstract | Low power design techniques have been extensively applied in modern IC designs to avoid negative side effects from high power density. Unlike Dynamic Voltage and/or Frequency Scaling (DVFS) approaches only applied on a “fixed” design, we propose a dynamic logic reconfigurable structure strategy which allows dynamic switching from a high speed/power logic structure to a low speed/power logic structure. A design with such configurable structure is called Dynamic Logic Reconfigurable Structure (DLRS). Different from approximate computing which trades off between computation accuracy and power, our DLRS designs maintain data integrity. In this paper, we propose novel low-cost DLRS adders and multipliers, and a comprehensive framework for low power designs. We further integrate DLRS with DVFS, which creates more flexibility to trade-off between performance and power consumption. Experimental results show that with DLRS adders and multipliers in three indoor designs, the proposed method can achieve up to 60.05% power reduction compared with traditional DVFS scheme with only 6.55% area overhead. |
| Title | An Energy-Efficient Random Number Generator for Stochastic Circuits |
| Author | *Kyounghoon Kim (Seoul National University, Republic of Korea), Jongeun Lee (UNIST, Republic of Korea), Kiyoung Choi (Seoul National University, Republic of Korea) |
| Page | pp. 256 - 261 |
| Keyword | Stochastic computing, stochastic number generator, energy-efficient design, approximate computing |
| Abstract | Stochastic circuits provide very high efficiency in terms of gate area and power consumption compared with conventional binary logic. However, they require random bit streams generated by stochastic number generators (SNGs), which account for a significant portion of area and energy offsetting their merits. In this paper, we propose a new SNG that significantly reduces area and energy while improving accuracy in progressive precision. Experimental results show that the proposed SNG reduces energy by more than 72% compared to the state-of-the-art designs. |
| Title | Design of an All-Digital Temperature Sensor in 28 nm CMOS Using Temperature-Sensitive Delay Cells and Adaptive-1P Calibration for Error Reduction |
| Author | Shang-Yi Li, *Pei-Yuan Chou, Jinn-Shyan Wang (Chung-Cheng University, Taiwan) |
| Page | pp. 262 - 267 |
| Keyword | temperature sensor, all digital, calibration, zero temperature coefficient, process variation |
| Abstract | We describe design techniques, calibration method, and measurement results of an all-digital temperature sensor in 28 nm CMOS. To deal with the issue of Vcc being near the zero-temperature-coefficient point, a new delay cell with much improved temperature sensitivity is proposed. Adaptive 1-point (1P) calibration is proposed to reduce the serious impact due to process variations, while without increasing the calibration cost. Measurement results show that, compared to the conventional 1P calibration, the new method achieves a 32% error reduction. |
| Title | Design and Allocation of Loosely Coupled Multi-bit Flip-flops for Power Reduction in Post-Placement Optimization |
| Author | *Hyoungseok Moon, Taewhan Kim (Seoul National University, Republic of Korea) |
| Page | pp. 268 - 273 |
| Keyword | Flip-flop allocation, clock power, Post-placement |
| Abstract | Recently, allocating multi-bit flip-flops (MBFFs) as opposed to 1-bit flip-flops has been recognized as one of effective design optimization techniques to reduce clock power. This work tries to eliminate timing and area constraints so that a full benefit of multi-bit flip-flops can be reaped. Precisely, rather than using the conventional structure of multi-bit flip-flops, we introduce a new style of multi-bit flip-flop, called loosely coupled multi-bit flip-flop (LC-MBFF). Utilizing LC-MBFFs, we propose a routability and clock-tree driven multi-bit flip-flop allocation algorithm, which fully explores the diverse allocation of LC-MBFF structures to maximally reduce clock power consumption. |