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SASIMI 2025
The 26th Workshop on Synthesis And System Integration of Mixed Information Technologies
Technical Program

Remark: The presenter of each paper is marked with "*".
Technical Program:   SIMPLE version   DETAILED version with abstract
Author Index:   HERE

Session Schedule

Thursday, October 9, 2025

Registration
8:30 -
Op  Opening
9:00 - 9:20
K1  Keynote Speech I
9:20 - 10:30
R1  Regular Poster Session I
10:30 - 12:00
Lunch Break
12:00 - 13:30
I1  Invited Talk I
13:30 - 14:30
R2  Regular Poster Session II
14:30 - 16:00
D  Panel Discussion
16:00 - 17:30
Banquet
18:00 - 20:00
Friday, October 10, 2025

K2  Keynote Speech II
9:20 - 10:30
R3  Regular Poster Session III
10:30 - 12:00
Lunch Break
12:00 - 13:30
I2  Invited Talk II
13:30 - 14:30
R4  Regular Poster Session IV
14:30 - 16:00
Cl  Closing
16:00 -


List of papers

Remark: The presenter of each paper is marked with "*".

Thursday, October 9, 2025

[To Session Table]

Keynote Speech I
Time: 9:20 - 10:30, Thursday, October 9, 2025

K1-1 (Time: 9:20 - 10:30)
Title(Keynote Speech) Verification Tools Should Certify Their Results
AuthorRandal. E. Bryant (Carnegie Mellon Univ., USA)
Detailed information


[To Session Table]

Regular Poster Session I
Time: 10:30 - 12:00, Thursday, October 9, 2025

R1-1
TitleModeling of Dynamic Input Capacitance in Trench-Gate SiC MOSFETs via Voltage-Dependent Gate Oxide Capacitance Partitioning
Author*Taiki Nishioka, Kazuki Matsumoto, Hajime Takayama (Kyoto Inst. of Tech., Japan), Jun Furuta (Okayama Prefectural Univ., Japan), Kazutoshi Kobayashi, Michihiro Shintani (Kyoto Inst. of Tech., Japan)
Detailed information (abstract, keywords, etc)

R1-2
TitleA Detailed Analysis of LLM Execution on IMAX3 and Initial Evaluation of IMAX4 Prototype for Server Environment
Author*Takuto ANDO, Yu ETO, Yasuhiko NAKASHIMA (NAIST, Japan)
Detailed information (abstract, keywords, etc)

R1-3
TitleGStreamer-integrated HLS-based JPEG Encoder for Edge FPGA SoCs
Author*Yuri Guimaraes Pereira Primo da Silva, Shinya Honda (Nagoya Univ., Japan), Sugako Ootani (Renesas, Japan), Masato Edahiro (Nagoya Univ., Japan), Abraham Monrroy Cano (MapIV, Japan)
Detailed information (abstract, keywords, etc)

R1-4
TitleAutoPre-ACM:Autoencoder Based Precision-Enhanced Anomaly Detection For Cyber-Physical Attacks in MEDA Biochips
Author*Purrnima Singh, Yash Gupta (Netaji Subhas Univ. of Tech., New Delhi, India), Syed Rameem Zahra (Sher-e-Kashmir Univ. of Agricultural Sciences and Technology, Kashmir, J&K, India), Ankur Gupta (Netaji Subhas Univ. of Tech., New Delhi, India), Shigeru Yamashita (Ritsumeikan Univ., 1-1-1 Noji Higashi, Kusatsu, Shiga 525-8577, JAPAN., Japan)
Detailed information (abstract, keywords, etc)

R1-5
TitleBinary Synthesis from ARM Machine Code Using a General-Purpose High-Level Synthesis System
Author*Yuga Sugimoto, Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Detailed information (abstract, keywords, etc)

R1-6
TitleQuantification of Design Difficulty of Analog Circuits Based on Volume of Effectual Design Space
AuthorRiku Anan, *Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (Univ. of Shiga Prefecture, Japan)
Detailed information (abstract, keywords, etc)

R1-7
TitleFlow-based Augmented Droplet Routing Algorithm for MEDA-Based DMFB
Author*Emuun Purevdagva, Masayuki Shimoda, Satoshi Tayu, Atsushi Takahashi (Institute of Science Tokyo, Japan)
Detailed information (abstract, keywords, etc)

R1-8
TitleEnhancing Hardware Trojan Detection via ATPG-Based Transition Delay Fault Testing with Split Fault Lists
Author*Asuka Koike, Yutaka Masuda, Tohru Ishihara (Nagoya Univ., Japan)
Detailed information (abstract, keywords, etc)

R1-9
TitleVoltage and Frequency Dependence of Single Event Transient Induced by Alpha-Particle
Author*Arata Matsumoto, Haruto Sugisaki, Ryuichi Nakajima (Kyoto Inst. of Tech., Japan), Jun Furuta (Okayama Prefectural Univ., Japan), Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan)
Detailed information (abstract, keywords, etc)

R1-10
TitleEvaluating Signal Integrity in InFO Package via Learning-based Methods
Author*Yi-Hua Yeh, Haoru Chang, Hung-Ming Chen, Chien-Nan Liu (NYCU, Taiwan)
Detailed information (abstract, keywords, etc)

R1-11
TitleA High Precision Heuristic for Motif Extraction Using Random Forests
AuthorJigen Murata, Masato Inagi, Martin Lukac, Shin'ichi Wakabayashi, *Shinobu Nagayama (Hiroshima City Univ., Japan)
Detailed information (abstract, keywords, etc)

R1-12
TitleSizing Transformation Technique for Analog Design Migration Across Different Technologies
AuthorYao-Cheng Wu, King-Ho Wong, *Chien-Nan Jimmy Liu (National Yang Ming Chiao Tung Univ., Taiwan), Chia-Tseng Chiang (Richtek Technology, Taiwan)
Detailed information (abstract, keywords, etc)

R1-13
TitleEqualizing QAM Waveform Distortion with Linear SVM Classifier and its Machine Learning Dataset Generation
Author*Yiwei Liu, Yukina Haruta, Yutaka Masuda, Tohru Ishihara (Nagoya Univ., Japan)
Detailed information (abstract, keywords, etc)

R1-14
TitleA Hardware Design Environment for ROS2 Node to FPGA-Integrated SoC
AuthorXingze Li (Nagoya Univ., Japan), *Ryota Yamamoto (National Inst. of Tech., Tomakomai College, Japan), Shinya Honda (Nagoya Univ., Japan)
Detailed information (abstract, keywords, etc)


[To Session Table]

Invited Talk I
Time: 13:30 - 14:30, Thursday, October 9, 2025

I1-1
Title(Invited Talk) Towards Emerging Device Computing for the Post-Moore Era
AuthorKoji Inoue (Kyushu Univ., Japan)
Detailed information


[To Session Table]

Regular Poster Session II
Time: 14:30 - 16:00, Thursday, October 9, 2025

R2-1
TitleOptimal Golomb Coding via Dynamic Programming and Its Application on Large Language Model Compression
AuthorJen-Hung Yang, Zhi-Kai Xu, *Juinn-Dar Huang (National Yang Ming Chiao Tung Univ., Taiwan)
Detailed information (abstract, keywords, etc)

R2-2
TitleOn Ratio of Embedded RECON Spare Cell Types for Technology Remapping
AuthorYasuaki Nabetani, Nobutaka Kuroki, *Masahiro Numa (Kobe Univ., Japan)
Detailed information (abstract, keywords, etc)

R2-3
TitleA Seamless Hardware/Software Switching Technique for Embedded Systems Using HDLRuby
Author*Lovic Gauthier, Sachi Yoshigai (National Inst. of Tech., Ariake College, Japan)
Detailed information (abstract, keywords, etc)

R2-4
TitleSpeeding Up a Routing Method Considering Droplet Splitting on MEDABiochips by Dijkstra’s Method
Author*Issei Nakamura, Shigeru Yamashita, Hiroyuki Tomiyama (Ritsumeikan Univ., Japan), Ankur Guputa (Netaji Subhas Univ. of Tech., India)
Detailed information (abstract, keywords, etc)

R2-5
TitleEMESN: an Extended MOSFET Reservoir Computing Architecture for Echo State Networks with Hardware-Software Co-Optimization
Author*Haoyuan Li (Kyoto Univ., China), Masami Utsunomiya, Ryuto Seki, Takashi Sato (Kyoto Univ., Japan), Feng Liang (Xi'an Jiaotong Univ., China)
Detailed information (abstract, keywords, etc)

R2-6
TitleDevelopment of Tsugaru Dialect Translation System Using Transparent Display
Author*Haruto Saito, Masashi Imai (Hirosaki Univ., Japan)
Detailed information (abstract, keywords, etc)

R2-7
TitleAccelerated Behavioral Simulation for Optimizing MOSFET-Based Echo State Networks
Author*Ryuto Seki, Masami Utsunomiya (Kyoto Univ., Japan), Haoyuan Li (Xi'an Jiaotong Univ., China), Hiromitsu Awano, Takashi Sato (Kyoto Univ., Japan)
Detailed information (abstract, keywords, etc)

R2-8
TitleA Design Method for Single-Rail LUT Cascades
Author*Tsutomu Sasao (Meiji Univ., Japan)
Detailed information (abstract, keywords, etc)

R2-9
TitleImplementation of Interrupt Handlers in Full Hardware Implementation of RTOS-Based Systems
Author*Yuki Nakatani, Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Hiroyuki Tomiyama, Hiroyuki Kanbara (Ritsumeikan Univ., Japan)
Detailed information (abstract, keywords, etc)

R2-10
TitleAn Error Diagnosis Technique Applicable to Single Line Errors Based on Location Variable Simulation
Author*Kazuki Sakamoto, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Detailed information (abstract, keywords, etc)

R2-11
TitleMulti-Objective Optimization of RESURF Structure in SiC MOSFET for I-V and C-V characteritics
Author*Sota Oyama (Hirosaki Univ., Japan), Ichirota Takazawa (Jedat, Japan), Satoru Honda, Toshiki Kanamoto (Hirosaki Univ., Japan)
Detailed information (abstract, keywords, etc)

R2-12
TitleA Systematic Hardware Solution for GDPR Compliance
AuthorYi-Chun Yang, *Ren-Song Tsay (National Tsing-Hua Univ., Taiwan)
Detailed information (abstract, keywords, etc)

R2-13
TitleReducing Registers in Convolution Operation for Binarized Neural Networks with Register-Bridge LSI Architecture
Author*Jun Masuda, Kazuhito Ito (Saitama Univ., Japan)
Detailed information (abstract, keywords, etc)

R2-14
TitleExtending the Single-Target Droplet Generation Method CoDOS to Multi-Target Synthesis
AuthorYusuke Igarashi, *Shigeru Yamashita (Ritsumeikan Univ., Japan)
Detailed information (abstract, keywords, etc)



Friday, October 10, 2025

[To Session Table]

Keynote Speech II
Time: 9:20 - 10:30, Friday, October 10, 2025

K2-1 (Time: 9:20 - 10:30)
Title(Keynote Speech) New Optical Path Design Trend on the IOWN Global Forum Open All-Photonics Network: Background, Application, and Key Enablers
AuthorHideki Nishizawa (NTT, Japan)
Detailed information


[To Session Table]

Regular Poster Session III
Time: 10:30 - 12:00, Friday, October 10, 2025

R3-1
TitleCross-Design Power Trace Prediction using Graph Neural Network
AuthorShih-Chun Lin, *Bo-Hao Haung, Yung-Chih Chen (National Taiwan Univ. of Science and Tech., Taiwan), Wang-Dauh Tseng (Yuan Ze Univ., Taiwan)
Detailed information (abstract, keywords, etc)

R3-2
TitleILP-Based Movable Layout Replacer for Standard Cells with Extending Metal Boundaries
AuthorYa-Chu Yang, Shih-Sian Tang, *Chen-Chen Yeh, Shao-Chien Lu, Hui-Lin Cho, Yu-Cheng Lin, Rung-Bin Lin (Department of Computer Science and Engineering, Yuan Ze Univ., Taoyuan, Taiwan)
Detailed information (abstract, keywords, etc)

R3-3
TitleCompact QUBO Formulation of Resource-Constrained Operation Scheduling in High-Level LSI Design
Author*Haruki Yamagishi, Takuto Kishimoto, Kazuhito Ito (Saitama Univ., Japan)
Detailed information (abstract, keywords, etc)

R3-4
TitleEfficitent FPGA Implementation of Multiple-Input Adders Using Generalized Parallel Counter (6,0,7;5)
Author*Mugi Noda, Ryo Kanai, Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Detailed information (abstract, keywords, etc)

R3-5
TitleGenetic Algorithm-based Layer-wise Adaptive Filter Pruning
AuthorTing-Yi Liu, Yi-Ting Li, Wuqian Tang (National Tsing Hua Univ., Taiwan), *Yung-Chih Chen (National Taiwan Univ. of Science and Tech., Taiwan), Shih-Chieh Chang, Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Detailed information (abstract, keywords, etc)

R3-6
TitleEvaluation of Free-form Conversation Learning Effects in a Tsugaru Dialect Speech Recognition Model
Author*Akihiro Murakami, Masashi Imai (Hirosaki Univ., Japan)
Detailed information (abstract, keywords, etc)

R3-7
TitleHigh-Speed SIFT Descriptor Generation with 36 Small-Region Division and Logic-Synthesis Evaluation
Author*Ayumu Mitsumoto, Tetsuo Hironaka (Hiroshima City Univ., Japan)
Detailed information (abstract, keywords, etc)

R3-8
TitleNumberlink Problem Variants Modeled after FPGA Routing Fabrics and their Solvers that Enumerate all the Solutions
Author*Ryohei Komi, Hiroyuki Ochi (Ritsumeikan Univ., Japan)
Detailed information (abstract, keywords, etc)

R3-9
TitleImplementation and Evaluation of a Speculative Execution-Based FPGA Accelerator for Electronic Circuit Simulation Using Gauss-Jordan and BiCGSTAB Methods
Author*Yuma Omoto, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univercity, Japan)
Detailed information (abstract, keywords, etc)

R3-10
TitleEfficient and Accurate SC Arithmetic Circuits Using Bit Manipulation Based on Interval Partitioning of Bit Strings
Author*Yota Yanagida, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Detailed information (abstract, keywords, etc)

R3-11
TitleLogic Gate Design Using Vertical Nanowire Transistors
Author*Genta Nakamura (Kyushu Univ., Japan), Katsuhiro Tomioka (Hokkaido Univ., Japan), Koji Inoue (Kyushu Univ., Japan)
Detailed information (abstract, keywords, etc)

R3-12
TitleSubitizing-Inspired Large Language Models for Floorplanning
AuthorChen-Chen Yeh, *Shao-Chien Lu, Hui-Lin Cho, Yu-Cheng Lin, Rung-Bin Lin (Department of Computer Science and Engineering, Yuan Ze Univ., Taoyuan, Taiwan)
Detailed information (abstract, keywords, etc)

R3-13
TitleReinforcement Learning-Based Loop Optimization Using the Polyhedral Model
Author*Hayato Takahashi, Motoki Amagasaki, Masato Kiyama, Kenshu Seto, Mery Diana (Kumamoto Univ., Japan)
Detailed information (abstract, keywords, etc)

R3-14
TitleEvaluation of FPGA Development Boards in a Cryogenic Environment
Author*Tomoki Takashima, Masashi Imai (Hirosaki Univ., Japan)
Detailed information (abstract, keywords, etc)


[To Session Table]

Invited Talk II
Time: 13:30 - 14:30, Friday, October 10, 2025

I2-1 (Time: 13:30 - 14:30)
Title(Invited Talk) A Symbolic Approach to Exact Quantum Circuit Simulation and Verification
AuthorJie-Hong Roland Jiang (National Taiwan Univ., Taiwan)
Detailed information


[To Session Table]

Regular Poster Session IV
Time: 14:30 - 16:00, Friday, October 10, 2025

R4-1
TitleCombatting Transient Errors and Aging in Heterogeneous Multicores: A Framework for Reliable and Energy-Efficient Task Deployment
AuthorYin-Rong Zhuo, *Yu-Guang Chen (National Central Univ., Taiwan), Zheng-Wei Chen (National Taiwan Univ., Taiwan), Ing-Chao Lin (National Cheng Kung Univ., Taiwan)
Detailed information (abstract, keywords, etc)

R4-2
TitleHW/SW Co-Design for Efficient GPT-2 Inference on FPGA via High-Level Synthesis
AuthorShao-Tang Sung, Yi-Wen Tang, Fen-Yu Hsieh, Rong-Yi Lin, *Fang-Yu Hsu, Chih-Tsun Huang (National Tsing Hua Univ., Taiwan)
Detailed information (abstract, keywords, etc)

R4-3
TitleOptimization of Power, Area, and Slack via Multi-bit Flip-Flop Generation
Author*Chi Hsu, Yi-Ting Li, Woei-Haur Hung, Chun-Yao Wang, Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Detailed information (abstract, keywords, etc)

R4-4
TitleError Recovery in MEDA Biochips Using Deep Reinforcement Learning with Electrode Health Awareness
Author*Yash Gupta, Purrnima Singh (Netaji Subhas Univ. of Tech., New Delhi, India), Syed Rameem Zahra (Sher-e-Kashmir Univ. of Agricultural Sciences and Technology, Kashmir, J&K, India), Ankur Gupta (Netaji Subhas Univ. of Tech., New Delhi, India), Shigeru Yamashita (Ritsumeikan Univ., 1-1-1 Noji Higashi, Kusatsu, Shiga 525-8577, JAPAN., Japan)
Detailed information (abstract, keywords, etc)

R4-5
TitleA Stochastic Number Comparator by Utilizing Positive Correlation
Author*Nao Shinoda, Zhou Songyu, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Detailed information (abstract, keywords, etc)

R4-6
TitleConcurrent Detection of Multiple Thermal Fault Injection Attacks on Optical Neural Networks
Author*Kota Nishida, Yoshihiro Midoh, Noriyuki Miura (Univ. of Osaka, Japan), Satoshi Kawakami (Kyushu Univ., Japan), Alex Orailoglu (Univ. of California, San Diego, USA), Jun Shiomi (Univ. of Osaka, Japan)
Detailed information (abstract, keywords, etc)

R4-7
TitleA design hackathon to bridge AI and hardware
Author*Hideharu Amano, Takao Goto, Mizuho Nitami, Yuki Mitarai, Jiawei Yu, Yuxuan Pan, Atsutake Kosuge, Makoto Ikeda (Univ. of Tokyo, Japan)
Detailed information (abstract, keywords, etc)

R4-8
TitleA Study of Image Classifier Combining In-pixel Array Operations and Digital Matrix Operations in Image Sensors
Author*Takeshi ENOMOTO, Kota IMAGAWA, Kota YOSHIDA, Shunsuke OKURA (Ritsumeikan Univ., Japan)
Detailed information (abstract, keywords, etc)

R4-9
TitleLMESN: A Low-Power Hardware Reservoir Computing Architecture Based on MOSFET Leakage Variation
Author*Masami Utsunomiya, Hiroya Murata, Ryuto Seki (Kyoto Univ., Japan), Haoyuan Li (Xi’an Jiaotong Univ., China), Hiromitsu Awano, Takashi Sato (Kyoto Univ., Japan)
Detailed information (abstract, keywords, etc)

R4-10
TitleComparison of latch-based circuit and flip-flop-based circuit in actual device
Author*Kenji TAKAHASHI, Tadaaki TANIMOTO, Keizo HIRAGA, Masayuki HAYASHI, Takato INOUE, Kazuhiro BESSHO, Toshimasa SHIMIZU (Sony Semiconductor Solutions, Japan)
Detailed information (abstract, keywords, etc)

R4-11
TitleWafer to Lot-level S-parameter Prediction in Radio Frequency Testing Using Radial Basis Function Neural Network
Author*Huimin WANG, Yasuhiko Iguchi, Chika Tanaka (Kioxia, Japan)
Detailed information (abstract, keywords, etc)

R4-12
TitleStriking Force Estimation on a Punching Bag Using IMU and Computer Vision
AuthorTsung-Han Lai, Ming-Qi Hsu, Yi-Ting Li, Wuqian Tang (National Tsing Hua Univ., Taiwan), Yun-Ju Lee (National Tsing-Hua Univ., Taiwan), Yung-Chih Chen (National Taiwan Univ. of Science and Tech., Taiwan), Wen-Hsin Chiu, *Chun-Yao Wang (National Tsing Hua Univ., Taiwan)
Detailed information (abstract, keywords, etc)

R4-13
TitleImproving Bokeh Simulation on CPUs: Faster Inference and Better Perception
Author*Chia-Lin Chang, Hao-Cheng Hsu, Cen-En Jian, Yu-Hui Huang (Yuan Ze Univ./Department of Electrical Engineering, Taiwan)
Detailed information (abstract, keywords, etc)

R4-14
TitleCross-Modal Quantization of BLIP-2 Using Activation-Aware Weight Quantization
AuthorHui-Yun Deng, Chia-Yun Chiang, *Yu-Hui Huang (Yuan Ze Univ., Taiwan)
Detailed information (abstract, keywords, etc)