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| Thursday, October 9, 2025 |
| Title | (Keynote Speech) Verification Tools Should Certify Their Results |
| Author | Randal. E. Bryant (Carnegie Mellon Univ., USA) |
| Page | p. 1 |
| Detailed information (abstract, etc) | |
| Title | Modeling of Dynamic Input Capacitance in Trench-Gate SiC MOSFETs via Voltage-Dependent Gate Oxide Capacitance Partitioning |
| Author | *Taiki Nishioka, Kazuki Matsumoto, Hajime Takayama (Kyoto Inst. of Tech., Japan), Jun Furuta (Okayama Prefectural Univ., Japan), Kazutoshi Kobayashi, Michihiro Shintani (Kyoto Inst. of Tech., Japan) |
| Page | pp. 2 - 7 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Detailed Analysis of LLM Execution on IMAX3 and Initial Evaluation of IMAX4 Prototype for Server Environment |
| Author | *Takuto Ando, Yu Eto, Yasuhiko Nakashima (NAIST, Japan) |
| Page | pp. 8 - 13 |
| Detailed information (abstract, keywords, etc) | |
| Title | GStreamer-integrated HLS-based JPEG Encoder for Edge FPGA SoCs |
| Author | *Yuri Guimaraes Pereira Primo da Silva, Shinya Honda (Nagoya Univ., Japan), Sugako Otani (Renesas Electronics, Japan), Masato Edahiro (Nagoya Univ., Japan), Abraham Monrroy Cano (MapIV, Japan) |
| Page | pp. 14 - 19 |
| Detailed information (abstract, keywords, etc) | |
| Title | AutoPre-ACM:Autoencoder Based Precision-Enhanced Anomaly Detection For Cyber-Physical Attacks in MEDA Biochips |
| Author | *Purrnima Singh, Yash Gupta (Netaji Subhas Univ. of Tech., New Delhi, India), Syed Rameem Zahra (Sher-e-Kashmir Univ. of Agricultural Sciences and Technology, Kashmir, J&K, India), Ankur Gupta (Netaji Subhas Univ. of Tech., New Delhi, India), Shigeru Yamashita (Ritsumeikan Univ., Japan) |
| Page | pp. 20 - 25 |
| Detailed information (abstract, keywords, etc) | |
| Title | Binary Synthesis from ARM Machine Code Using a General-Purpose High-Level Synthesis System |
| Author | *Yuga Sugimoto, Nagisa Ishiura (Kwansei Gakuin Univ., Japan) |
| Page | pp. 26 - 31 |
| Detailed information (abstract, keywords, etc) | |
| Title | Quantification of Design Difficulty of Analog Circuits Based on Volume of Effectual Design Space |
| Author | Riku Anan, *Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (Univ. of Shiga Prefecture, Japan) |
| Page | pp. 32 - 37 |
| Detailed information (abstract, keywords, etc) | |
| Title | Flow-based Augmented Droplet Routing Algorithm for MEDA-Based DMFB |
| Author | *Emuun Purevdagva, Masayuki Shimoda, Satoshi Tayu, Atsushi Takahashi (Inst. of Science Tokyo, Japan) |
| Page | pp. 38 - 43 |
| Detailed information (abstract, keywords, etc) | |
| Title | Enhancing Hardware Trojan Detection via ATPG-Based Transition Delay Fault Testing with Split Fault Lists |
| Author | *Asuka Koike, Yutaka Masuda, Tohru Ishihara (Nagoya Univ., Japan) |
| Page | pp. 44 - 49 |
| Detailed information (abstract, keywords, etc) | |
| Title | Voltage and Frequency Dependence of Single Event Transient Induced by Alpha-Particle |
| Author | *Arata Matsumoto, Haruto Sugisaki, Ryuichi Nakajima (Kyoto Inst. of Tech., Japan), Jun Furuta (Okayama Prefectural Univ., Japan), Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan) |
| Page | pp. 50 - 51 |
| Detailed information (abstract, keywords, etc) | |
| Title | Evaluating Signal Integrity in InFO Package via Learning-based Methods |
| Author | *Yi-Hua Yeh, Haoru Chang, Hung-Ming Chen, Chien-Nan Liu (NYCU, Taiwan) |
| Page | pp. 52 - 57 |
| Detailed information (abstract, keywords, etc) | |
| Title | A High Precision Heuristic for Motif Extraction Using Random Forests |
| Author | *Jigen Murata, Masato Inagi, Martin Lukac, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City Univ., Japan) |
| Page | pp. 58 - 63 |
| Detailed information (abstract, keywords, etc) | |
| Title | Sizing Transformation Technique for Analog Design Migration Across Different Technologies |
| Author | Yao-Cheng Wu, King-Ho Wong, *Chien-Nan Jimmy Liu (National Yang Ming Chiao Tung Univ., Taiwan), Chia-Tseng Chiang (Richtek Technology, Taiwan) |
| Page | pp. 64 - 65 |
| Detailed information (abstract, keywords, etc) | |
| Title | Equalizing QAM Waveform Distortion with Linear SVM Classifier and its Machine Learning Dataset Generation |
| Author | *Yiwei Liu, Yukina Haruta, Yutaka Masuda, Tohru Ishihara (Nagoya Univ., Japan) |
| Page | pp. 66 - 71 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Hardware Design Environment for ROS2 Node to FPGA-Integrated SoC |
| Author | Xingze Li (Nagoya Univ., Japan), *Ryota Yamamoto (National Inst. of Tech., Tomakomai College, Japan), Shinya Honda (Nagoya Univ., Japan) |
| Page | pp. 72 - 77 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Talk) Towards Emerging Device Computing for the Post-Moore Era |
| Author | Koji Inoue (Kyushu Univ., Japan) |
| Page | p. 78 |
| Detailed information (abstract, etc) | |
| Title | Optimal Golomb Coding via Dynamic Programming and Its Application on Large Language Model Compression |
| Author | Jen-Hung Yang, Zhi-Kai Xu, *Juinn-Dar Huang (National Yang Ming Chiao Tung Univ., Taiwan) |
| Page | pp. 79 - 84 |
| Detailed information (abstract, keywords, etc) | |
| Title | On Ratio of Embedded RECON Spare Cell Types for Technology Remapping |
| Author | *Yasuaki Nabetani, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
| Page | pp. 85 - 90 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Seamless Hardware/Software Switching Technique for Embedded Systems Using HDLRuby |
| Author | *Lovic Gauthier, Sachi Yoshigai (National Inst. of Tech., Ariake College, Japan) |
| Page | pp. 91 - 96 |
| Detailed information (abstract, keywords, etc) | |
| Title | Speeding Up a Routing Method Considering Droplet Splitting on MEDABiochips by Dijkstra’s Method |
| Author | *Issei Nakamura, Shigeru Yamashita, Hiroyuki Tomiyama (Ritsumeikan Univ., Japan), Ankur Guputa (Netaji Subhas Univ. of Tech., India) |
| Page | pp. 97 - 102 |
| Detailed information (abstract, keywords, etc) | |
| Title | EMESN: an Extended MOSFET Reservoir Computing Architecture for Echo State Networks with Hardware-Software Co-Optimization |
| Author | *Haoyuan Li (Xi'an Jiaotong Univer./Kyoto Univ., China), Masami Utsunomiya, Ryuto Seki, Takashi Sato (Kyoto Univ., Japan), Feng Liang (Xi'an Jiaotong Univ., China) |
| Page | pp. 103 - 108 |
| Detailed information (abstract, keywords, etc) | |
| Title | Development of Tsugaru Dialect Translation System Using Transparent Display |
| Author | *Haruto Saito, Masashi Imai (Hirosaki Univ., Japan) |
| Page | pp. 109 - 114 |
| Detailed information (abstract, keywords, etc) | |
| Title | Accelerated Behavioral Simulation for Optimizing MOSFET-Based Echo State Networks |
| Author | *Ryuto Seki, Masami Utsunomiya (Kyoto Univ., Japan), Haoyuan Li (Xi'an Jiaotong Univ., China), Hiromitsu Awano, Takashi Sato (Kyoto Univ., Japan) |
| Page | pp. 115 - 120 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Design Method for Single-Rail LUT Cascades |
| Author | *Tsutomu Sasao (Meiji Univ., Japan) |
| Page | pp. 121 - 126 |
| Detailed information (abstract, keywords, etc) | |
| Title | Implementation of Interrupt Handlers in Full Hardware Implementation of RTOS-Based Systems |
| Author | *Yuki Nakatani, Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Hiroyuki Tomiyama, Hiroyuki Kanbara (Ritsumeikan Univ., Japan) |
| Page | pp. 127 - 132 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Error Diagnosis Technique Applicable to Single Line Errors Based on Location Variable Simulation |
| Author | *Kazuki Sakamoto, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) |
| Page | pp. 133 - 138 |
| Detailed information (abstract, keywords, etc) | |
| Title | Multi-Objective Optimization of RESURF Structure in SiC MOSFET for I-V and C-V Characteritics |
| Author | *Sota Oyama (Hirosaki Univ., Japan), Ichirota Takazawa (Jedat, Japan), Satoru Honda, Toshiki Kanamoto (Hirosaki Univ., Japan) |
| Page | pp. 139 - 144 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Systematic Hardware Solution for GDPR Compliance |
| Author | Yi-Chun Yang, *Ren-Song Tsay (National Tsing Hua Univ., Taiwan) |
| Page | pp. 145 - 147 |
| Detailed information (abstract, keywords, etc) | |
| Title | Reducing Registers in Convolution Operation for Binarized Neural Networks with Register-Bridge LSI Architecture |
| Author | *Jun Masuda, Kazuhito Ito (Saitama Univ., Japan) |
| Page | pp. 148 - 153 |
| Detailed information (abstract, keywords, etc) | |
| Title | Extending the Single-Target Droplet Generation Method CoDOS to Multi-Target Synthesis |
| Author | Yusuke Igarashi, *Shigeru Yamashita (Ritsumeikan Univ., Japan) |
| Page | pp. 154 - 158 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Panel Discussion) Classical Techniques Meet Emerging Technologies: Retrospectives and Future Prospects |
| Author | Moderator: Shin-ichi Minato (Kyoto Univ., Japan), Panelists: Randal E. Bryant (Carnegie Mellon Univ., USA), Hideki Nishizawa (NTT, Japan), Jie-Hong Roland Jiang (National Taiwan Univ., Taiwan), Koji Inoue (Kyushu Univ., Japan), Chun-Yao Wang (National Tsing Hua Univ., Taiwan), Shigeru Yamashita (Ritsumeikan Univ., Japan), Organizer: Shin-ichi Minato (Kyoto Univ., Japan) |
| Page | p. 159 |
| Detailed information (abstract, etc) | |
| Friday, October 10, 2025 |
| Title | (Keynote Speech) New Optical Path Design Trend on the IOWN Global Forum Open All-Photonics Network: Background, Application, and Key Enablers |
| Author | Hideki Nishizawa (NTT, Japan) |
| Page | p. 160 |
| Detailed information (abstract, etc) | |
| Title | Cross-Design Power Trace Prediction using Graph Neural Network |
| Author | Shih-Chun Lin, *Bo-Hao Haung, Yung-Chih Chen (National Taiwan Univ. of Science and Tech., Taiwan), Wang-Dauh Tseng (Yuan Ze Univ., Taiwan) |
| Page | pp. 161 - 166 |
| Detailed information (abstract, keywords, etc) | |
| Title | ILP-Based Movable Layout Replacer for Standard Cells with Extending Metal Boundaries |
| Author | Ya-Chu Yang, Shih-Sian Tang, *Chen-Chen Yeh, Shao-Chien Lu, Hui-Lin Cho, Yu-Cheng Lin, Rung-Bin Lin (Yuan Ze Univ., Taiwan) |
| Page | pp. 167 - 172 |
| Detailed information (abstract, keywords, etc) | |
| Title | Compact QUBO Formulation of Resource-Constrained Operation Scheduling in High-Level LSI Design |
| Author | *Haruki Yamagishi, Takuto Kishimoto, Kazuhito Ito (Saitama Univ., Japan) |
| Page | pp. 173 - 178 |
| Detailed information (abstract, keywords, etc) | |
| Title | Efficitent FPGA Implementation of Multiple-Input Adders Using Generalized Parallel Counter (6,0,7;5) |
| Author | Mugi Noda, *Ryo Kanai, Nagisa Ishiura (Kwansei Gakuin Univ., Japan) |
| Page | pp. 179 - 184 |
| Detailed information (abstract, keywords, etc) | |
| Title | Genetic Algorithm-based Layer-wise Adaptive Filter Pruning |
| Author | Ting-Yi Liu, Yi-Ting Li, Wuqian Tang (National Tsing Hua Univ., Taiwan), *Yung-Chih Chen (National Taiwan Univ. of Science and Tech., Taiwan), Shih-Chieh Chang, Chun-Yao Wang (National Tsing Hua Univ., Taiwan) |
| Page | pp. 185 - 190 |
| Detailed information (abstract, keywords, etc) | |
| Title | Evaluation of Free-form Conversation Learning Effects in a Tsugaru Dialect Speech Recognition Model |
| Author | *Akihiro Murakami, Masashi Imai (Hirosaki Univ., Japan) |
| Page | pp. 191 - 192 |
| Detailed information (abstract, keywords, etc) | |
| Title | High-Speed SIFT Descriptor Generation with 36 Small-Region Division and Logic-Synthesis Evaluation |
| Author | *Ayumu Mitsumoto, Tetsuo Hironaka (Hiroshima City Univ., Japan) |
| Page | pp. 193 - 198 |
| Detailed information (abstract, keywords, etc) | |
| Title | Numberlink Problem Variants Modeled after FPGA Routing Fabrics and their Solvers that Enumerate all the Solutions |
| Author | *Ryohei Komi, Hiroyuki Ochi (Ritsumeikan Univ., Japan) |
| Page | pp. 199 - 204 |
| Detailed information (abstract, keywords, etc) | |
| Title | Implementation and Evaluation of a Speculative Execution-Based FPGA Accelerator for Electronic Circuit Simulation Using Gauss-Jordan and BiCGSTAB Methods |
| Author | *Yuma Omoto, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ., Japan) |
| Page | pp. 205 - 210 |
| Detailed information (abstract, keywords, etc) | |
| Title | Efficient and Accurate SC Arithmetic Circuits Using Bit Manipulation Based on Interval Partitioning of Bit Strings |
| Author | *Yota Yanagida, Shigeru Yamashita (Ritsumeikan Univ., Japan) |
| Page | pp. 211 - 216 |
| Detailed information (abstract, keywords, etc) | |
| Title | Logic Gate Design Using Vertical Nanowire Transistors |
| Author | *Genta Nakamura (Kyushu Univ., Japan), Katsuhiro Tomioka (Hokkaido Univ., Japan), Koji Inoue (Kyushu Univ., Japan) |
| Page | pp. 217 - 222 |
| Detailed information (abstract, keywords, etc) | |
| Title | Subitizing-Inspired Large Language Models for Floorplanning |
| Author | Chen-Chen Yeh, *Shao-Chien Lu, Hui-Lin Cho, Yu-Cheng Lin, Rung-Bin Lin (Yuan Ze Univ., Taiwan) |
| Page | pp. 223 - 228 |
| Detailed information (abstract, keywords, etc) | |
| Title | Reinforcement Learning-Based Loop Optimization Using the Polyhedral Model |
| Author | *Hayato Takahashi, Motoki Amagasaki, Masato Kiyama, Kenshu Seto, Mery Diana (Kumamoto Univ., Japan) |
| Page | pp. 229 - 234 |
| Detailed information (abstract, keywords, etc) | |
| Title | Evaluation of FPGA Development Boards in a Cryogenic Environment |
| Author | *Tomoki Takashima, Masashi Imai (Hirosaki Univ., Japan) |
| Page | pp. 235 - 240 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Talk) A Symbolic Approach to Exact Quantum Circuit Simulation and Verification |
| Author | Jie-Hong Roland Jiang (National Taiwan Univ., Taiwan) |
| Page | p. 241 |
| Detailed information (abstract, etc) | |
| Title | Combatting Transient Errors and Aging in Heterogeneous Multicores: A Framework for Reliable and Energy-Efficient Task Deployment |
| Author | Yin-Rong Zhuo, *Yu-Guang Chen (National Central Univ., Taiwan), Zheng-Wei Chen (National Taiwan Univ., Taiwan), Ing-Chao Lin (National Cheng Kung Univ., Taiwan) |
| Page | pp. 242 - 247 |
| Detailed information (abstract, keywords, etc) | |
| Title | HW/SW Co-Design for Efficient GPT-2 Inference on FPGA via High-Level Synthesis |
| Author | Shao-Tang Sung, Yi-Wen Tang, Fen-Yu Hsieh, Rong-Yi Lin, *Fang-Yu Hsu, Chih-Tsun Huang (National Tsing Hua Univ., Taiwan) |
| Page | pp. 248 - 253 |
| Detailed information (abstract, keywords, etc) | |
| Title | Optimization of Power, Area, and Slack via Multi-bit Flip-Flop Generation |
| Author | Chi Hsu, Yi-Ting Li, Woei-Haur Hung, Chun-Yao Wang, *Ting-Chi Wang (National Tsing Hua Univ., Taiwan) |
| Page | pp. 254 - 259 |
| Detailed information (abstract, keywords, etc) | |
| Title | Error Recovery in MEDA Biochips Using Deep Reinforcement Learning with Electrode Health Awareness |
| Author | *Yash Gupta, Purrnima Singh (Netaji Subhas Univ. of Tech., New Delhi, India), Syed Rameem Zahra (Sher-e-Kashmir Univ. of Agricultural Sciences and Technology, Kashmir, J&K, India), Ankur Gupta (Netaji Subhas Univ. of Tech., New Delhi, India), Shigeru Yamashita (Ritsumeikan Univ., Japan) |
| Page | pp. 260 - 265 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Stochastic Number Comparator by Utilizing Positive Correlation |
| Author | *Nao Shinoda, Zhou Songyu, Shigeru Yamashita (Ritsumeikan Univ., Japan) |
| Page | pp. 266 - 271 |
| Detailed information (abstract, keywords, etc) | |
| Title | Concurrent Detection of Multiple Thermal Fault Injection Attacks on Optical Neural Networks |
| Author | *Kota Nishida, Yoshihiro Midoh, Noriyuki Miura (Univ. of Osaka, Japan), Satoshi Kawakami (Kyushu Univ., Japan), Alex Orailoglu (Univ. of California, San Diego, USA), Jun Shiomi (Univ. of Osaka, Japan) |
| Page | pp. 272 - 277 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Design Hackathon to Bridge AI and Hardware |
| Author | *Hideharu Amano, Takao Goto, Mizuho Nitami, Yuki Mitarai, Jiawei Yu, Yuxuan Pan, Atsutake Kosuge, Makoto Ikeda (Univ. of Tokyo, Japan) |
| Page | pp. 278 - 283 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Study of Image Classifier Combining In-pixel Array Operations and Digital Matrix Operations in Image Sensors |
| Author | *Takeshi Enomoto, Kota Imagawa, Kota Yoshida, Shunsuke Okura (Ritsumeikan Univ., Japan) |
| Page | pp. 284 - 289 |
| Detailed information (abstract, keywords, etc) | |
| Title | LMESN: A Low-Power Hardware Reservoir Computing Architecture Based on MOSFET Leakage Variation |
| Author | *Masami Utsunomiya, Hiroya Murata, Ryuto Seki (Kyoto Univ., Japan), Haoyuan Li (Xi'n Jiaotong Univ., China), Hiromitsu Awano, Takashi Sato (Kyoto Univ., Japan) |
| Page | pp. 290 - 295 |
| Detailed information (abstract, keywords, etc) | |
| Title | Comparison of Latch-Based Circuit and Flip-Flop-Based Circuit in Actual Device |
| Author | *Kenji Takahashi, Tadaaki Tanimoto, Keizo Hiraga, Masayuki Hayashi, Takato Inoue, Kazuhiro Bessho, Toshimasa Shimizu (Sony Semiconductor Solutions, Japan) |
| Page | pp. 296 - 301 |
| Detailed information (abstract, keywords, etc) | |
| Title | Wafer to Lot-level S-parameter Prediction in Radio Frequency Testing Using Radial Basis Function Neural Network |
| Author | *Huimin Wang, Yasuhiko Iguchi, Chika Tanaka (Kioxia, Japan) |
| Page | pp. 302 - 305 |
| Detailed information (abstract, keywords, etc) | |
| Title | Striking Force Estimation on a Punching Bag Using IMU and Computer Vision |
| Author | Tsung-Han Lai, Ming-Qi Hsu, Yi-Ting Li, Wuqian Tang, Yun-Ju Lee (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (National Taiwan Univ. of Science and Tech., Taiwan), Wen-Hsin Chiu, *Chun-Yao Wang (National Tsing Hua Univ., Taiwan) |
| Page | pp. 306 - 311 |
| Detailed information (abstract, keywords, etc) | |
| Title | Improving Bokeh Simulation on CPUs: Faster Inference and Better Perception |
| Author | *Chia-Lin Chang, Hao-Cheng Hsu, Cen-En Jian, Yu-Hui Huang (Yuan Ze Univ., Taiwan) |
| Page | pp. 312 - 313 |
| Detailed information (abstract, keywords, etc) | |
| Title | Cross-Modal Quantization of BLIP-2 Using Activation-Aware Weight Quantization |
| Author | Hui-Yun Deng, Chia-Yun Chiang, *Yu-Hui Huang (Yuan Ze Univ., Taiwan) |
| Page | pp. 314 - 315 |
| Detailed information (abstract, keywords, etc) | |