SASIMI 2022
The 24th Workshop on Synthesis And System Integration of Mixed Information Technologies
Technical Program

Remark: The presenter of each paper is marked with "*". Time zone is JST (=UTC+9:00)

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Monday, October 24, 2022

Premier Hall (on-site)	Zoom (online)	Gather (online)
Op Opening 9:00 - 9:40
K1 Keynote Speech I 9:40 - 10:40
A Poster Session (Group A) 10:40 - 12:10		BO Poster Session (Group B) 10:40 - 12:10
Lunch Break 12:10 - 13:40
I1 Invited Talk I 13:40 - 14:40
Break & Exhibitors' Presentation 14:40 - 15:00
		V Poster Session (Group V) 15:00 - 16:40
K2 Keynote Speech II 16:40 - 17:40

Tuesday, October 25, 2022

Premier Hall (on-site)	Zoom (online)	Gather (online)
I2 Invited Talk II 9:00 - 10:00
B Poster Session (Group B) 10:00 - 11:30		CO Poster Session (Group C) 10:00 - 11:30
Lunch Break 11:30 - 13:00
I3 Invited Talk III 13:00 - 14:00
C Poster Session (Group C) 14:00 - 15:30		AO Poster Session (Group A) 14:00 - 15:30
Cl Closing 15:30 - 15:40

List of papers

Remark: The presenter of each paper is marked with "*". Time zone is JST (=UTC+9:00)

Monday, October 24, 2022

[To Session Table]

Opening
Time: 9:00 - 9:40, Monday, October 24, 2022
Location: Premier Hall (on-site) / Zoom (online)

[To Session Table]

Keynote Speech I
Time: 9:40 - 10:40, Monday, October 24, 2022
Location: Premier Hall (on-site) / Zoom (online)
Chair: Yoshinori Takeuchi (Kindai Univ., Japan)

K1-1 (Time: 9:40 - 10:40)

Title	(Keynote Speech) Hardware/Software Codesign for Machine Learning Acceleration with Silicon Photonics
Author	Sudeep Pasricha (Colorado State Univ., USA)
Page	p. 1
Detailed information (abstract, keywords, etc)

[To Session Table]

Poster Session (Group A)
Time: 10:40 - 12:10, Monday, October 24, 2022
Location: Premier Hall (on-site)
Chair: Kenshu Seto (Tokyo City Univ., Japan)

Outstanding Paper Award
A-1 (Time: 10:40 - 10:42)

Title	Full Hardware Implementation of RTOS-Based Systems Using General High-Level Synthesizer
Author	Takuya Ando, Iori Muguruma, *Yugo Ishii, Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Hiroyuki Tomiyama (Ritsumeikan Univ., Japan), Hiroyuki Kanbara (ASTEM RI/Kyoto, Japan)
Page	pp. 2 - 7
Detailed information (abstract, keywords, etc)

A-2 (Time: 10:42 - 10:44)

Title	SNRoverSDNN: A Metric for Robust CNN-based ROI Selection in Remote Heart Rate Extraction
Author	*Yuta Hitotsuyanagi, Takashi Sato (Kyoto Univ., Japan)
Page	pp. 8 - 13
Detailed information (abstract, keywords, etc)

A-3 (Time: 10:44 - 10:46)

Title	Hardware RTOS Services for Full Hardware Implementation of RTOS-Based Systems
Author	*Hiro Minamiguchi, Masaki Nakahara, Yugo Ishii, Yukino Shinohara, Iori Muguruma, Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
Page	pp. 14 - 19
Detailed information (abstract, keywords, etc)

A-4 (Time: 10:46 - 10:48)

Title	Importance Evaluation Methodology of FFs for Design Optimization of Approximate Computing Circuits
Author	*Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara (Nagoya Univ., Japan)
Page	pp. 20 - 25
Detailed information (abstract, keywords, etc)

A-5 (Time: 10:48 - 10:50)

Title	Bottleneck Channel Routing to Reduce the Area of Analog VLSI
Author	*Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Inst. of Tech., Japan), Yukichi Todoroki, Makoto Minami (Jedat, Japan)
Page	pp. 26 - 31
Detailed information (abstract, keywords, etc)

A-6 (Time: 10:50 - 10:52)

Title	Binding and Scheduling of 2×3 Mixers for Transport-Free Sample Preparation Using Programmable Microfluidic Devices
Author	*Masataka Hirai, Shigeru Yamashita (Ritsumeikan Univ., Japan), Sudip Roy (Indian Inst. of Tech. (IIT) Roorkee, India), Hiroyuki Tomiyama (Ritsumeikan Univ., Japan)
Page	pp. 32 - 37
Detailed information (abstract, keywords, etc)

A-7 (Time: 10:52 - 10:54)

Title	Segmented DAC Linearity Improvement Algorithm Using Unit Cell Sorted Alternately with Digital Method
Author	*Yi Liu, Anna Kuwana, Shogo Katayama, Xiongyan Li (Gunma Univ., Japan), Atsushi Motozawa (Renesas Electronics, Japan), Haruo Kobayashi (Gunma Univ., Japan)
Page	pp. 38 - 43
Detailed information (abstract, keywords, etc)

A-8 (Time: 10:54 - 10:56)

Title	Aging-Compromised Computing-In-Memory Dot-Product Calculation Technique Through DVFS
Author	*Yu-Guang Chen, Chi-Hsu Wang (National Central Univ., Taiwan), Ing-Chao Lin (National Cheng Kung Univ., Taiwan)
Page	pp. 44 - 47
Detailed information (abstract, keywords, etc)

A-9 (Time: 10:56 - 10:58)

Title	An Implementation of Self-Testable Layout-Level Scan C-element
Author	*Kokoro Yamasaki, Hiroshi Iwata, Ken'ichi Yamaguchi (National Inst. of Tech., Nara College, Japan)
Page	pp. 48 - 53
Detailed information (abstract, keywords, etc)

A-10 (Time: 10:58 - 11:00)

Title	Voice Learning of Reservoir Computing Architecture using Ternary Content Addressable Memory with Individuality
Author	*Sayaka Akiyama, Go Ajiki, Xiangbo Kong, Takeshi Kumaki (Ritsumeikan Univ., Japan)
Page	pp. 54 - 59
Detailed information (abstract, keywords, etc)

Outstanding Paper Award
A-11 (Time: 11:00 - 11:02)

Title	Formulation of Maximum Independent Set Problem for Simulated Quantum Annealing Machine
Author	*Haruki Nakayama, Yukihide Kohira (Univ. of Aizu, Japan)
Page	pp. 60 - 65
Detailed information (abstract, keywords, etc)

A-12 (Time: 11:02 - 11:04)

Title	Efficient Hardware Architecture for Taylor-Series Expansion Calculation Using Distributed Arithmetic with Term Division
Author	*Xaybandith Hemthavy, Jianglin Wei, Shogo Katayama, Anna Kuwana, Haruo Kobayashi (Gunma Univ., Japan), Kazuyoshi Kubo (Oyama National College of Tech., Japan)
Page	pp. 66 - 70
Detailed information (abstract, keywords, etc)

[To Session Table]

Poster Session (Group B)
Time: 10:40 - 12:10, Monday, October 24, 2022
Location: Gather (online)
Chair: Ing-Jer Huang (National Sun Yat-sen Univ., Taiwan)

These papers are assigned to session B

BO-D:1 (Time: 10:40 - 10:42)

Title Optimal Synthesis of NNA-Compliant Quantum Circuits in 2-D Architectures by Utilizing Don't Care Conditions

Author *Kyohei Seino, Shigeru Yamashita (Ritsumeikan Univ., Japan)

Detailed information (abstract, keywords, etc)
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BO-D:2 (Time: 10:42 - 10:44)

Title	On Technology Remapping Approach Using Multi-Gate Functionality of Reconfigurable Cells for Post-Mask ECO
Author	*Tomohiro Nishiguchi, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
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BO-D:3 (Time: 10:44 - 10:46)

Title	Binary Synthesis Using High-Level Synthesizer as its Back-End
Author	Ryo Nakamichi, *Sho Kishimoto, Nagisa Ishiura, Takumi Kondo (Kwansei Gakuin Univ., Japan)
Detailed information (abstract, keywords, etc)
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BO-D:4 (Time: 10:46 - 10:48)

Title	An Error Diagnosis Technique Based on Location Variable Simulation Employing Implicit Representation of Error Location Sets
Author	*Hiroki Tsuyama, Akio Masamori, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Detailed information (abstract, keywords, etc)
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BO-D:5 (Time: 10:48 - 10:50)

Title	Extending Channel Routing Method for Two-Layer Routing Problem Allowing for Terminals Placed within the Routing Area
Author	*Kaito Ishigami, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Detailed information (abstract, keywords, etc)
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BO-D:6 (Time: 10:50 - 10:52)

Title	A Study on the Design of Interface Circuits Between Synchronous-Asynchronous Modules Using Click Elements
Author	*Shogo Semba, Hiroshi Saito (Univ. of Aizu, Japan)
Detailed information (abstract, keywords, etc)
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BO-D:7 (Time: 10:52 - 10:54)

Title	A Scalable Linear Equation Solver FPGA using High-Level Synthesis
Author	*Haopeng Meng, Kazutoshi Wakabayashi, Tadahiro Kuroda (Univ. of Tokyo, Japan)
Detailed information (abstract, keywords, etc)
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BO-D:8 (Time: 10:54 - 10:56)

Title	Tail Layer CNN Training for a SoC-based FPGA
Author	*Yuki Takashima, Akira Jinguji, Ryosuke Kuramochi, Ryota Kayanoma, Hiroki Nakahara (Tokyo Inst. of Tech., Japan)
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BO-D:9 (Time: 10:56 - 10:58)

Title	A Thermally Optimizing Method of Thin Film Resistor Trimming with Machine Learning
Author	*Tomoya Akasaka (Hirosaki Univ., Japan), Shigeru Hidaka (Nikkohm, Japan), Ryosuke Watanabe, Taisei Arima, Atsushi Kurokawa, Toshiki Kanamoto (Hirosaki Univ., Japan)
Detailed information (abstract, keywords, etc)
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BO-D:10 (Time: 10:58 - 11:00)

Title	Development of Text Translation System from Tsugaru Dialect into Common Japanese
Author	*Taiki Niida, Masashi Imai (Hirosaki Univ., Japan)
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BO-D:11 (Time: 11:00 - 11:02)

Title	On Providing Faster IR-Drop Forecast via SVM-Based Solutions
Author	Ya-Ying Chien (NYCU, Taiwan), Chang-Tzu Lin (ITRI, Taiwan), *Hung-Ming Chen (NYCU, Taiwan)
Detailed information (abstract, keywords, etc)
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[To Session Table]

Invited Talk I
Time: 13:40 - 14:40, Monday, October 24, 2022
Location: Premier Hall (on-site) / Zoom (online)
Chair: Toshiki Kanamoto (Hirosaki Univ., Japan)

I1-1 (Time: 13:40 - 14:40)

Title	(Invited Talk) Utilization of Dominant Time Constant Information to Improve the Efficiency of Power and Hard-Breakdown Device Simulation
Author	Shigetaka Kumashiro (Kyoto Inst. of Tech., Japan)
Page	p. 71
Detailed information (abstract, keywords, etc)

[To Session Table]

Poster Session (Group V)
Time: 15:00 - 16:40, Monday, October 24, 2022
Location: Gather (online)
Chair: Yukihide Kohira (Univ. of Aizu, Japan)

V-1 (Time: 15:00 - 15:02)

Title	Electronic Component Placement Optimization for Heat Measures of Smartglasses
Author	*Kyosuke Kusumi (Hirosaki Univ., Japan), Koutaro Hachiya (Teikyo Heisei Univ., Japan), Ryotaro Kudo, Toshiki Kanamoto, Atsushi Kurokawa (Hirosaki Univ., Japan)
Page	pp. 72 - 76
Detailed information (abstract, keywords, etc)

V-2 (Time: 15:02 - 15:04)

Title	ML-assisted Sizing Approach for Low-Voltage Circuits Considering Process Variation
Author	*Ling-Yen Song, Chih-Yun Chou, Tung-Chieh Kuo, Chien-Nan Jimmy Liu, Juinn-Dar Huang (National Yang Ming Chiao Tung Univ., Taiwan)
Page	pp. 77 - 80
Detailed information (abstract, keywords, etc)

V-3 (Time: 15:04 - 15:06)

Title	Tag-Less Compression for FPGA Configuration Data
Author	*Souhei Takagi, Naoya Niwa, Yusuke Yanai, Hideharu Amano (Keio Univ., Japan), Masaki Amagasaki, Yuya Nakazato, Masahiro Iida (Kumamoto Univ., Japan)
Page	pp. 81 - 82
Detailed information (abstract, keywords, etc)

V-4 (Time: 15:06 - 15:08)

Title	Co-optimization of Prefix Structure and Bit-Line Arrangement for Long Bit-Length Parallel Prefix Adders
Author	*Kazuya Uryu, Mineo Kaneko (JAIST, Japan)
Page	pp. 83 - 84
Detailed information (abstract, keywords, etc)

V-5 (Time: 15:08 - 15:10)

Title	A Global Buffer and Splitter Insertion Algorithm in AQFP Circuits
Author	*Rongliang Fu (Chinese Univ. of Hong Kong, Hong Kong), Mengmeng Wang (Yokohama National Univ., Japan), Yirong Kan (NAIST, Japan), Olivia Chen (Tokyo City Univ., Japan), Nobuyuki Yoshikawa (Yokohama National Univ., Japan), Tsung-Yi Ho (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 85 - 90
Detailed information (abstract, keywords, etc)

V-6 (Time: 15:10 - 15:12)

Title	Heating of Foreign Object in Inductive Wireless Charging
Author	*Issei Sato, Ryotaro Kudo, Toshiki Kanamoto (Hirosaki Univ., Japan), Koutaro Hachiya (Teikyo Heisei Univ., Japan), Shinsuke Kashiwazaki, Atsushi Kurokawa (Hirosaki Univ., Japan)
Page	pp. 91 - 95
Detailed information (abstract, keywords, etc)

V-7 (Time: 15:12 - 15:14)

Title	An Efficient LSI Implementation of the Summation of Products in Convolution Operation for Binarized Neural Networks
Author	*Mitsuru Takahashi, Kazuhito Ito (Saitama Univ., Japan)
Page	pp. 96 - 101
Detailed information (abstract, keywords, etc)

[To Session Table]

Keynote Speech II
Time: 16:40 - 17:40, Monday, October 24, 2022
Location: Premier Hall (on-site) / Zoom (online)
Chair: Hiroyuki Ochi (Ritsumeikan Univ., Japan)

K2-1 (Time: 16:40 - 17:40)

Title	(Keynote Speech) One is not Enough: Using Hybrid Proof Engines for Polynomial Formal Verification
Author	*Rolf Drechsler (Univ. of Bremen/DFKI, Germany), Alireza Mahzoon (Univ. of Bremen, Germany)
Page	pp. 102 - 107
Detailed information (abstract, keywords, etc)

Tuesday, October 25, 2022

[To Session Table]

Invited Talk II
Time: 9:00 - 10:00, Tuesday, October 25, 2022
Location: Premier Hall (on-site) / Zoom (online)
Chair: Hiroyuki Ochi (Ritsumeikan Univ., Japan)

I2-1 (Time: 9:00 - 10:00)

Title	(Invited Talk) Design and Development of Electronic Devices for Driving, Measuring and Controlling Humanoid Robots
Author	Kunio Kojima (Univ. of Tokyo, Japan)
Page	p. 108
Detailed information (abstract, keywords, etc)

[To Session Table]

Poster Session (Group B)
Time: 10:00 - 11:30, Tuesday, October 25, 2022
Location: Premier Hall (on-site)
Chair: Masato Inagi (Hiroshima City Univ., Japan)

Outstanding Paper Award
B-1 (Time: 10:00 - 10:02)

Title	Optimal Synthesis of NNA-Compliant Quantum Circuits in 2-D Architectures by Utilizing Don't Care Conditions
Author	*Kyohei Seino, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Page	pp. 109 - 114
Detailed information (abstract, keywords, etc)

B-2 (Time: 10:02 - 10:04)

Title	On Technology Remapping Approach Using Multi-Gate Functionality of Reconfigurable Cells for Post-Mask ECO
Author	*Tomohiro Nishiguchi, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 115 - 120
Detailed information (abstract, keywords, etc)

B-3 (Time: 10:04 - 10:06)

Title	Binary Synthesis Using High-Level Synthesizer as its Back-End
Author	Ryo Nakamichi, *Sho Kishimoto, Nagisa Ishiura, Takumi Kondo (Kwansei Gakuin Univ., Japan)
Page	pp. 121 - 126
Detailed information (abstract, keywords, etc)

B-4 (Time: 10:06 - 10:08)

Title	An Error Diagnosis Technique Based on Location Variable Simulation Employing Implicit Representation of Error Location Sets
Author	*Hiroki Tsuyama, Akio Masamori, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan)
Page	pp. 127 - 132
Detailed information (abstract, keywords, etc)

B-5 (Time: 10:08 - 10:10)

Title	Extending Channel Routing Method for Two-Layer Routing Problem Allowing for Terminals Placed within the Routing Area
Author	*Kaito Ishigami, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech., Japan)
Page	pp. 133 - 138
Detailed information (abstract, keywords, etc)

B-6 (Time: 10:10 - 10:12)

Title	A Study on the Design of Interface Circuits Between Synchronous-Asynchronous Modules Using Click Elements
Author	*Shogo Semba, Hiroshi Saito (Univ. of Aizu, Japan)
Page	pp. 139 - 144
Detailed information (abstract, keywords, etc)

B-7 (Time: 10:12 - 10:14)

Title	A Scalable Linear Equation Solver FPGA using High-Level Synthesis
Author	*Haopeng Meng, Kazutoshi Wakabayashi, Tadahiro Kuroda (Univ. of Tokyo, Japan)
Page	pp. 145 - 150
Detailed information (abstract, keywords, etc)

B-8 (Time: 10:14 - 10:16)

Title	Tail Layer CNN Training for a SoC-based FPGA
Author	*Yuki Takashima, Akira Jinguji, Ryosuke Kuramochi, Ryota Kayanoma, Hiroki Nakahara (Tokyo Inst. of Tech., Japan)
Page	pp. 151 - 156
Detailed information (abstract, keywords, etc)

B-9 (Time: 10:16 - 10:18)

Title	A Thermally Optimizing Method of Thin Film Resistor Trimming with Machine Learning
Author	*Tomoya Akasaka (Hirosaki Univ., Japan), Shigeru Hidaka (Nikkohm, Japan), Ryosuke Watanabe, Taisei Arima, Atsushi Kurokawa, Toshiki Kanamoto (Hirosaki Univ., Japan)
Page	pp. 157 - 162
Detailed information (abstract, keywords, etc)

B-10 (Time: 10:18 - 10:20)

Title	Development of Text Translation System from Tsugaru Dialect into Common Japanese
Author	*Taiki Niida, Masashi Imai (Hirosaki Univ., Japan)
Page	pp. 163 - 167
Detailed information (abstract, keywords, etc)

B-11 (Time: 10:20 - 10:22)

Title	On Providing Faster IR-Drop Forecast via SVM-Based Solutions
Author	Ya-Ying Chien (NYCU, Taiwan), Chang-Tzu Lin (ITRI, Taiwan), *Hung-Ming Chen (NYCU, Taiwan)
Page	pp. 168 - 171
Detailed information (abstract, keywords, etc)

[To Session Table]

Poster Session (Group C)
Time: 10:00 - 11:30, Tuesday, October 25, 2022
Location: Gather (online)
Chair: Takeshi Kumaki (Ritsumeikan Univ., Japan)

These papers are assigned to session C

CO-D:1 (Time: 10:00 - 10:02)

Title DNN-based Accelerator for Intelligent Robotic Arm Control with High-Level Synthesis

Author *Yu-Chien Chung, Hao-Hsiang Lian, Yong-Lun Xiao, Chih-Tsun Huang, Jing-Jia Liou (National Tsing Hua Univ., Taiwan)

Detailed information (abstract, keywords, etc)
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CO-D:2 (Time: 10:02 - 10:04)

Title	Trotter Based Parallel Processing of Quantum Annealing for FPGA
Author	*Sohei Shimomai, Shinji Kimura (Waseda Univ., Japan)
Detailed information (abstract, keywords, etc)
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CO-D:3 (Time: 10:04 - 10:06)

Title	An Efficient Realization of Power-Root SC Calculations by Inserting Bits
Author	*Yuto Arimura, Shigeru Yamashita (Ritsumeikan Univ., Japan)
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CO-D:4 (Time: 10:06 - 10:08)

Title	An NDA-free Oriented Open PDK Technology and EDA for Small Volume LSI Developments
Author	*Seijiro Moriyama (Anagix, Japan), Tadaaki Tsuchiya, Shingo Ura (Logic Research, Japan)
Detailed information (abstract, keywords, etc)
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CO-D:5 (Time: 10:08 - 10:10)

Title	Development of Diagnosis-based Hardware Trojan Tolerate System
Author	*Takuro Kasai, Masashi Imai (Hirosaki Univ., Japan)
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CO-D:6 (Time: 10:10 - 10:12)

Title	Feasibility Study of DSP Block Mapping Algorithms for FPGAs Utilizing SAT-solver and Top-down ZDD Construction
Author	*Takuya Serizawa, Koyo Shibata (Ritsumeikan Univ., Japan), Takashi Imagawa (Meiji Univ., Japan), Hiroyuki Ochi (Ritsumeikan Univ., Japan)
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CO-D:7 (Time: 10:12 - 10:14)

Title	Evaluating Accuracy of Quantum Circuit Learning via Quantum Circuit Mapping
Author	*Nanao Segawa, Takashi Sato (Kyoto Univ., Japan)
Detailed information (abstract, keywords, etc)
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CO-D:8 (Time: 10:14 - 10:16)

Title	PCB Component Copper Landing Pad Design Optimization
Author	*Hsiao-Chieh Ma, Yi-Yu Liu (National Taiwan Univ. of Science and Tech., Taiwan)
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CO-D:9 (Time: 10:16 - 10:18)

Title	Flat-Shape Capacitive Sensor of Droplet Contact-Angle for Electrowetting-on-Dielectric Microfluidic Systems
Author	Tomohiro Kodaniguchi, *Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (Univ. of Shiga Prefecture, Japan)
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CO-D:10 (Time: 10:18 - 10:20)

Title	Remote Access Tag Array for Efficient GPU Intra-Cluster Data Sharing
Author	Bo-Wun Cheng, *En-Ming Huang, Chen-Hao Chao, Wei-Fang Sun (National Tsing Hua Univ., Taiwan), Tsung-Tai Yeh (National Yang Ming Chiao Tung Univ., Taiwan), Chun-Yi Lee (National Tsing Hua Univ., Taiwan)
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CO-D:11 (Time: 10:20 - 10:22)

Title	On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC
Author	Bo-Yang Chen, Chang-Yun Liu, Bo-Tsang Huang, *Hung-Ming Chen (NYCU, Taiwan)
Detailed information (abstract, keywords, etc)
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[To Session Table]

Invited Talk III
Time: 13:00 - 14:00, Tuesday, October 25, 2022
Location: Premier Hall (on-site) / Zoom (online)
Chair: Yoshinori Takeuchi (Kindai Univ., Japan)

I3-1 (Time: 13:00 - 14:00)

Title	(Invited Talk) Challenges and Opportunities for New Radio New Type Communications for 5G and Beyond
Author	Jen-Ming Wu (National Tsing Hua Univ./Hon Hai Research Institute, Taiwan)
Page	p. 172
Detailed information (abstract, keywords, etc)

[To Session Table]

Poster Session (Group C)
Time: 14:00 - 15:30, Tuesday, October 25, 2022
Location: Premier Hall (on-site)
Chair: Mahfuzul Islam (Kyoto Univ., Japan)

Best Paper Award
C-1 (Time: 14:00 - 14:02)

Title	DNN-based Accelerator for Intelligent Robotic Arm Control with High-Level Synthesis
Author	*Yu-Chien Chung, Hao-Hsiang Lian, Yong-Lun Xiao, Chih-Tsun Huang, Jing-Jia Liou (National Tsing Hua Univ., Taiwan)
Page	pp. 173 - 177
Detailed information (abstract, keywords, etc)

C-2 (Time: 14:02 - 14:04)

Title	Trotter Based Parallel Processing of Quantum Annealing for FPGA
Author	*Sohei Shimomai, Shinji Kimura (Waseda Univ., Japan)
Page	pp. 178 - 183
Detailed information (abstract, keywords, etc)

C-3 (Time: 14:04 - 14:06)

Title	An Efficient Realization of Power-Root SC Calculations by Inserting Bits
Author	*Yuto Arimura, Shigeru Yamashita (Ritsumeikan Univ., Japan)
Page	pp. 184 - 189
Detailed information (abstract, keywords, etc)

C-4 (Time: 14:06 - 14:08)

Title	An NDA-free Oriented Open PDK Technology and EDA for Small Volume LSI Developments
Author	*Seijiro Moriyama (Anagix, Japan), Tadaaki Tsuchiya, Shingo Ura (Logic Research, Japan)
Page	pp. 190 - 195
Detailed information (abstract, keywords, etc)

C-5 (Time: 14:08 - 14:10)

Title	Development of Diagnosis-based Hardware Trojan Tolerate System
Author	*Takuro Kasai, Masashi Imai (Hirosaki Univ., Japan)
Page	pp. 196 - 197
Detailed information (abstract, keywords, etc)

C-6 (Time: 14:10 - 14:12)

Title	Feasibility Study of DSP Block Mapping Algorithms for FPGAs Utilizing SAT-solver and Top-down ZDD Construction
Author	*Takuya Serizawa, Koyo Shibata (Ritsumeikan Univ., Japan), Takashi Imagawa (Meiji Univ., Japan), Hiroyuki Ochi (Ritsumeikan Univ., Japan)
Page	pp. 198 - 203
Detailed information (abstract, keywords, etc)

C-7 (Time: 14:12 - 14:14)

Title	Evaluating Accuracy of Quantum Circuit Learning via Quantum Circuit Mapping
Author	*Nanao Segawa, Takashi Sato (Kyoto Univ., Japan)
Page	pp. 204 - 209
Detailed information (abstract, keywords, etc)

C-8 (Time: 14:14 - 14:16)

Title	PCB Component Copper Landing Pad Design Optimization
Author	*Hsiao-Chieh Ma, Yi-Yu Liu (National Taiwan Univ. of Science and Tech., Taiwan)
Page	pp. 210 - 215
Detailed information (abstract, keywords, etc)

C-9 (Time: 14:16 - 14:18)

Title	Flat-Shape Capacitive Sensor of Droplet Contact-Angle for Electrowetting-on-Dielectric Microfluidic Systems
Author	Tomohiro Kodaniguchi, *Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine (Univ. of Shiga Prefecture, Japan)
Page	pp. 216 - 220
Detailed information (abstract, keywords, etc)

C-10 (Time: 14:18 - 14:20)

Title	Remote Access Tag Array for Efficient GPU Intra-Cluster Data Sharing
Author	Bo-Wun Cheng, *En-Ming Huang, Chen-Hao Chao, Wei-Fang Sun (National Tsing Hua Univ., Taiwan), Tsung-Tai Yeh (National Yang Ming Chiao Tung Univ., Taiwan), Chun-Yi Lee (National Tsing Hua Univ., Taiwan)
Page	pp. 221 - 222
Detailed information (abstract, keywords, etc)

C-11 (Time: 14:20 - 14:22)

Title	On-Interposer Decoupling Capacitors Placement for Interposer-based 3DIC
Author	Bo-Yang Chen, Chang-Yun Liu, Bo-Tsang Huang, *Hung-Ming Chen (NYCU, Taiwan)
Page	pp. 223 - 228
Detailed information (abstract, keywords, etc)

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Poster Session (Group A)
Time: 14:00 - 15:30, Tuesday, October 25, 2022
Location: Gather (online)
Chair: Shimpei Sato (Shinshu Univ., Japan)

These papers are assigned to session A

AO-D:1 (Time: 14:00 - 14:02)

Title Full Hardware Implementation of RTOS-Based Systems Using General High-Level Synthesizer

Author Takuya Ando, Iori Muguruma, *Yugo Ishii, Nagisa Ishiura (Kwansei Gakuin Univ., Japan), Hiroyuki Tomiyama (Ritsumeikan Univ., Japan), Hiroyuki Kanbara (ASTEM RI/Kyoto, Japan)

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AO-D:2 (Time: 14:02 - 14:04)

Title	SNRoverSDNN: A Metric for Robust CNN-based ROI Selection in Remote Heart Rate Extraction
Author	*Yuta Hitotsuyanagi, Takashi Sato (Kyoto Univ., Japan)
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AO-D:3 (Time: 14:04 - 14:06)

Title	Hardware RTOS Services for Full Hardware Implementation of RTOS-Based Systems
Author	*Hiro Minamiguchi, Masaki Nakahara, Yugo Ishii, Yukino Shinohara, Iori Muguruma, Nagisa Ishiura (Kwansei Gakuin Univ., Japan)
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AO-D:4 (Time: 14:06 - 14:08)

Title	Importance Evaluation Methodology of FFs for Design Optimization of Approximate Computing Circuits
Author	*Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara (Nagoya Univ., Japan)
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AO-D:5 (Time: 14:08 - 14:10)

Title	Bottleneck Channel Routing to Reduce the Area of Analog VLSI
Author	*Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi (Tokyo Inst. of Tech., Japan), Yukichi Todoroki, Makoto Minami (Jedat, Japan)
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AO-D:6 (Time: 14:10 - 14:12)

Title	Binding and Scheduling of 2×3 Mixers for Transport-Free Sample Preparation Using Programmable Microfluidic Devices
Author	*Masataka Hirai, Shigeru Yamashita (Ritsumeikan Univ., Japan), Sudip Roy (Indian Inst. of Tech. (IIT) Roorkee, India), Hiroyuki Tomiyama (Ritsumeikan Univ., Japan)
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AO-D:7 (Time: 14:12 - 14:14)

Title	Segmented DAC Linearity Improvement Algorithm Using Unit Cell Sorted Alternately with Digital Method
Author	*Yi Liu, Anna Kuwana, Shogo Katayama, Xiongyan Li (Gunma Univ., Japan), Atsushi Motozawa (Renesas Electronics, Japan), Haruo Kobayashi (Gunma Univ., Japan)
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AO-D:8 (Time: 14:14 - 14:16)

Title	Aging-Compromised Computing-In-Memory Dot-Product Calculation Technique Through DVFS
Author	*Yu-Guang Chen, Chi-Hsu Wang (National Central Univ., Taiwan), Ing-Chao Lin (National Cheng Kung Univ., Taiwan)
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AO-D:9 (Time: 14:16 - 14:18)

Title	An Implementation of Self-Testable Layout-Level Scan C-element
Author	*Kokoro Yamasaki, Hiroshi Iwata, Ken'ichi Yamaguchi (National Inst. of Tech., Nara College, Japan)
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AO-D:10 (Time: 14:18 - 14:20)

Title	Voice Learning of Reservoir Computing Architecture using Ternary Content Addressable Memory with Individuality
Author	*Sayaka Akiyama, Go Ajiki, Xiangbo Kong, Takeshi Kumaki (Ritsumeikan Univ., Japan)
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AO-D:11 (Time: 14:20 - 14:22)

Title	Formulation of Maximum Independent Set Problem for Simulated Quantum Annealing Machine
Author	*Haruki Nakayama, Yukihide Kohira (Univ. of Aizu, Japan)
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AO-D:12 (Time: 14:22 - 14:24)

Title	Efficient Hardware Architecture for Taylor-Series Expansion Calculation Using Distributed Arithmetic with Term Division
Author	*Xaybandith Hemthavy, Jianglin Wei, Shogo Katayama, Anna Kuwana, Haruo Kobayashi (Gunma Univ., Japan), Kazuyoshi Kubo (Oyama National College of Tech., Japan)
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Closing
Time: 15:30 - 15:40, Tuesday, October 25, 2022
Location: Premier Hall (on-site) / Zoom (online)

SASIMI 2022 The 24th Workshop on Synthesis And System Integration of Mixed Information Technologies Technical Program

Session Schedule

List of papers

SASIMI 2022
The 24th Workshop on Synthesis And System Integration of Mixed Information Technologies
Technical Program