| Title | Future Directions of Silicon Devices |
| Author(s) | *Chenming Hu (Univ. of California, Berkeley) |
| Page(s) | pp. 3 - 4 |
| Detailed information (abstract, keywords, etc) | |
| Title | Ultra-Low Power Design - the Road to Disappearing Electronics |
| Author(s) | *Jan M. Rabaey (Univ. of California, Berkeley) |
| Page(s) | pp. 7 - 12 |
| Detailed information (abstract, keywords, etc) | |
| Title | Model to Hardware Closure for nm Generation Technologies |
| Author(s) | *Sani R. Nassif (IBM) |
| Page(s) | pp. 15 - 20 |
| Detailed information (abstract, keywords, etc) | |
| Title | Leakage Power Considerations for Processor Array-Based Vision Systems |
| Author(s) | *Jason Schlessman, Wayne Wolf (Princeton Univ.) |
| Page(s) | pp. 23 - 26 |
| Detailed information (abstract, keywords, etc) | |
| Title | A ROBDD-Based Generalized Nodal Control Scheme for Standby Leakage Power Reduction |
| Author(s) | Hsinwei Chou (Univ. of Wisconsin-Madison), *Charlie Chung-Ping Chen (National Taiwan Univ.) |
| Page(s) | pp. 27 - 33 |
| Detailed information (abstract, keywords, etc) | |
| Title | Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer |
| Author(s) | *Satoshi Komatsu, Masahiro Fujita (Univ. of Tokyo) |
| Page(s) | pp. 34 - 40 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Analytical Power Model for Synthesized Register Files Considering Address Dependencies |
| Author(s) | *Akihiko Higuchi, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.) |
| Page(s) | pp. 41 - 46 |
| Detailed information (abstract, keywords, etc) | |
| Title | Energy-Aware Dynamic Task Scheduling Applied to a Real-Time Multimedia Application on an Xscale Board |
| Author(s) | Chantal Ykman-Couvreur, Francky Catthoor, Johan Vounckx, Andy Folens, Filip Louagie, *Rudy Lauwereins (IMEC) |
| Page(s) | pp. 47 - 54 |
| Detailed information (abstract, keywords, etc) | |
| Title | LSI Power Network Analysis with On-chip Wire Inductance |
| Author(s) | *Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera (Kyoto Univ.) |
| Page(s) | pp. 55 - 60 |
| Detailed information (abstract, keywords, etc) | |
| Title | Power Supply Noise Reduction with Design for Manufacturability |
| Author(s) | *Hiroyuki Tsujikawa, Kenji Shimazaki, Shozo Hirano, Kazuhiro Sato, Masanori Hirofuji, Junichi Shimada, Mitsumi Ito, Kiyohito Mukai (Matsushita Electric Industrial Co., Ltd.) |
| Page(s) | pp. 61 - 65 |
| Detailed information (abstract, keywords, etc) | |
| Title | An IR-Drop Minimization by Optimizing Number and Location of Power Supply Pads |
| Author(s) | *Takashi Sato (Kyoto Univ.), Masanori Hashimoto (Osaka Univ.), Hidetoshi Onodera (Kyoto Univ.) |
| Page(s) | pp. 66 - 72 |
| Detailed information (abstract, keywords, etc) | |
| Title | High Speed and Low Energy Lateral BJT-CMOS Inverter |
| Author(s) | *Toshiro Akino (Kinki Univ.) |
| Page(s) | pp. 73 - 77 |
| Detailed information (abstract, keywords, etc) | |
| Title | Topology-Oriented Design of Current Mirrors Using Evolutionary Graph Generation System |
| Author(s) | *Masanori Natsui, Naofumi Homma, Takafumi Aoki (Tohoku Univ.), Tatsuo Higuchi (Tohoku Inst. of Tech.) |
| Page(s) | pp. 78 - 84 |
| Detailed information (abstract, keywords, etc) | |
| Title | MOSFET Layout Design for Electrical Performance Improvement |
| Author(s) | *Philip Beow Yew Tan (Silterra Malaysia Sdn. Bhd. & Univ. Science Malaysia), Albert Victor Kordesch (Silterra Malaysia Sdn. Bhd.), Othman Sidek (Univ. Science Malaysia) |
| Page(s) | pp. 85 - 89 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Thermal-aware Sigma-Delta Modulator for CMOS Monolithic Temperature Sensors |
| Author(s) | *Suhow Wu, Herming Chiueh (National Chiao Tung Univ.) |
| Page(s) | pp. 90 - 94 |
| Detailed information (abstract, keywords, etc) | |
| Title | Real-Time Segmentation of Large-Scale Images by Pipeline Processing with Small-Size Cell-Network |
| Author(s) | *Hidekazu Adachi, Takashi Morimoto, Osamu Kiriyama, Zhaomin Zhu, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.) |
| Page(s) | pp. 95 - 102 |
| Detailed information (abstract, keywords, etc) | |
| Title | System on Programmable Chip Platform Based Design of JPEG-2000 Entropy Coder |
| Author(s) | Riad Benmouhoub, Imed Aouadi, *Omar Hammami (ENSTA) |
| Page(s) | pp. 103 - 106 |
| Detailed information (abstract, keywords, etc) | |
| Title | Efficient Hardware Architecture of a New Simple Public-Key Cryptosystem for Real-Time Data Processing |
| Author(s) | *Chengnan Jin, Nobuhiro Doi (Waseda Univ.), Hatsukazu Tanaka (Kobe Univ.), Shigeki Imai (Sharp Co.), Shinji Kimura (Waseda Univ.) |
| Page(s) | pp. 107 - 112 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Parameterized On-Chip-Bus-Compliant FDWT/IDWT Accelerator IP Generator |
| Author(s) | Chih-Chun Chang, *Youn-Long Lin (National Tsing Hua Univ.) |
| Page(s) | pp. 113 - 120 |
| Detailed information (abstract, keywords, etc) | |
| Title | VLSI Implementation of a 3D Sound Movement System |
| Author(s) | *Nobuyuki Iwanaga, Takao Onoye (Osaka Univ.), Wataru Kobayashi, Kazuhiko Furuya (Arnis Sound Technologies, Co., Ltd.), Isao Shirakawa (Univ. of Hyogo) |
| Page(s) | pp. 121 - 125 |
| Detailed information (abstract, keywords, etc) | |
| Title | Nanodevices Beyond Silicon: Device and Circuit Implications |
| Author(s) | *H.-S. Philip Wong (Stanford Univ.) |
| Page(s) | pp. 129 - 133 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Application Specific Network-on-Chip (ASNOC) Design with Binary Tree Architecture |
| Author(s) | *Yuan-Long Jeang, Win-Hsien Huang, Wei-Feng Fang, Jain-Zhou Huang, Nan-Long Tsai, Chien-Cheng Ou (National Kaohsiung Univ. of Applied Sciences) |
| Page(s) | pp. 137 - 142 |
| Detailed information (abstract, keywords, etc) | |
| Title | The Design and Implementation of a Multimedia Coprocessor for ARM7 Microprocessors |
| Author(s) | *Tse-Chen Yeh, Ing-Jer Huang (National Sun Yat-Sen Univ.) |
| Page(s) | pp. 143 - 147 |
| Detailed information (abstract, keywords, etc) | |
| Title | ParSyC: An Efficient SystemC Parser |
| Author(s) | *Görschwin Fey, Daniel Große, Tim Cassens, Christian Genz, Tim Warode, Rolf Drechsler (Univ. of Bremen) |
| Page(s) | pp. 148 - 154 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Simulation Environment for Asynchronous Codesign |
| Author(s) | *Satoshi Tsutsumi, Hideharu Amano (Keio Univ.) |
| Page(s) | pp. 155 - 161 |
| Detailed information (abstract, keywords, etc) | |
| Title | Extracting Structural and Communication Information of SystemC Descriptions |
| Author(s) | *Fábio Prudente, Edna Barros (Univ. Federal de Pernambuco) |
| Page(s) | pp. 162 - 168 |
| Detailed information (abstract, keywords, etc) | |
| Title | Software Execution Time Back-annotation Method for High Speed Hardware-Software Co-simulation |
| Author(s) | *Michiaki Muraoka, Noriyoshi Itoh, Rafael K. Morizawa, Hiroyuki Yamashita , Takao Shinsha (STARC) |
| Page(s) | pp. 169 - 175 |
| Detailed information (abstract, keywords, etc) | |
| Title | Wire Length Distribution of SoC considering Macro Block Shapes |
| Author(s) | *Takanori Kyogoku, Hidenari Nakashima, Junpei Inoue, Naohiro Takagi, Hiyouko Shinoki, Kenichi Okada , Kazuya Masu (Tokyo Inst. of Tech.) |
| Page(s) | pp. 176 - 180 |
| Detailed information (abstract, keywords, etc) | |
| Title | Interconnect Synthesis for Lithography and Manufacturability in Deep Submicron Design |
| Author(s) | Sameer Pujari (SUNY Binghamton ECE), Ryon M. Smey (SUNY Binghamton CSD/InternetCAD), Tan Yan (Univ. of Kitakyushu), Hannibal H. Madden (AVS), *Patrick H. Madden (Univ. of Kitakyushu) |
| Page(s) | pp. 181 - 188 |
| Detailed information (abstract, keywords, etc) | |
| Title | Compact Modeling and Experimental Verification of Substrate Resistance in Lightly Doped Substrates |
| Author(s) | Hai Lan, Tze Wee Chen, Chi On Chui, *Robert W. Dutton (Stanford Univ.) |
| Page(s) | pp. 189 - 195 |
| Detailed information (abstract, keywords, etc) | |
| Title | Realization of Digital Noise Emulator for Characterization of Systems Exposed to Substrate Noise |
| Author(s) | Yi-Chang Lu, Jae Wook Kim (Stanford Univ.), *Nobuhiko Nakano (Keio Univ.), David Colleran (Stanford Univ.), Patrick Yue (Carnegie Mellon Univ.), Robert W. Dutton (Stanford Univ.) |
| Page(s) | pp. 196 - 203 |
| Detailed information (abstract, keywords, etc) | |
| Title | Passive-Assured Rational Function Approach for Compact Modeling of On-chip Passive Components |
| Author(s) | *Zuochang Ye, Zhiping Yu (Tsinghua Univ.) |
| Page(s) | pp. 204 - 208 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Analytical Phase Response Model for 3-stage Ring Oscillators |
| Author(s) | *Jaijeet Roychowdhury (Univ. of Minnesota) |
| Page(s) | pp. 209 - 213 |
| Detailed information (abstract, keywords, etc) | |
| Title | Statistical Analysis of Clock Skew Variation |
| Author(s) | *Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera (Kyoto Univ.) |
| Page(s) | pp. 214 - 219 |
| Detailed information (abstract, keywords, etc) | |
| Title | Statistical Timing Analysis with Global Variations and Path Reconvergence |
| Author(s) | Lizheng Zhang, Yuhen Hu (Univ. of Wisconsin-Madison), *Charlie Chung-Ping Chen (National Taiwan Univ.) |
| Page(s) | pp. 220 - 227 |
| Detailed information (abstract, keywords, etc) | |
| Title | SIRE/M: A Homogeneous Intermediate Format for VHDL-AMS Mixed Signal Simulation |
| Author(s) | *Hamid Reza Ghasemi, Zainalabedin Navabi (Univ. of Tehran) |
| Page(s) | pp. 228 - 234 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Layout-Aware Circuit Sizing Model Using Parametric Analysis |
| Author(s) | *I-Lun Tseng, Adam Postula (Univ. of Queensland) |
| Page(s) | pp. 235 - 240 |
| Detailed information (abstract, keywords, etc) | |
| Title | LARTTE: A Posynomial-Based Lagrangian Relaxation Tuning Tool for Fast and Effective Gate-Sizing and Multiple Vt Assignment |
| Author(s) | Hsinwei Chou (Univ. of Wisconsin-Madison), Yu-Hao Wang (Incentia Design Systems), *Charlie Chung-Ping Chen (National Taiwan Univ.) |
| Page(s) | pp. 241 - 248 |
| Detailed information (abstract, keywords, etc) | |
| Title | A DSP Core for Portable Multimedia Application |
| Author(s) | *Chein-Wei Jen (SoC Technology Center, ITRI, Taiwan) |
| Page(s) | pp. 251 - 252 |
| Title | Zero Overhead Loop Techniques for Application Specific Instruction-set Processors |
| Author(s) | *Shinsuke Kobayashi (Univ. of Tokyo), Kentaro Mita, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
| Page(s) | pp. 255 - 261 |
| Detailed information (abstract, keywords, etc) | |
| Title | Buffering Hardware Nested Loop of Parameterized and Embedded DSP Core |
| Author(s) | *Ya-Lan Tsao, Wei-Hao Chen, Shyh-Jye Jou (National Central Univ.) |
| Page(s) | pp. 262 - 265 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Methodology for Automated Test Generation for LISA Processor Models |
| Author(s) | *Olaf Lüthje (CoWare, Inc.) |
| Page(s) | pp. 266 - 273 |
| Detailed information (abstract, keywords, etc) | |
| Title | Design Understanding by Automatic Property Generation |
| Author(s) | Rolf Drechsler, *Görschwin Fey (Univ. of Bremen) |
| Page(s) | pp. 274 - 281 |
| Detailed information (abstract, keywords, etc) | |
| Title | Behavioral Model Construction for Formal Verification of Advanced On-chip Bus Protocols |
| Author(s) | *Yosuke Kakiuchi (Osaka Univ.), Akira Kitajima (Osaka Electro-Communication Univ.), Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.) |
| Page(s) | pp. 282 - 289 |
| Detailed information (abstract, keywords, etc) | |
| Title | On Debugging Assistance in Assertion-Based Verification |
| Author(s) | *Bao-Ren Huang, Tzung-Jr Tsai, Chien-Nan Liu (National Central Univ.) |
| Page(s) | pp. 290 - 295 |
| Detailed information (abstract, keywords, etc) | |
| Title | Matlab based Environment for Designing DSP Systems using IP Blocks |
| Author(s) | Nacer-Eddine Zergainoh, Katalin Popovici, *Ahmed Amine Jerraya (TIMA Laboratory), Pascal Urard (STMicroelectronics) |
| Page(s) | pp. 296 - 302 |
| Detailed information (abstract, keywords, etc) | |
| Title | Asynchronous Datapath Synthesis Enhancing Graceful Degradation for Delay Faults |
| Author(s) | *Koji Ohashi, Mineo Kaneko (JAIST) |
| Page(s) | pp. 303 - 309 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Behavioral Synthesis Method Considering Complex Operations |
| Author(s) | *Tsuyoshi Sadakata, Yusuke Matsunaga (Kyushu Univ.) |
| Page(s) | pp. 310 - 314 |
| Detailed information (abstract, keywords, etc) | |
| Title | Customizable Framework for Arithmetic Synthesis |
| Author(s) | *Taeko Matsunaga (Fukuoka Industry, Science & Technology Foundation), Yusuke Matsunaga (Kyushu Univ.) |
| Page(s) | pp. 315 - 318 |
| Detailed information (abstract, keywords, etc) | |
| Title | Arithmetic Description Language and Its Application to Parallel Multiplier Design |
| Author(s) | *Naofumi Homma, Kazuya Ishida, Takafumi Aoki (Tohoku Univ.), Tatsuo Higuchi (Tohoku Inst. of Tech.) |
| Page(s) | pp. 319 - 326 |
| Detailed information (abstract, keywords, etc) | |
| Title | Area efficient Wave-Pipelined Adder Using Redundant Binary Encoding |
| Author(s) | *Tatsuya Yamamoto, Kiyofumi Tanaka (JAIST) |
| Page(s) | pp. 327 - 332 |
| Detailed information (abstract, keywords, etc) | |
| Title | Reduction on the Usage of Intermediate Registers for Pipelined Circuits |
| Author(s) | *Bakhtiar Affendi Rosdi, Atsushi Takahashi (Tokyo Inst. of Tech.) |
| Page(s) | pp. 333 - 338 |
| Detailed information (abstract, keywords, etc) | |
| Title | Error Diagnosis Technique Based on Boolean Resubstitution |
| Author(s) | Toshifumi Sugane, *Ryosuke Arai, Takayuki Iida, Hiroshi Inoue, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) |
| Page(s) | pp. 339 - 344 |
| Detailed information (abstract, keywords, etc) | |
| Title | Extraction of Subcircuits for Incremental Synthesis Based on Error Diagnosis |
| Author(s) | *Takayuki Iida, Toshifumi Sugane, Takahiro Iwasaki, Hiroshi Inoue, Nobutaka Kuroki, Masahiro Numa, Keisuke Yamamoto (Kobe Univ.) |
| Page(s) | pp. 345 - 350 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Patchwork-like Partitioning Method for Engineering Change Orders in Redesign of High Performance LSIs |
| Author(s) | *Yuichi Nakamura, Ko Yoshikawa (NEC), Takeshi Yoshimura (Waseda Univ.) |
| Page(s) | pp. 351 - 356 |
| Detailed information (abstract, keywords, etc) | |
| Title | Logic Optimization Method after Technology Mapping |
| Author(s) | *Ko Yoshikawa, Yuichi Nakamura (NEC), Kyo Akashi (NEC Informatec Systems), Takeshi Yoshimura (Waseda Univ.) |
| Page(s) | pp. 357 - 362 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Feed-Foreward Dynamic Voltage Frequency Management by Workload Prediction for a Low Power Motion Video Compression |
| Author(s) | *Masahiko Yoshimoto (Kobe Univ.), Kentaro Kawakami (Kanazawa Univ.) |
| Page(s) | pp. 365 - 370 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Vision towards an Ambient Intelligent Environment and the Associated System Level Design Challenges |
| Author(s) | *Rudy Lauwereins (IMEC) |
| Page(s) | pp. 373 - 375 |
| Detailed information (abstract, keywords, etc) | |
| Title | Analog Topological Placement with Symmetry Constraints Using a O(n loglog n) Evaluation Algorithm |
| Author(s) | Karthik Krishnamoorthy, Sarat C. Maruvada, *Florin Balasa (Univ. of Illinois at Chicago) |
| Page(s) | pp. 379 - 386 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Detailed Placement Method for Structured Devices with Multiple Resources |
| Author(s) | *Yoshihiro Ono, Takumi Okamoto (NEC) |
| Page(s) | pp. 387 - 394 |
| Detailed information (abstract, keywords, etc) | |
| Title | Floorplan Design for 3-D ICs |
| Author(s) | Lei Cheng, Liang Deng, *Martin D.F. Wong (Univ. of Illinois at Urbana-Champaign) |
| Page(s) | pp. 395 - 401 |
| Detailed information (abstract, keywords, etc) | |
| Title | Minimization in the Number of Empty Rooms on Floorplan by Dissection Line Merge |
| Author(s) | *Chikaaki Kodama, Kunihiro Fujiyoshi (Tokyo Univ. of Agri. and Tech.) |
| Page(s) | pp. 402 - 407 |
| Detailed information (abstract, keywords, etc) | |
| Title | Area-Array I/O Clustering in Design Cost and Performance Optimization |
| Author(s) | *Hung-Ming Chen (National Chiao Tung Univ.), I-Min Liu (Cadence Design Systems), Martin D.F. Wong (Univ. of Illinois at Urbana-Champaign) |
| Page(s) | pp. 408 - 413 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Integrated Approach of Variable Ordering and Logic Mapping into LUT-Array-Based PLD |
| Author(s) | *Tomonori Izumi, Sinichi Kouyama (Kyoto Univ.), Hideyuki Ito (NTT Co.), Yukihiro Nakamura (Kyoto Univ.) |
| Page(s) | pp. 414 - 421 |
| Detailed information (abstract, keywords, etc) | |
| Title | Application of LUT Cascades to Numerical Function Generators |
| Author(s) | Tsutomu Sasao (Kyushu Inst. of Tech.), *Jon T. Butler (Naval Postgraduate School), Marc D. Riedel (California Inst. of Tech.) |
| Page(s) | pp. 422 - 429 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Design Algorithm for Sequential Circuits using LUT Rings |
| Author(s) | *Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (Kyushu Inst. of Tech.) |
| Page(s) | pp. 430 - 437 |
| Detailed information (abstract, keywords, etc) | |
| Title | Scannable Flip-Flops for Test of 3D Asynchronous Finite State Machine |
| Author(s) | *Soo-Hyun Kim (Gwangju Inst. of Science and Tech.), Ho-Yong Choi (Chungbuk National Univ.), Kiseon Kim (Gwangju Inst. of Science and Tech.) |
| Page(s) | pp. 438 - 442 |
| Detailed information (abstract, keywords, etc) | |
| Title | Cost Functions for the Design of Dynamically Reconfigurable Processor Architectures |
| Author(s) | *Tobias Oppold, Thomas Schweizer, Tommy Kuhn, Wolfgang Rosenstiel (Univ. of Tuebingen) |
| Page(s) | pp. 443 - 450 |
| Detailed information (abstract, keywords, etc) | |
| Title | Dynamic Reconfigurable RF Circuit Design |
| Author(s) | *Kenichi Okada, Yoshiaki Yoshihara, Hirotaka Sugawara, Kazuya Masu (Tokyo Inst. of Tech.) |
| Page(s) | pp. 451 - 457 |
| Detailed information (abstract, keywords, etc) | |
| Title | Asynchronous Dynamically Reconfigurable Logic LSIs Suitable For Technology Scaling |
| Author(s) | *Hideyuki Ito, Ryusuke Konishi, Hiroshi Nakada, Yuichi Okuyama, Akira Nagoya (NTT Co.), Tomonori Izumi, Yukihiro Nakamura (Kyoto Univ.) |
| Page(s) | pp. 458 - 465 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Optimization Method in Floating-point to Fixed-point Conversion using Positive and Negative Error Analysis and Sharing of Operations |
| Author(s) | *Nobuhiro Doi (Waseda Univ.), Takashi Horiyama (Kyoto Univ.), Masaki Nakanishi (NAIST), Shinji Kimura (Waseda Univ.) |
| Page(s) | pp. 466 - 471 |
| Detailed information (abstract, keywords, etc) | |
| Title | Reusing Cache for Real-Time Memory Address Trace Compression |
| Author(s) | Ing-Jer Huang, *Chung-Fu Kao (National Sun Yat-Sen Univ.) |
| Page(s) | pp. 472 - 476 |
| Detailed information (abstract, keywords, etc) | |
| Title | Dynamic Voltage and Frequency Scaling Techniques for Heterogeneous Multi-Processor Architecture in Future Nanometer Technologies |
| Author(s) | *Yutetsu Takatsukasa, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.) |
| Page(s) | pp. 477 - 482 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Sub-Operation Parallelism Optimization Algorithm in HW/SW Partitioning for SIMD Processor Cores |
| Author(s) | *Hideki Kawazu, Jumpei Uchida, Yuichiro Miyaoka (Waseda Univ.), Nozomu Togawa (Univ. of Kitakyushu), Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) |
| Page(s) | pp. 483 - 490 |
| Detailed information (abstract, keywords, etc) | |
| Title | Highly Efficient Switch Architecture Based on Banked Memory with Multiple Ports |
| Author(s) | *Takayuki Fujii (Hiroshima Univ.), Kazuhiko Kobayashi (Hiroshima City Univ.), Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.), Tetsuo Hironaka (Hiroshima City Univ.) |
| Page(s) | pp. 491 - 498 |
| Detailed information (abstract, keywords, etc) | |
| Title | Life at the End of CMOS Scaling |
| Author(s) | Organizer & Moderator: Rob Rutenbar (Carnegie Mellon Univ.), Panelists: Sani Nassif (IBM), Jan Rabaey (Univ. of California, Berkeley), H.-S. Philip Wong (Stanford Univ.), Kazuo Yano (Hitachi Ltd.) |
| Page(s) | p. 501 |
| Detailed information (abstract, keywords, etc) | |