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International Workshop on
DIELECTRIC THIN FILMS FOR FUTURE ULSI DEVICES: SCIENCE AND TECHNOLOGY

Session S3  Characterization
Time: 9:00 - 10:30 Thursday, November 6, 2008
Chairs: Kazuyoshi Torii (Hitachi, Japan), Sungjoo Lee (National Univ. of Singapore, Singapore)

S3-1 (Time: 9:00 - 9:30)
Title(Invited Paper) What Can We Learn from Structural Characterization of Metal-Oxide Gate Stacks?
Author*Matt Copel (IBM, United States)
Pagepp. 61 - 62

S3-2 (Time: 9:30 - 9:50)
TitleElectrical Properties of Ge3N4/Ge Gate Stacks Fabricated Using High-Density Plasma Nitridation
Author*Gaku Okamoto, Katsuhiro Kutsuki, Takuji Hosoi, Takayoshi Shimura, Heiji Watanabe (Osaka Univ., Japan)
Pagepp. 63 - 64

S3-3 (Time: 9:50 - 10:10)
TitleUnderstanding of Carrier Transport in MOS Device with High-k Gate Dielectric: An Electron-Beam-Induced Current Study of Leakage Sites
Author*Jun Chen, Takashi Sekiguchi, Masami Takase, Naoki Fukata, Toyohiro Chikyow (National Inst. for Materials Science, Japan), Ryu Hasunuma, Kikuo Yamabe (Univ. of Tsukuba, Japan), Motoyuki Sato, Yasuo Nara (Selete, Japan), Keisaku Yamada (Waseda Univ., Japan)
Pagepp. 65 - 66

S3-4 (Time: 10:10 - 10:30)
TitlePr-Si-O Gate Stack with an Ultrathin Interfacial Layer Grown by MOCVD and PDA under Low O2 Partial Pressure
Author*Yoshishige Tsuchiya (Tokyo Inst. of Tech./Univ. of Southampton, Japan), Ryosuke Furukawa (Tokyo Inst. of Tech./Musashi Inst. of Tech., Japan), Koji Kitamura, Hiroshi Nohira (Musashi Inst. of Tech., Japan), Shunri Oda (Tokyo Inst. of Tech., Japan)
Pagepp. 67 - 68