| Title | A Design of Low-Power Frequency Synthesizer for GPS Application using Multiple Reference Clocks in 0.18μm CMOS Technology |
| Author | *YoungGun Pu (Konkuk University, Republic of Korea), Jun-Gi Jo, Changsik Yoo (Hanyang University, Republic of Korea), Dojin Park, Seong-Eon Park, Suk-Joong Lee (CoreLogic Inc, Republic of Korea), Kang-Yoon Lee (Konkuk University, Republic of Korea) |
| Page | pp. 433 - 436 |
| Keyword | frequency synthesizer, low-power, GPS, phase noise |
| Abstract | This paper presents a low power CMOS frequency synthesizer for GPS application that can support multiple reference clocks. The frequency synthesizer has fractional-N phase locked loop structure with sigma-delta modulator to allow multiple reference clock frequencies. The measured phase noise is -126dBc/Hz at 1MHz offset from the carrier. This chip is fabricated with 0.18um CMOS technology, and the die area of the frequency synthesizer is 1.1mm x 1.05mm. The power consumption is 18mW at 1.8V supply voltage. |
| Title | A 0.18um CMOS Current Reused Low-Noise Amplifier with Gain Compensated for Ultra-Wideband Wireless Receiver |
| Author | Zhe-Yang Huang, *Yeh-Tai Hung (National Chiao Tung University, Taiwan), Che-Cheng Huang (RealTek, Taiwan), Meng-Ping Chen (National Tsing Hua University, Taiwan) |
| Page | pp. 437 - 440 |
| Keyword | RFIC, UWB, LNA, Low-Noise Amplifier, Current Reused |
| Abstract | A current reused low-noise amplifier (LNA) with gain compensated to extend the bandwidth and is designed for ultra-wideband (UWB) wireless receiver. The design consists of two cascode common-source amplifier and an output buffer which is implemented in 0.18um RF CMOS process. The LNA gives 13.1dB gain; 9.1GHz 3dB bandwidth (3.1-12.2GHz) while consuming 13.9mW through a 1.8V supply. Over the 3.1GHz - 10.6GHz frequency band, a minimum noise figure of 2.7dB and input return loss lower than -8.7dB have been achieved. |
| Title | Design Trade Off on Noise Figure and Chip Area in Multi-Stage Low-Noise Amplifier for Ultra-Wideband Wireless Receiver |
| Author | *Zhe-Yang Huang (National Chiao Tung University, Taiwan), Che-Cheng Huang (RealTek, Taiwan), Yeh-Tai Hung (National Chiao Tung University, Taiwan), Meng-Ping Chen (National Tsing Hua University, Taiwan) |
| Page | pp. 441 - 444 |
| Keyword | RFIC, UWB, LNA, Low-Noise Amplifier, Muli-Stage |
| Abstract | A multi-stage low-noise amplifier (LNA) with LC-tank load to extend the bandwidth is designed for ultra-wideband (UWB) wireless receiver. The design consists of three LC-tank cascode amplifier and one output buffer and is implemented in 0.18um RF CMOS process. The trade off on noise figure and chip area in low-noise amplifier design is discussed. The two LNA (LC and Res) gives 14.5dB gain; 7.2GHz and 7.0GHz 3dB bandwidth (3.1-10.3GHz and 3.1-10.1GHz) while consuming 22.8mW and 23.8mW through a 1.5V supply. Over the 3.1GHz - 10.3GHz and 3.1GHz-10.1GHz frequency band, a minimum noise figure of 2.6dB and 6.3dB and input return loss lower than -8.8dB and -6.8dB have been achieved. |
| Title | Combinational Logic Computing for Single-Flux Quantum Circuits with Asynchronous Collision-Based Fusion Gates |
| Author | *Kazuhito Yamada, Tetsuya Asai, Yoshihito Amemiya (Hokkaido University, Japan) |
| Page | pp. 445 - 448 |
| Keyword | single-flux quantum, combinational logic, collision-based computing, asynchronous circuits, fusion gates |
| Abstract | In collision-based (fusion) computing, information propagates in an impulse form; i.e., existence of a mobile object, particle or self-localization is represented by a spatial impulse on the abstract media. Unlike other electronic devices, a medium for signals in SFQ circuits is a pulse of a fluxoid quantum, therefore SFQ circuits are able to implement the collision-based computers more simply. |