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The 23rd International Technical Conference on Circuits/Systems, Computers and Communications

Session F2  Graph, Petri Nets & Algorithms 2
Time: 13:30 - 15:00 Monday, July 7, 2008
Location: 8F 803 Room
Chairs: Shigemasa Takai (Kyoto Institute of Technology, Japan), Pornchai Supnithi (King Mongkut's Institute of Technology Ladkrabang)

F2-1 (Time: 13:30 - 13:48)
TitleDelay Time Estimation for Petri Net Models of Signaling Pathways Based on Experimental Data
Author*Yoshimasa Miwa, Kanji Hioka (Yamaguchi University, Japan), Chen Li (University of Tokyo, Japan), Hiroshi Matsuno (Yamaguchi University, Japan), Satoru Miyano (University of Tokyo, Japan)
Pagepp. 297 - 300
Keywordsignaling pathway, Petri net, delay time estimation, simulation
AbstractIn this paper, we propose a delay time estimation algorithm for Petri net models of signaling pathways based on experimental data. Firstly, we model signaling pathways (we use the example of ErbB4 receptor signaling pathway) with discrete Petri nets. Then, we propose a delay time estimation algorithm for Petri net models with experimental data, and assign estimated delay times to a model to be run on the simulation tool Cell Illustrator 3.0. Finally, we verify the simulation result by comparing with the experimental data and evaluate the performance of the estimation algorithm.

F2-2 (Time: 13:48 - 14:06)
TitleEdge Coloring Problem of Graph Theory Considering Interference on Network Coding
Author*Hiroshi Tamura (Niigata Institute of Technology, Japan), Masakazu Sengoku (Niigata University, Japan), Shoji Shinoda (Chuo University, Japan)
Pagepp. 301 - 304
KeywordMultihop wireless network, network coding, edge coloring, graph theory
AbstractMultihop wireless networks consist of mobile terminals with personal communication devices. Each terminal can receive a message from a terminal and send it to the other terminal. If a terminal can not communicate the other terminal that sends data directly, some terminals relay the data. Network coding is a new architecture for wireless network and various applications using this architecture are expected. In this paper, we expand the previous coloring problem and propose a new coloring problem including the architecture.

F2-3 (Time: 14:06 - 14:24)
TitleA Method of Generating Feature Graph for Handwritten Character Recognition of Japanese Historical Documents
Author*Masaki Hayashi (Graduate School of Education, Yamaguchi University, Japan), Shuichi Nishida (Graduate School of Education, Yamaguchi University, Japan), Mitsuru Nakata, Qi-Wei Ge, Makoto Yoshimura (Yamaguchi University, Japan)
Pagepp. 305 - 308
Keywordfeature graph, Handwritten Character Recognition, clustring, curve vertices
AbstractIn this paper, we propose a method of generating feature graphs for recognition of handwritten characters in Japanese historical documents. The feature graph represents structure of a handwritten character. In our method, the feature graph is generated as follows: (1) a rough graph is generated by thinning, clustering and other processes; (2) connections between vertices are retrieved with edge trace; (3) the curve vertices, which express curved strokes of a character, are added into the graph; (4) relative locations between vertices are calculated.

F2-4 (Time: 14:24 - 14:42)
TitleOn Verification and Application of Behavioral Inheritance for Parallel Synchronized Interworkflows
AuthorShingo Yamaguchi, *Tetsushi Narui, Qi-Wei Ge, Minoru Tanaka (Yamaguchi University, Japan)
Pagepp. 309 - 312
Keywordinterworkflow, WF-net, branching bisimirality, behavioral inheritance
AbstractBehavioral inheritance guarantees that interworkflow can be substituted for workflow. Nevertheless it may happen that the behavior is not inherited. Behavioral inheritance can be verified by comparing the reachability graphs of the WF-nets representing interworkflow and workflow. However this verification method is limited to small interworkflows due to the complexity of the state-space explosion. we propose a condition to verify behavioral inheritance of Parallel synchronized interworkflows.

F2-5 (Time: 14:42 - 15:00)
TitleA Linear Time Algorithm for Tri-connectivity Augmentation of Bi-connected Graphs with Upper Bounds on Vertex-Degree Increase
Author*Toshiya Mashima (Hiroshima International University, Japan), Satoshi Taoka, Toshimasa Watanabe (Hiroshima University, Japan)
Pagepp. 313 - 316
Keywordgraph, algorithm, connectivity, augmentation problem, degree constraints
AbstractThe $3$-vertex-connectivity augmentation problem of a graph with degree constraints, $3$VCA-DC, is defined as follows: ``Given an undirected graph $G=(V,E)$, and an upper bound $b(v)\in Z^+\cup\{\infty\}$ on vertex-degree increase for each $v\in V$, find a smallest set $E'$ of edges such that $(V,E\cup E')$ is 3-vertex-connected and such that vertex-degree increase of each $v\in V$ by the addition of $E'$ to $G$ is at most $b(v)$, where $Z^+$ is the set of nonnegative integers.''In this paper we show that checking the existence of a feasible solution and finding an optimum solution to $3$VCA-DC for any bi-connected graph $G$ can be done in $O(|V|+|E|)$ time.