| Title | Multiple-Valued Logic Clock Converter Networks |
| Author | *Ali Massoud Haidar, Nawar El Ahdab (Beirut Arab University, Lebanon), Hiroyuki Shirahama (Ehime University, Japan), Ali Alaeldine (Grand Ecole D’Ingénieurs Généralistes en Electronique, Informatique, Télécoms et Réseaux, France) |
| Page | pp. 589 - 592 |
| Keyword | neural network, digital systems, binary systems, multiple-valued logic, clock wave transformer |
| Abstract | novel multiple-valued logic clock converters using artificial neural network are proposed. Based on a set of novel neural clock base converters, an essential part of the creative solution to the multiple-valued logic dual-clock or multi-clock circuit synchronization problem is presented in this paper. The multiple-valued logic neuron clock converters are planned to be useful in the multiple-valued logic neural central processing unit. The novel neural networks of the multiple-valued logic clock converters show numerous functionality features combined with design simplicity. All the converters make advantage of the logic oriented neural network mathematical tools and parallelism concepts allowing fast and simple systematic analysis. The simulation outcomes presented, pave the way toward new, stable, high speed, revolutionary neural multiple-valued logic processors. |
| Title | A Novel Neural Network Ternary Arithmetic Logic Unit |
| Author | *Ali Massoud Haidar, Mohammad Jad Hamdan, Mohammad Backer Rashid, Hassan A. Hamieh, Ahmad A. Issa (Beirut Arab University, Lebanon), Abdallah Kassem (Notre Dame University, Lebanon) |
| Page | pp. 593 - 596 |
| Keyword | Neural Networks, Logic theory, Multiple valued logic, ALU |
| Abstract | In this paper we introduce a new set of ternary neural networks to realize a novel Ternary Arithmetic Logic Unit (TALU). All the neurons take advantage of the Logic Oriented neural network mathematical tools and parallelism concepts allowing fast and simple systematic analysis. The simulation results, done using MATLAB Simulink, demonstrate the feasibility, functionality and the correctness of the neural networks designed. |
| Title | Low-Power CMOS CNN Cell and its Application to an Oscillatory CNN |
| Author | *Hisashi Tanaka, Koichi Tanno, Hiroki Tamura, Kenji Murao (University of Miyazaki, Japan) |
| Page | pp. 597 - 600 |
| Keyword | cellular neural networks, low-power, low-voltage, OTA |
| Abstract | In this paper, we propose a low-power OTA for CMOS cellular neural networks (CNN) cell. The OTA use MOSFETs operating in the weak inversion region. The transconductance can be changed by changing the external bias voltage. From the results of HSPICE simulation, the power consumption of the proposed OTA is less than 3.5 micro-watts with 1.2 V power supply. As an application of the proposed OTA, an oscillatory CNN circuit using two CNN cells with the proposed OTA is presented. |
| Title | Adaptive Noise Reduction Filter for Speech Using Cascaded Sandglass-type Neural Network |
| Author | *Hiroki Yoshimura, Tadaaki Shimizu (Tottori University, Japan), Toshie Matumura (Nara National College, Japan), Masaya Kimoto (Tottori University, Japan), Naoki Isu (Mie University, Japan) |
| Page | pp. 605 - 608 |
| Keyword | Neural Network, Speech Signal, Adaptive Filter, Noise Reduction, Sandglass-type |
| Abstract | In this study, we developed a new adaptive noise reduction filter (CSNNFR: Cascaded Sandglass-type Neural Network Noise Reduction Filter) which is extended from the SNNRF (Sandglass-type Neural Network Noise Reduction Filter). The CSNNRF can perform adaptive noise reduction while capturing dynamic characteristics of the speech signal, owing to the plasticity of the SNN. The CSNNRF is suitable for application to the hearing aid since the ease of hearing the speech signal after noise reduction is more important than the denoising rate. We examined the improvement rate of SN ratio and performed a hearing experiment to evaluate the performance of the CSNNRF as a hearing aid. |