| Title | Open Lead Detection Based on Logical Change Caused by AC Voltage Signal Stimulus |
| Author | *Akira Ono (Takuma National College of Technology, Japan), Masahiro Ichimiya, Hiroyuki Yotsuyanagi (The University of Tokushima, Japan), Masao Takagi (Takuma National College of Technology, Japan), Masaki Hashizume (The University of Tokushima, Japan) |
| Page | pp. 241 - 244 |
| Keyword | open leads, detection method, logical change |
| Abstract | In this paper, we propose a new test method for detecting an open lead which occurs when an IC is mounted on a printed circuit board. In the method, an open lead is detected by observing output logical change of an open lead detector. Since the test method is a vectorless test one, test generation and test input application are not needed. Testability of the test method is examined by some experiments. The results show that open leads of SSIs and LSIs will be detected by the method. |
| Title | Flexible Multi-IP Verification Methodology Based on an FPGA Platform |
| Author | *Jin Woo Song, Ki-Seok Chung (Hanyang University, Republic of Korea) |
| Page | pp. 245 - 248 |
| Keyword | SoC, FPGA, verification, OpenRisc |
| Abstract | It is well-known that in ASIC designs, verification is more difficult and time consuming than design itself. As the number of IPs in an SoC design increases, verifying multiple IPs together is really important to reduce time-to-market. In this paper, we propose a novel SoC platform based verification methodology which tests multiple IPs together using a single testbench. We’ve found that commercially available SoC platform such as Altera Cyclone, Xilinx Spartan FPGA provides excellent environment in verifying the functionalities of mutually interactive multiple IPs with very low cost. In our methodology, Only FPGA is used mainly for verification purposes. We program the softcore CPU, Bus Architecture and other peripherals into the FPGA, which will execute C-based testbench and mutually interactive IPs are also programmed into the FPGA device. We implement a set of tools which consists of a communication interface and a wrapper generator which will automatically connect Bus architecture and the IP module together. Using this platform, we have verified up to 5 IPs together successfully, but we can verify more IPs together easily. Time and effort to verify complex IPs have been significantly reduced using this methodology. |
| Title | Fault Analysis of Interconnect Opens in 90nm CMOS ICs with Device Simulator |
| Author | *Masaki Hashizume, Yuichi Yamada, Hiroyuki Yotsuyanagi (The University of Tokushima, Japan), Toshiyuki Tsutsumi, Koji Yamazaki (Meiji University, Japan), Yoshinobu Higami, Hiroshi Takahashi, Yuzo Takamatsu (Ehime University, Japan) |
| Page | pp. 249 - 252 |
| Keyword | interconncet open, fault analysis, device simulation |
| Abstract | Faulty effects of interconnect opens in logic ICs fabricated with a 90nm CMOS process are analyzed by device simulation. Also, it is examined whether a logical error can be caused at an opened input signal line by logic signals of the neighboring signal lines. The simulation results suggest us that a logical error may occur at an interconnect surrounding by 8 interconnects if the interconnects are longer than 5µm and the width of an open defect is greater than 2.0nm. |
| Title | Virtual ARM Simulation Platform for Embedded System Developers |
| Author | Alex Heunhe Han, *Young-Ho Ahn, Ki-Seok Chung (Hanyang University, Republic of Korea) |
| Page | pp. 253 - 256 |
| Keyword | Virtual ARM, Simulation, Embedded System, Developing tools |
| Abstract | Virtual ARM Simulation Platform enables to observe the execution result of embedded software as if they are downloaded and executed on a real hardware ARM Platform. Developers can write program codes, build executable files, and verify their programs by using Virtual ARM Simulation Platform in the development host (PC). Since it doesn't need any hardware but PC, there is no downloading stage in developing procedure (See Figure 1). Major benefits that can be achieved by utilizing a Virtual ARM Simulation Platform are (1) reducing development cost, (2) lowering the entrance barrier for embedded system novices, and (3) making it easier to test and debug embedded software designs. |