| Title | Gain Based Delay Balancing in the Deep Submicron Era |
| Author | *Ryusuke Egawa (Tohoku University, Japan), Jubee Tada (Yamagata University, Japan), Hiroaki Kobayashi (Tohoku University, Japan), Gensuke Goto (Yamagata University, Japan) |
| Page | pp. 577 - 580 |
| Keyword | delay-balancing, wave piepline, VLSI |
| Abstract | In this paper we develop delay balancing tools for equal delay circuit design. Aiming at delay balancing in a deep submicron era, our delay balancing technique employs the gain based delay model. The experimental results show that our tools can realize delay balancing for two kind of adders with 9.96% delay variation on average. |
| Title | Design of an ADALINE Adaptive Filter Based Noise Cancellation Based on Fine-grained Pipelines |
| Author | *Nattha Jindapetch, Pornchai Phukpattaranont, Krerkchai Thongnoo (Prince of Songkla University, Thailand) |
| Page | pp. 581 - 584 |
| Keyword | fine-grained pipeline, ADALINE, noise cancellation, FPGA |
| Abstract | In this paper, a design of an ADALINE adaptive filter based noise
cancellation based on fine-grained pipelines is presented. The
circuit is implemented from 32-bit floating-point arithmetic
function units which are partitioned into proper fine-grained
pipeline stages. Fine-grained pipeline resource-sharing is
performed to minimize the circuit size. The ADALINE adaptive
filter is implemented on an FPGA (Xilinx SPARTAN-3 XC3S400) to
perform power line noise reduction. The performance is also
evaluated. The proposed fine-grained pipelines implementation
archived much higher throughput than the implementation on a
commercial DSP chip, and two times higher than the normal pipeline
implementation. |
| Title | An Efficient Implementation of Multi-channel H.264 Decoder SoC |
| Author | *Wonjong Kim, Juneyoung Chang, Hanjin Cho (Electronics and Telecommunications Research Institute, Republic of Korea) |
| Page | pp. 585 - 588 |
| Keyword | H.264, decoder, soc, surveillance, DVR |
| Abstract | We developed a multi-channel H.264 decoder based on a single channel H.264 decoder which was developed using autonomous module design methodology. Since an autonomous module can control itself by checking states of its neighbor modules, we could easily extend the decoder for decoding multi-channel streams. We utilized the nature of SDRAM structure for efficient use of frame data. We developed specialized SDRAM controller and DMA controller for efficient data transfers of 2-dimensional data. By assigning dedicated channels for modules which require data transfer from/to SDRAM, they can freely use SDRAM data. The decoder can decode 1~16 channels of QVGA, 1~4 channels of VGA, 1~2 channels of XGA or HD, or 1 channel of Full-HD videos at 30 fps within 150 MHz.1 |