| Title | SoC Platform Design and Verification for Multimedia Application |
| Author | *Hongkyun Jung, Xianzhe Jin, Younjin Jung, Ok Kim, Byoungyup Lee, Kwangki Ryoo (Hanbat National University, Republic of Korea) |
| Page | pp. 221 - 224 |
| Keyword | SoC platform, OpenRISC, multimedia |
| Abstract | This paper proposes an SoC platform for the development of multimedia applications. The SoC platform uses a 32-bit RISC processor with 4-way set-associative cache, a VGA controller and an AC97 controller, an SoC debug interface and supports WISHBONE compatible IPs. The multimedia SoC platform is implemented on Xilinx VIRTEX-4 FPGA device and the FPGA executes at the maximum frequency of 64.574MHz. As a result of system-level verification in development board, the SoC platform was satisfactory for the desired functions. |
| Title | Design of Low-Complexity Interpolator for Motion Compensation in H.264 Decoder |
| Author | *Yonghoon Yu, Chanho Lee (Soongsil University, Republic of Korea), Yukyeong Hwang (Mtekvision, Republic of Korea) |
| Page | pp. 225 - 228 |
| Keyword | H.264, Motion Compensation, Interpolation |
| Abstract | The H.264 video coding standard is widely used due to the high compression rate and quality. The motion compensation is the most time-consuming and complex unit in the H.264 decoder. The performance of the motion compensation is determined by the calculation of pixel interpolation. The quarter-pixel interpolation is achieved using 6-tap horizontal or vertical FIR filters for luminance data and bilinear FIR filters for chroma data. We propose the architecture for interpolation of luminance and chroma data in H.264 decoders. It is composed of dual-channel pipelined processing elements and can interpolate integer-, half- and quarter-pixel data. The number of the processing cycles is different depending on the position. The processing elements are composed of adders and shifters to reduce the complexity while the accuracy of the pixel data are maintained. We design interpolators for luminance and chroma data using Verilog-HDL and verify the function and performance by implementing using an FPGA. |
| Title | A Design of OpenVG 2D Vector Graphics Accelerator for a Mobile Device |
| Author | *Jeong-Hun Park, Kwang-Yeob Lee (Department of Computer Engineering, Seokyeong University, Republic of Korea), Jae-Chang Kwak (Department of Computer Science, Seokyeong University, Republic of Korea) |
| Page | pp. 229 - 232 |
| Keyword | 2D Graphics, OpenVG, Vector Graphics |
| Abstract | OpenVG is a royalty-free, cross-platform API that provides a low-level hardware acceleration interface for vector graphic libraries such as Flash and SVG. OpenVG is targeted primarily on handheld devices that require portable acceleration of high-quality vector graphics for compelling user interfaces and text on small screen devices - while enabling hardware acceleration to provide[2].
In this paper, we propose the hardware architecture to accelerate 2D Vector graphics process for mobile device. |
| Title | Recovery Scheme to Reduce Latency of Miss-Prediction for Superscalar Processor using L1 Recovery Cache |
| Author | *JiongYao Ye, Takahiro Watanabe (Graduate School of Information, Production and Systems, Waseda University, Japan) |
| Page | pp. 233 - 236 |
| Keyword | recovery , superscalar, cache, miss-prediction |
| Abstract | A branch prediction is indispensable to modern superscalar processors for high performance. Although it has great possibility to improve performance, the advantage may be lost due to miss-prediction. To reduce such a branch miss-prediction penalty, finer recovery mechanisms are needed. One of those mechanisms is a RcB (recovery buffer), which preserves instructions to be restarted when miss-prediction occurs. But RcB cannot recover instructions issued out of order for a superscalar processor.
This paper proposes a L1 recovery cache embedded in a superscalar processing, RcC for short, which overcomes weakness of RcB and can recover instructions issued out of order so that recovery penalty is reduced. Our proposed L1 RcC scheme can work supplementing the conventional 1-bit dynamic branch predictor used in a superscalar processor, so that miss-prediction penalty can be effectively reduced. |
| Title | Development and Evaluation of Raytracing Accelerating Engine with Bit Serial Arithmetic Units |
| Author | *Tomoyuki Kawamoto, Kazuya Tanigawa, Tetsuo Hironaka, Yuhki Yamabe (Graduate School of Information Sciences, Hiroshima City University, Japan) |
| Page | pp. 237 - 240 |
| Keyword | raytracing, bit serial arithmetic unit, evaluation |
| Abstract | Several methods of parallel computing for high speed processing for raytracing with hardware were proposed.
But, the chip of conventional raytracing hardware needs huge area by using parallel arithmetic units.
In this paper, we present a design of a raytracing accelerator engine with bit serial arithmetic unit to decrease chip area and improve the performance.
As the first stage, we designed prototype hardware which calculate only the process of highest load ratio in processing elements, and evaluate it.
As a result, the prototype hardware was about 5.09 times faster within same chip area. |