| Title | Efficient FPGA-based Hardware Algorithms for Approximate String Matching |
| Author | Sadatoshi Mikami, *Yosuke Kawanaka, Shin'ichi Wakabayashi, Shinobu Nagayama (Hiroshima City University, Japan) |
| Page | pp. 201 - 204 |
| Keyword | string matching, edit distance, FPGA, systolic algorithm, bioinformatics |
| Abstract | In this paper, an efficient FPGA-based hardware algorithm and its extensions are proposed for calculating the edit distance as a degree of similarity between two strings. The proposed algorithms are implemented on FPGA and compared to software which implements the same algorithm. Experimental results show the effectiveness of the proposed algorithms. |
| Title | Design and Analysis of On-chip Leakage Monitor using an MTCMOS circuit |
| Author | *Satoshi Koyama (Shibaura Institute of Technology, Japan), Seidai Takeda (University of Tokyo, Japan), Kimiyoshi Usami (Shibaura Institute of Technology, Japan) |
| Page | pp. 205 - 208 |
| Keyword | MTCMOS circuits, Leakag Power |
| Abstract | Leakage current varies drastically due to process variation and temperature changes. At the circuit design stage, it is difficult to estimate the amount of leakage current at every manufactured chip. The Virtual-ground (VGND) voltage of MTCMOS circuits increases during the sleep operation, because parasitic capacitance of the line is charged up by the leakage current. By applying this behavior, we design leakage monitor circuits using ASPLA 90nm technology. Simulation results show that monitor delay-time is 165ns and monitor-error is 6% under the typical process condition, 25°C and operating frequency of 200MHz. |
| Title | A Multi-thread Processor Architecture With Dual Phase Variable-Length Instructions |
| Author | *HyungKi Jeong (Graduate School of Seokyeong University, Republic of Korea), KwangYeob Lee, Jae-Chang Kwak (Seokyeong University, Republic of Korea) |
| Page | pp. 209 - 212 |
| Keyword | multi-thread, multi-core, stream processor, dual-phase |
| Abstract | Most of multimedia processors for 2D/3D graphics acceleration uses a lots of integer/floating point arithmetic units. We present a new architecture that has more small chip size, performs effective ALU using and reduces instruction cycles significantly with a foundation of multi-thread operation, variable length instruction words, dual phase operation and phase instruction's coordination theories. |
| Title | Power Reduction Technique for Dynamic Reconfigurable Processors with Dynamic Assignment of Dual Supply Voltages |
| Author | *Yusuke Umahashi, Yuki Kambayashi (Shibaura Institute of Technology, Japan), Masaru Kato, Yohei Hasegawa, Hideharu Amano (Keio University, Japan), Kimiyoshi Usami (Shibaura Institute of Technology, Japan) |
| Page | pp. 213 - 216 |
| Keyword | Dynamic Reconfigurable, Dual Supply Voltages, Power Reduction |
| Abstract | When the dynamic reconfigurable processors run, a lot of Processing Elements (PE) are changed by the context which is written information of circuit configuration. Some PEs execute heavy operations, while other PEs execute light operation. Therefore, the delay time of each PE changes with the contexts. We propose a technique to dynamically change dual supply voltages at each PE. When the same voltage was assigned to, the power consumption was reduced by 18.7%. When the voltage is assigned PE-by-PE individually, the power consumption was reduced by 20.3%. |
| Title | Power-Switch Clustering Method for Static Timing Analysis |
| Author | *Tatsunori Hashida, Kimiyoshi Usami (Shibaura Institute of Technology, Japan) |
| Page | pp. 217 - 220 |
| Keyword | MTCMOS, Static Timing Analysis, STA, Power Switch |
| Abstract | A Multiple-Threshold CMOS (MTCMOS) is one of the
techniques which reduce leakage power while keeping high
performance of LSI. Static Timing Analysis (STA) is an
established technique to estimate the delay of circuits. In
MTCMOS circuits, the conventional STA cannot be applied.
In addition, the delay is changed by overlapping of discharge
currents from each gate. In this paper, we propose a PS
clustering technique that makes STA in MTCMOS circuits
possible. |