| Title | High-Performance Architecture of Transform Circuit for Multi-standard Video CODEC |
| Author | *Seonyoung Lee, Kyeongsoon Cho (Hankuk University of Foreign Studies, Republic of Korea) |
| Page | pp. 181 - 184 |
| Keyword | Multi-standard, Video CODEC, Transform, Circuit architecture |
| Abstract | This paper presents the architecture of transform circuit that can support multiple video CODEC standards such as JPEG, MPEG-1/2/4, H.264 and VC-1. The proposed architecture exploits the similarity of 4-point and 8-point DCT's based on the permutation matrices. Since our circuit accepts the transform coefficients from the users, it can be extended very easily to cover any kind of DCT-based transforms for future standards. We described the proposed transform circuit at RTL and verified its operation on FPGA board. |
| Title | A New Implementation of Multilevel Framework for Interconnect-Driven Floorplanning |
| Author | *Zheng Xu, Song Chen, Takeshi Yoshimura (Waseda University, Japan), Yong Fang (Shanghai University, China) |
| Page | pp. 185 - 188 |
| Keyword | V-shaped Multilevel Framework, Fixed-outline Floorplanning, VLSI Design, Multilevel Sequence Pair |
| Abstract | In this paper, we propose a multilevel fixed-outline floorplanning method, called multilevel IARFP, to deal with floorplanning problem for the large-scale integrated circuit designs. We combine the IARFP into the V-shaped multilevel framework, engaging in getting a better result with minimized wirelength. We recursively partition the circuits by using hMetis, to get min-cut cost. After the partition stage, we do floorplanning from top to down building sequences for merging and refinement stage. Then we bottom-up merge the sub-regions into big regions until attain the final floorplan. The IARFP is based on Sequence Pair representation; for multilevel case, we present multilevel Sequence Pair representation to handle the floorplanning. We can get about 11% reductions in wirelength within about 55% run time comparing with flat IARFP algorithm. |
| Title | Design of Application Specific Processor and Compiler for H.264 CAVLC Decoding |
| Author | *Jae-Jin Lee, Jun-Young Lee, MooKyoung Jeong, SeongMo Park, NakWoong Eum (Electronics and Telecommunications Research Institute, Republic of Korea) |
| Page | pp. 189 - 192 |
| Keyword | ASIP, H.264, CAVLC Decoding |
| Abstract | ASIPs are powerful solution which combines high performance of ASICs and flexibility of general purpose processors. This paper proposes a new application specific processor and compiler for CAVLC decoding and portable multimedia application. They are based on the 6-stage pipelined dual issue VLIW(Very Long Instruction Word) architecture, efficient CAVLC decoding instructions and compiler mapping techniques such as CKF(Compiler Known Function), Inline-Assembly and CGD(Code Generator Description). The proposed application specific processor whose gate-count is about 73K runs at 100MHz. Compared to the ARM966ES processor, the proposed method results in about 80% speed-up in terms of execution time and about 50% reduction in terms of hardware complexity without quality degeneration. |
| Title | A Power-Saving 1GBPS Irregular LDPC Decoder based on High-Efficiency Message-Passing |
| Author | Wenming Tang, *Wen Ji (Graduate School of Information, Production and System, Waseda University, Japan), Xianghui Wei, Takeshi Ikenaga, Satoshi Goto (Graduate School of Information, Production and Systems, Waseda University, Japan) |
| Page | pp. 193 - 196 |
| Keyword | LDPC decoder, Message-passing, high throughput, shift-register |
| Abstract | In this paper we proposed a partially-parallel decoder for irregular LDPC codes from IEEE802.11n standards. Our proposed decoder adopts high-efficiency message-passing algorithm and uses the min-sum algorithm handle the message-passing to reduce the hardware implementation complexity and area, and keep high throughput. Considering reducing the power consumption, we used half-registers and half-memory to store the temporary intrinsic messages. The wasted motion of shift-register was suppressed. This strategy would save us higher as 30% power under good channel condition. The synthesis result in TSMC 0.18um COMS technology demonstrated that for (1296,324) irregular LDPC code achieved high throughput (1.05Gbps) at the frequency of 200MHz, with 6% area reduction. |
| Title | A Design Method of Finding Optimal Sampling Pulses and Transistor Sizes in a Sampling Circuit for Liquid Crystal Displays |
| Author | *Shingo Takahashi, Shuji Tsukiyama (Chuo University, Japan), Masanori Hashimoto (Osaka University, Japan), Isao Shirakawa (University of Hyogo, Japan) |
| Page | pp. 197 - 200 |
| Keyword | active matrix LCD, CAD tool, sampling pulse, sampling switch, buffer circuit |
| Abstract | In the design of column driver circuit of liquid crystal displays, a sampling circuit must be designed so that the pixel voltage of a pixel is as close to an input video voltage as possible in various conditions. In this paper, we propose a design method of finding optimal combinations of a sampling switch size and a sampling pulse waveform, which attains this objective. Moreover, in order to optimize both buffer and sampling circuits, we propose a figure of suitability of each combination to the design of buffer circuit generating sampling pulses. We show an experimental result which indicates that the proposed method produced almost equal quality design in eleven times faster than the optimizer in SPICE. |