The 30th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Monday, January 20, 2025

Room Saturn	Innovation Hall
T1 Tutorial-1: Automation of Standard Cell Layout Generation and Design-Technology Co-optimization 9:30 - 12:30	T2 Tutorial-2: AHS: An EDA toolbox for Agile Chip Front-end Design 9:30 - 12:30
T3 Tutorial-3: Memory Built-In Self-Test (MBIST): Advanced Techniques for SoC Design and Verification 14:30 - 16:30	T4 Tutorial-4: Efficient Deployment of Large Language Models on Resource Constrained Edge Computing Platforms 14:30 - 17:30

Tuesday, January 21, 2025

Room Saturn	Room Uranus	Room Venus	Room Mars/Mercury	Innovation Hall	Miraikan Hall
1K (Miraikan Hall) Opening and Keynote Session I 8:30 - 9:45
Coffee Break 9:45 - 10:05
1A (T1-1) System-Level Modeling and Design Methodologies 10:05 - 11:45	1B (T4.2-1) Tools and Techniques for On-Device AI Deployment 10:05 - 11:45	1C (T8-1) AI and Logic Synthesis – A perfect match? 10:05 - 11:20	1D (T3-1) Application-Specific Computing-In-Memory 10:05 - 11:45	1E (SS-1) Machine Learning Based Physical Simulation and Physics-Aware Optimization 10:05 - 11:45	1F (SS-CEDA) CEDA/CASS/SSCS Joint session on Silicon Photonics 10:05 - 11:45
Lunch Break 11:45 - 13:15
2A (T5-1) Accelerating Vision and Transformer Models 13:15 - 15:20	2B (T6-1) Shaping the Future of Analog EDA 13:15 - 14:55	2C (T7-1) Approximate and Stochastic Computing 13:15 - 15:20	2D (T2-1) Next-Generation Embedded Architectures and Tools 13:15 - 15:20	2E (SS-2) Advances in 3D-IC and Ultra-Large-Scale Integration 13:15 - 15:20	2F University Design Contest 13:15 - 15:20
Coffee Break 15:20 - 15:40
3A (SS-3) LLM Acceleration and Specialization for Circuit Design and Edge Applications 15:40 - 17:20	3B (T9-1) Timing Analysis and Optimization 15:40 - 17:45	3C (T12-1) Side Channel Attacks and Trusted Execution Environment 15:40 - 17:45	3D (T3-2) Frameworks and Modeling for Computing-In-Memory 15:40 - 17:20	3E (T4.1-1) AI/ML for Circuit Design and Prediction 15:40 - 17:45
1S (Room Jupiter) ACM SIGDA Student Research Forum / WIP Poster Session 18:00 - 20:00

Wednesday, January 22, 2025

Room Saturn	Room Uranus	Room Venus	Room Mars/Mercury	Innovation Hall	Miraikan Hall
2K (Miraikan Hall) 30th Anniversary and Keynote Session II 8:30 - 9:45
Coffee Break 9:45 - 10:05
4A (T4.2-2) Advanced Methods in AI Hardware Co-Design 10:05 - 11:45	4B (T1-2) Communication Networks 10:05 - 11:45	4C (T2-2) Design and Optimization of Emerging Embedded Applications 10:05 - 11:45	4D (T11-1) Verification and Testing in Machine Lerning Era 10:05 - 11:45	4E (T3-3) Hybrid/Co-Designed Near/In Memory Computing 10:05 - 11:45	4F (SS-4) ML for IC Design and Manufacturing: When Is It Real? 10:05 - 11:45
Lunch Break / CEDA 20th Anniversary Panel (Innovation Hall and more) (See also information at CEDA site) 11:45 - 13:15
5A (T5-2) Innovations in Deep Learning and Neural Network Acceleration 13:15 - 15:20	5B (T7-2) Neuromorphic and Emerging Computing Techniques 13:15 - 15:20	5C (T9-2) Package and PCB 13:15 - 14:55	5D (T12-2) Logic Locking and Hardware Watermarking 13:15 - 14:55	5E (T4.1-2) AI-Driven Innovative Design Methods 13:15 - 15:20	5F (DF-1) Quantum Computing 13:15 - 14:30
Coffee Break 15:20 - 15:40
6A (SS-5) Beyond Digital: Advancing Design Automation for Physical Computing Systems 15:40 - 17:20	6B (T9-3) Floorplan and Placement 15:40 - 17:45	6C (T13-1) Let’s Quantumize: Welcome to the World of Quantum 15:40 - 16:55	6D (T10-1) Innovative Techniques for Energy-Efficient and Reliable Hardware Systems 15:40 - 17:45	6E (T4.1-3) Leveraging Large Language Models in Hardware Design 15:40 - 17:45	6F (DF-2) Advanced Sensor Technologies and Sensor Fusion 15:40 - 16:55
Banquet 18:30 - 20:30

Thursday, January 23, 2025

Room Saturn	Room Uranus	Room Venus	Room Mars/Mercury	Innovation Hall	Miraikan Hall
3K (Miraikan Hall) Keynote Session III 9:00 - 9:45
Coffee Break 9:45 - 10:05
7A (T1-3) Accelerator Design Methodologies 10:05 - 11:45	7B (T5-3) Advanced Architectures for Scientific and Edge Computing 10:05 - 11:45	7C (T6-2) The Science of Light: the New Advancement of Photonic Computing 10:05 - 11:45	7D (T8-2) From Math to Circuits 10:05 - 11:20	7E (T4.2-3) Innovative Techniques in AI Model Optimization and Training 10:05 - 11:20	7F (SS-6) Rapidus' Initiatives to Half Semiconductor Development Time 10:05 - 11:20
Lunch Break 11:45 - 13:15
8A (T1-4) System Level Modelling & Optimization 13:15 - 14:55	8B (T5-4) Emerging Trends in Reconfigurable and Compute-in-Memory 13:15 - 14:55	8C (T3-4) Adaptive and Flexible Memory Architecture 13:15 - 14:55	8D (T9-4) Reliability in Physical Design 13:15 - 14:55	8E (SS-7) Hardware Authenticity towards a Trustworthy Society 13:15 - 14:55	8F (DF-3) Extending the Limits of Classical Computers using Emerging Device and Circuit Technology 13:15 - 14:30
Coffee Break 14:45 - 15:20
9A (T12-3) Homomorphic Encryption and Cloud Security 15:20 - 17:30	9B (T11-2) Advanced Modeling, Simulation, and Verification 15:20 - 17:30	9C (T13-2) Carbon, Light, Fluids: Emerging Technologies 15:20 - 17:30	9D (T10-2) Advanced Techniques for Power Optimization and IR Prediction 15:20 - 17:30	9E (SS-8) Innovations and Challenges on Cryo-CMOS Devices, Circuits and Design Platforms 15:20 - 17:30	9F (DF-4) Integrated Circuit Design Methodologies using Open Source and Artificial Intelligence 15:20 - 16:35

DF: Designers' Forum, SS: Special Session

List of papers

Remark: The presenter of each paper is marked with "*".

Monday, January 20, 2025

[To Session Table]

Session T1 Tutorial-1: Automation of Standard Cell Layout Generation and Design-Technology Co-optimization
Time: 9:30 - 12:30, Monday, January 20, 2025
Location: Room Saturn

T1-1 (Time: 9:30 - 12:30)

Title	(Tutorial) Automation of Standard Cell Layout Generation and Design-Technology Co-optimization
Author	*Taewhan Kim (Seoul National Univ., Republic of Korea)
Detailed information (abstract, etc)

[To Session Table]

Session T2 Tutorial-2: AHS: An EDA toolbox for Agile Chip Front-end Design
Time: 9:30 - 12:30, Monday, January 20, 2025
Location: Innovation Hall

T2-1 (Time: 9:30 - 12:30)

Title	(Tutorial) AHS: An EDA toolbox for Agile Chip Front-end Design
Author	Yun (Eric) Liang, Youwei Xiao, Ruifan Xu (Peking Univ., China)
Detailed information (abstract, etc)

[To Session Table]

Session T3 Tutorial-3: Memory Built-In Self-Test (MBIST): Advanced Techniques for SoC Design and Verification
Time: 14:30 - 16:30, Monday, January 20, 2025
Location: Room Saturn

T3-1 (Time: 14:30 - 16:30)

Title	(Tutorial) Memory Built-In Self-Test (MBIST): Advanced Techniques for SoC Design and Verification
Author	*Prashant Seetharaman (Siemens Digital Industries Software, USA)
Detailed information (abstract, etc)

[To Session Table]

Session T4 Tutorial-4: Efficient Deployment of Large Language Models on Resource Constrained Edge Computing Platforms
Time: 14:30 - 17:30, Monday, January 20, 2025
Location: Innovation Hall

T4-1 (Time: 14:30 - 17:30)

Title	(Tutorial) Efficient Deployment of Large Language Models on Resource-Constrained Edge Computing Platforms
Author	*Yiyu Shi (Univ. of Notre Dame, USA)
Detailed information (abstract, etc)

Tuesday, January 21, 2025

[To Session Table]

Session 1K Opening and Keynote Session I
Time: 8:30 - 9:45, Tuesday, January 21, 2025
Location: Miraikan Hall
Chair: Yuichi Nakamura (NEC, Japan)

1K-1

Title	ASP-DAC 2025 Opening
Detailed information

1K-2

Title	(Keynote Address) Design Innovation and Collaboration with Foundries: Towards a Sustainable Semiconductor Industry
Author	Kazunari Ishimaru (Rapidus, Japan)
Detailed information (abstract, etc)

[To Session Table]

Session 1A (T1-1) System-Level Modeling and Design Methodologies
Time: 10:05 - 11:45, Tuesday, January 21, 2025
Location: Room Saturn
Chair: Jing-Jia Liou (National Tsing Hua Univ., Taiwan)

1A-1 (Time: 10:05 - 10:30)

Title	MACO: A HW-Mapping Co-optimization Framework for DNN Accelerators
Author	*Wujie Zhong, Zijun Jiang, Yangdi Lyu (Hong Kong Univ. of Science and Tech. (GZ), China)
Detailed information (abstract, keywords, etc)

1A-2 (Time: 10:30 - 10:55)

Title	KAPLA: Scalable NN Accelerator Dataflow Design Space Structuring and Fast Exploring
Author	Zhiyao Li, *Mingyu Gao (Tsinghua Univ., China)
Detailed information (abstract, keywords, etc)

1A-3 (Time: 10:55 - 11:20)

Title	Dynamic Co-Optimization Compiler: Leveraging Multi-Agent Reinforcement Learning for Enhanced DNN Accelerator Performance
Author	Arya Fayyazi, Mehdi Kamal, *Massoud Pedram (Univ. of Southern California, USA)
Detailed information (abstract, keywords, etc)

1A-4 (Time: 11:20 - 11:45)

Title	A Computation and Energy Efficient Hardware Architecture for SSL Acceleration
Author	*Huidong Ji (Fudan Univ., China), Sheng Li (Univ. of Pittsburgh, USA), Yue Cao (Fudan Univ., China), Chen Ding (Guangdong Institute of Intelligence Science and Technology, China), Jiawei Xu (Royal Inst. of Tech., Sweden), Qitao Tan (Univ. of Georgia, USA), Jun Liu (Northeastern Univ., USA), Ao Li (Univ. of Arizona, USA), Xulong Tang (Univ. of Pittsburgh, USA), Lirong Zheng (Fudan Univ., China), Geng Yuan (Univ. of Georgia, USA), Zhuo Zou (Fudan Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1B (T4.2-1) Tools and Techniques for On-Device AI Deployment
Time: 10:05 - 11:45, Tuesday, January 21, 2025
Location: Room Uranus
Chairs: Jongeun Lee (Ulsan National Inst. of Science and Tech. (UNIST)), Youngsoo Shin (KAIST, Republic of Korea)

1B-1 (Time: 10:05 - 10:30)

Title	Sequential Printed Multilayer Perceptron Circuits for Super-TinyML Multi-Sensory Applications
Author	Gurol Saglam (Karlsruhe Inst. of Tech., Germany), Florentia Afentaki, *Georgios Zervakis (Univ. of Patras, Greece), Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany)
Detailed information (abstract, keywords, etc)

1B-2 (Time: 10:30 - 10:55)

Title	Learning to Prune and Low-Rank Adaptation for Compact Language Model Deployment
Author	*Asmer Hamid Ali (Arizona State Univ., USA), Fan Zhang (Johns Hopkins Univ., USA), Li Yang (Univ. of North Carolina, Charlotte, USA), Deliang Fan (Arizona State Univ., USA)
Detailed information (abstract, keywords, etc)

1B-3 (Time: 10:55 - 11:20)

Title	LightCL: Compact Continual Learning with Low Memory Footprint For Edge Device
Author	*Zeqing Wang, Fei Cheng, Kangye Ji, Bohu Huang (Xidian Univ., China)
Detailed information (abstract, keywords, etc)

1B-4 (Time: 11:20 - 11:45)

Title	Skip2-LoRA: A Lightweight On-device DNN Fine-tuning Method for Low-cost Edge Devices
Author	*Hiroki Matsutani, Masaaki Kondo, Kazuki Sunaga (Keio Univ., Japan), Radu Marculescu (Univ. of Texas, Austin, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1C (T8-1) AI and Logic Synthesis – A perfect match?
Time: 10:05 - 11:20, Tuesday, January 21, 2025
Location: Room Venus
Chairs: Christophe Dubach (McGill Univ., Canada), Andrea Costamagna (EPFL, Switzerland)

1C-1 (Time: 10:05 - 10:30)

Title	High-Effort Logic Synthesis Using Randomized Transduction
Author	*Yukio Miyasaka (UC Berkeley/X, the moonshot factory, USA), Alan Mishchenko, John Wawrzynek (UC Berkeley, USA), Dino Ruić, Xiaoqing Xu (X, the moonshot factory, USA)
Detailed information (abstract, keywords, etc)

1C-2 (Time: 10:30 - 10:55)

Title	PIRLLS: Pretraining with Imitation and RL Finetuning for Logic Synthesis
Author	*Guande Dong, Jianwang Zhai, Hongtao Cheng, Xiao Yang, Chuan Shi, Kang Zhao (Beijing Univ. of Posts and Telecommunications, China)
Detailed information (abstract, keywords, etc)

1C-3 (Time: 10:55 - 11:20)

Title	MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization
Author	Faezeh Faez, Raika Karimi, *Yingxue Zhang (Huawei Noah’s Ark Lab, Canada), Xing Li, Lei Chen, Mingxuan Yuan (Huawei Noah’s Ark Lab, China), Mahdi Biparva (Huawei Noah’s Ark Lab, Canada)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1D (T3-1) Application-Specific Computing-In-Memory
Time: 10:05 - 11:45, Tuesday, January 21, 2025
Location: Room Mars/Mercury
Chairs: Hiromitsu Awano (Kyoto Univ., Japan), Yiming Chen (Tsinghua Univ., China)

1D-1 (Time: 10:05 - 10:30)

Title	ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis
Author	Tsung-Yu Liu (Academia Sinica, Taiwan), Yen An Lu (Cornell Univ., USA), James Yu (Georgia Tech, USA), *Chin-Fu Nien (National Yang Ming Chiao Tung Univ., Taiwan), Hsiang-Yun Cheng (Academia Sinica, Taiwan)
Detailed information (abstract, keywords, etc)

1D-2 (Time: 10:30 - 10:55)

Title	High-Parallel In-Memory NTT Engine with Hierarchical Structure and Even-Odd Data Mapping
Author	*Bing Li, Huaijun Liu (Capital Normal Univ., China), Yibo Du (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China), Ying Wang (Chinese Academy of Sciences, China)
Detailed information (abstract, keywords, etc)

1D-3 (Time: 10:55 - 11:20)

Title	Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot Learning
Author	*Hao-Wei Chiang, Chi-Tse Huang (National Taiwan Univ., Taiwan), Hsiang-Yun Cheng (Academia Sinica, Taiwan), Po-Hao Tseng, Ming-Hsiu Lee (Macronix International, Taiwan), An-Yeu (Andy) Wu (National Taiwan Univ., Taiwan)
Detailed information (abstract, keywords, etc)

1D-4 (Time: 11:20 - 11:45)

Title	DCiROM: A Fully Digital Compute-in-ROM Design Approach to High Energy Efficiency of DNN Inference at Task Level
Author	*Tianyi Yu, Tianyu Liao, Mufeng Zhou, Xiaotian Chu, Guodong Yin, Mingyen Lee, Yongpan Liu, Huazhong Yang, Xueqing Li (Tsinghua Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1E (SS-1) Machine Learning Based Physical Simulation and Physics-Aware Optimization
Time: 10:05 - 11:45, Tuesday, January 21, 2025
Location: Innovation Hall
Chairs: Wenjian Yu (Tsinghua Univ., China), Yuanqing Cheng (Beihang Univ., China)

1E-1 (Time: 10:05 - 10:30)

Title	(Invited Paper) Deep Learning Inspired Capacitance Extraction Techniques
Author	*Wenjian Yu, Shan Shen, Dingcheng Yang, Haoyuan Li, Jiechen Huang, Chunyan Pei (Tsinghua Univ., China)
Detailed information (abstract, keywords, etc)

1E-2 (Time: 10:30 - 10:55)

Title	(Invited Paper) Enhanced Operator Learning for Scalable and Ultra-fast Thermal Simulation in 3D-IC Design
Author	Xinling Yu, Ziyue Liu (UCSB, USA), Hai Li, Ian Young (Intel, USA), *Zheng Zhang (UCSB, USA)
Detailed information (abstract, keywords, etc)

1E-3 (Time: 10:55 - 11:20)

Title	(Invited Paper) Boosting the Performance of Transistor-Level Circuit Simulation with GNN
Author	Jiqing Jiang, Yongqiang Duan, *Zhou Jin (China Univ. of Petroleum-Beijing, China)
Detailed information (abstract, keywords, etc)

1E-4 (Time: 11:20 - 11:45)

Title	(Invited Paper) Emag-Aware ML-Based Layout Optimization for High-Speed IC Design
Author	*Garth Sundberg (ANSYS, USA), Rodger Luo (ANSYS, China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1F (SS-CEDA) CEDA/CASS/SSCS Joint session on Silicon Photonics
Time: 10:05 - 11:45, Tuesday, January 21, 2025
Chair: Tsung-Yi Ho (Chinese Univ. of Hong Kong, Hong Kong)

1F-1 (Time: 10:05 - 10:30)

Title	(Invited Paper) Bridging EDA and Silicon Photonics Design: Enabling Robust-by-Design Photonic Integrated Circuits
Author	Zahra Ghanaatian, Asif Mirza, Amin Shafiee, Sudeep Pasricha, *Mahdi Nikdast (Colorado State Univ., USA)
Detailed information (abstract, keywords, etc)

1F-2 (Time: 10:30 - 10:55)

Title	(Invited Paper) SPICE-Compatible Modeling and Design for Electronic-Photonic Integrated Circuits
Author	*Yuxiang Fu, Yinyi Liu (Hong Kong Univ. of Science and Tech., Hong Kong), Ngai Wong (Univ. of Hong Kong, Hong Kong), Jiang Xu (Hong Kong Univ. of Science and Tech. (GZ), China)
Detailed information (abstract, keywords, etc)

1F-3 (Time: 10:55 - 11:20)

Title	(Invited Paper) Modeling and Simulation of Silicon Photonics Systems in SystemVerilog/XMODEL
Author	*Jaeha Kim (Seoul National Univ./Scientific Analog, Republic of Korea)
Detailed information (abstract, keywords, etc)

1F-4 (Time: 11:20 - 11:45)

Title	(Invited Paper) Si Photonic Ring-Resonator-Based WDM Transceivers
Author	*Woo-Young Choi, Dae-Won Rho (Yonsei Univ., Republic of Korea), Jae-Koo Park (Yonsei Univ./Samsung Electronics, Republic of Korea), Seung-Jae Yang, Jae-Ho Lee, Yongjin Ji (Yonsei Univ., Republic of Korea)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2A (T5-1) Accelerating Vision and Transformer Models
Time: 13:15 - 15:20, Tuesday, January 21, 2025
Location: Room Saturn
Chairs: Quan Chen (Southern Univ. of Science and Tech., China), Sheldon Tan (UC Riverside, USA)

2A-1 (Time: 13:15 - 13:40)

Title	ViDA: Video Diffusion Transformer Acceleration with Differential Approximation and Adaptive Dataflow
Author	*Li Ding, Jun Liu, Shan Huang, Guohao Dai (Shanghai Jiao Tong Univ., China)
Detailed information (abstract, keywords, etc)

2A-2 (Time: 13:40 - 14:05)

Title	APTO: Accelerating Serialization-Based Point Cloud Transformers with Position-Aware Pruning
Author	*Qichu Sun, Rui Meng, Haishuang Fan (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China), Fangqiang Ding (Univ. of Edinburgh, UK), Linxi Lu (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China), Jingya Wu, Xiaowei Li (Chinese Academy of Sciences, China), Guihai Yan (Chinese Academy of Sciences/YUSUR Technology, China)
Detailed information (abstract, keywords, etc)

2A-3 (Time: 14:05 - 14:30)

Title	UEDA: A Universal And Efficient Deformable Attention Accelerator For Various Vision Tasks
Author	Kairui Sun, *Meiqi Wang, Junhai Zhou, Zhongfeng Wang (Sun Yat-sen Univ., China)
Detailed information (abstract, keywords, etc)

2A-4 (Time: 14:30 - 14:55)

Title	Deploying Diffusion Models with Scheduling Space Search and Memory Overflow Prevention Based on Graph Optimization
Author	*Hao Zhou, Yang Liu, Hongji Wang (Fudan Univ., China), EnHao Tang (Nanjing Univ., China), Shun Li (Southeast Univ., China), Yifan Zhang (Fudan Univ., China), Guohao Dai (Shanghai Jiao Tong Univ., China), Yongpan Liu (Tsinghua Univ., China)
Detailed information (abstract, keywords, etc)

2A-5 (Time: 14:55 - 15:20)

Title	TWDP: A Vision Transformer Accelerator with Token-Weight Dual-Pruning Strategy for Edge Device Deployment
Author	*Guang Yang, Xinming Yan, Hui Kou, Zihan Zou, Qingwen Wei, Hao Cai, Bo Liu (Southeast Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2B (T6-1) Shaping the Future of Analog EDA
Time: 13:15 - 14:55, Tuesday, January 21, 2025
Location: Room Uranus
Chairs: Zhou Jin (China Univ. of Petroleum, China), Nobukazu Takai (Kyoto Inst. of Tech.)

2B-1 (Time: 13:15 - 13:40)

Title	A Practical Randomized GMRES Algorithm for Solving Linear Equation System in Circuit Simulation
Author	*Baiyu Chen, Jiawen Cheng, Wenjian Yu (Tsinghua Univ., China)
Detailed information (abstract, keywords, etc)

2B-2 (Time: 13:40 - 14:05)

Title	Balancing Objective Optimization and Constraint Satisfaction for Robust Analog IC Design Automation
Author	*Jintao Li (Univ. of Electronic Science and Tech. of China, China), Haochang Zhi (Southeast Univ., China), Jiang Xiao (Univ. of Electronic Science and Tech. of China, China), Yanhan Zeng (Guangzhou Univ., China), Weiwei Shan (Southeast Univ., China), Yun Li (Univ. of Electronic Science and Tech. of China, China)
Detailed information (abstract, keywords, etc)

2B-3 (Time: 14:05 - 14:30)

Title	Analog Circuit Transfer Method Across Technology Nodes via Transistor Behavior
Author	*Haochang Zhi (Southeast Univ., China), Jintao Li, Yun Li (Shenzhen Institute for Advanced Study, UESTC, China), Weiwei Shan (Southeast Univ., China)
Detailed information (abstract, keywords, etc)

2B-4 (Time: 14:30 - 14:55)

Title	AIPlace: Analog IC Placement with Multi-Task Learning Framework
Author	*Lijie Wang, Jing Wang, Song Chen, Qi Xu (Univ. of Science and Tech. of China, China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2C (T7-1) Approximate and Stochastic Computing
Time: 13:15 - 15:20, Tuesday, January 21, 2025
Location: Room Venus
Chair: Yue Zhang (Beihang Univ., China)

2C-1 (Time: 13:15 - 13:40)

Title	Stochastic Multivariate Universal-Radix Finite-State Machine: a Theoretically and Practically Elegant Nonlinear Function Approximator
Author	*Xincheng Feng (Univ. of Hong Kong, Hong Kong), Guodong Shen, Jianhao Hu (Univ. of Electronic Science and Tech. of China, China), Meng Li (Peking Univ., China), Ngai Wong (Univ. of Hong Kong, Hong Kong)
Detailed information (abstract, keywords, etc)

2C-2 (Time: 13:40 - 14:05)

Title	ACLAM: Accuracy-Configurable Logarithmic Approximate Floating-point Multiplier
Author	*Zhongyu Guan, Qiang Liu (Tianjin Univ., China), Guangdong Lin (Anhui Siliepoch Technology Company, China)
Detailed information (abstract, keywords, etc)

2C-3 (Time: 14:05 - 14:30)

Title	AmPEC: Approximate MRAM with Partial Error Correction for Fine-grained Energy-quality Trade-off
Author	*Lan-yang Sun (Southeast Univ., China), Yaoru Hou (Hong Kong Univ. of Science and Tech., Hong Kong), Hao Cai (Southeast Univ., China)
Detailed information (abstract, keywords, etc)

2C-4 (Time: 14:30 - 14:55)

Title	HyPPO: Hybrid Piece-wise Polynomial Approximation and Optimization for Hardware Efficient Designs
Author	*Lakshmi Sai Niharika Vulchi, Valipireddy Pranathi, Mahati Basavaraju, Madhav Rao (IIIT Bangalore, India)
Detailed information (abstract, keywords, etc)

2C-5 (Time: 14:55 - 15:20)

Title	Hybrid Temporal Computing for Lower Power Hardware Accelerators
Author	Maliha Tasnim, Sachin Sachdeva, Yibo Liu, *Sheldon X.D. Tan (Univ. of California, Riverside, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2D (T2-1) Next-Generation Embedded Architectures and Tools
Time: 13:15 - 15:20, Tuesday, January 21, 2025
Location: Room Mars/Mercury
Chair: Chao Huang (Univ. of Southampton)

2D-1 (Time: 13:15 - 13:40)

Title	PULSE: Progressive Utilization of Log-Structured Techniques to Ease SSD Write Amplification in B-epsilon-tree
Author	Huai-De Peng (National Central Univ., Taiwan), *Yi-Shen Chen (National Taiwan Univ. of Science and Tech., Taiwan), Tseng-Yi Chen (National Central Univ., Taiwan), Yuan-Hao Chang (Academia Sinica, Taiwan)
Detailed information (abstract, keywords, etc)

2D-2 (Time: 13:40 - 14:05)

Title	Rethinking B^ε tree Indexing Structure over NVM with the Support of Multi-write Modes
Author	Hui-Tang Luo, *Tseng-Yi Chen (National Central Univ., Taiwan)
Detailed information (abstract, keywords, etc)

2D-3 (Time: 14:05 - 14:30)

Title	End-to-end Compilation is All FPGAs Need: A Unified Overlay-based FPGA Compiler for Deep Learning
Author	*Kai Qian, Haodong Lu (Fudan Univ., China), Yinqiu Liu (Nanyang Technological Univ., Singapore), Zexu Zhang, Kun Wang (Fudan Univ., China)
Detailed information (abstract, keywords, etc)

2D-4 (Time: 14:30 - 14:55)

Title	HDCC: A Hierarchical Dataflow-Oriented CGRA Compiler for Complex Applications
Author	*Shangli Li, Mingjie Xing, Yanjun Wu (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China)
Detailed information (abstract, keywords, etc)

2D-5 (Time: 14:55 - 15:20)

Title	HAMMER: Hardware-aware Runtime Program Execution Acceleration through runtime reconfigurable CGRAs
Author	Qilin Si, *Benjamin Carrion Schafer (Univ. of Texas, Dallas, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2E (SS-2) Advances in 3D-IC and Ultra-Large-Scale Integration
Time: 13:15 - 15:20, Tuesday, January 21, 2025
Location: Innovation Hall
Chair: Yibo Lin (Peking Univ., China)

2E-1 (Time: 13:15 - 13:40)

Title	(Invited Paper) Fast Routing Algorithm for Mask Stitching Region of Ultra Large Wafer Scale Integration
Author	Zhen Zhuang (Chinese Univ. of Hong Kong, Hong Kong), Quan Chen, Hao Yu (Southern Univ. of Science and Tech., China), *Tsung-Yi Ho (Chinese Univ. of Hong Kong, Hong Kong)
Detailed information (abstract, keywords, etc)

2E-2 (Time: 13:40 - 14:05)

Title	(Invited Paper) The Survey of 2.5D Integrated Architecture: An EDA perspective
Author	Shixin Chen (Chinese Univ. of Hong Kong, Hong Kong), Hengyuan Zhang, Zichao Ling, Jianwang Zhai (Beijing Univ. of Post and Telecommunication, China), *Bei Yu (Chinese Univ. of Hong Kong, Hong Kong)
Detailed information (abstract, keywords, etc)

2E-3 (Time: 14:05 - 14:30)

Title	(Invited Paper) Toward Advancing 3D-ICs Physical Design: Challenges and Opportunities
Author	Xueyan Zhao (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China), Weiguo Li, Zhisheng Zeng (Pengcheng Laboratory, China), Zhipeng Huang (Beijing Institute of Open Source Chip, China), Biwei Xie (Chinese Academy of Sciences/Pengcheng Laboratory/Univ. of Chinese Academy of Sciences, China), *Xingquan Li (Pengcheng Laboratory/Beijing Institute of Open Source Chip, China), Yungang Bao (Chinese Academy of Sciences/Beijing Institute of Open Source Chip/Univ. of Chinese Academy of Sciences, China)
Detailed information (abstract, keywords, etc)

2E-4 (Time: 14:30 - 14:55)

Title	(Invited Paper) Processing-Near-Memory with Chip Level 3D-IC
Author	*Miao Liu, Qingqing Sun, David Wei Zhang (Fudan Univ., China)
Detailed information (abstract, keywords, etc)

2E-5 (Time: 14:55 - 15:20)

Title	(Invited Paper) Clustering-Driven Bonding Terminal Legalization with Reinforcement Learning for F2F 3D ICs
Author	Gyumin Kim, *Heechun Park (Ulsan National Inst. of Science and Tech. (UNIST), Republic of Korea)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 2F University Design Contest
Time: 13:15 - 15:20, Tuesday, January 21, 2025
Chairs: Mahfuzul Islam (Tokyo Inst. of Tech., Japan), Shinya Takamaeda Yamazaki (Univ. of Tokyo, Japan)

2F-1 (Time: 13:15 - 13:20)

Title	A 10.60 μW 150 GOPS Mixed-Bit-Width Sparse CNN Accelerator for Life-Threatening Ventricular Arrhythmia Detection
Author	Yifan Qin, Zhenge Jia, Zheyu Yan (Univ. of Notre Dame, USA), Jay Mok, Manto Yung, Yu Liu, Xuejiao Liu (Hong Kong Univ. of Science and Tech./AI Chip Center for Emerging Smart System, Hong Kong), Wujie Wen (North Carolina State Univ., USA), Luhong Liang, Kwang-Ting Tim Cheng (Hong Kong Univ. of Science and Tech./AI Chip Center for Emerging Smart System, Hong Kong), Xiaobo Sharon Hu, *Yiyu Shi (Univ. of Notre Dame, USA)
Detailed information (abstract, keywords, etc)

2F-2 (Time: 13:20 - 13:25)

Title	Headset-Integrated Brain-Machine Interface for Mind Imagery and Control in VR/MR Applications
Author	Zhiwei Zhong (Northwestern Univ., USA), Yijie Wei (Kilby Labs, Texas Instruments, USA), Lance Go, Yiqi Li, *Jie Gu (Northwestern Univ., USA)
Detailed information (abstract, keywords, etc)

2F-3 (Time: 13:25 - 13:30)

Title	Humanoid Robot Control: A Mixed-Signal Footstep Planning SoC with ZMP Gait Scheduler and Neural Inverse Kinematics
Author	Qiankai Cao, Yiqi Li, Juin Chuen Oh, *Jie Gu (Northwestern Univ., USA)
Detailed information (abstract, keywords, etc)

2F-4 (Time: 13:30 - 13:35)

Title	A Coarse- and Fine-Grained LUT Segmentation Method Enabling Single FPGA Implementation of Wired-Logic DNN Processor
Author	*Yuxuan Pan, Dongzhu Li, Mototsugu Hamada, Atsutake Kosuge (Univ. of Tokyo, Japan)
Detailed information (abstract, keywords, etc)

2F-5 (Time: 13:35 - 13:40)

Title	Learned Image Codec on FPGA: Algorithm, Architecture and System Design
Author	*Heming Sun, Jing Wang (Yokohama National Univ., Japan), Silu Liu, Shinji Kimura (Waseda Univ., Japan), Masahiro Fujita (Univ. of Tokyo, Japan)
Detailed information (abstract, keywords, etc)

2F-6 (Time: 13:40 - 13:45)

Title	Transformer Hetero-CiM: Heterogeneous Integration of ReRAM CiM and SRAM CiM for Vision Transformer at Edge Devices
Author	*Naoko Misawa, Tao Wang, Chihiro Matsui, Ken Takeuchi (Univ. of Tokyo, Japan)
Detailed information (abstract, keywords, etc)

2F-7 (Time: 13:45 - 13:50)

Title	A High-Density Hybrid Buck Converter with a Charge Converging Phase Reducing Inductor Current for 12V Power Supply Systems
Author	*Yichao Ji, Ji Jin, Lin Cheng (Univ. of Science and Tech. of China, China)
Detailed information (abstract, keywords, etc)

2F-8 (Time: 13:50 - 13:55)

Title	A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology
Author	*Yunseong Jo, Taeseung Kang (Hanyang Univ., Republic of Korea), Jeonghyu Yang (Ramschip, Republic of Korea), Jaeduk Han (Hanyang Univ., Republic of Korea)
Detailed information (abstract, keywords, etc)

2F-9 (Time: 13:55 - 14:00)

Title	A 4-Stream 8-Element Time-Division MIMO Phased-Array Receiver for 5G NR and Beyond Achieving 9.6Gbps Data Rate
Author	*Yi Zhang, Minzhe Tang, Zheng Li, Dongfan Xu, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada (Institute of Science Tokyo, Japan)
Detailed information (abstract, keywords, etc)

2F-10 (Time: 14:00 - 14:05)

Title	Design of a 1-5GHz Inverter-Based Phase Interpolator for Spin-Wave Detection
Author	*Yuyang Zhu, Zunsong Yang, Zhenyu Cheng, Md Shamim Sarker, Hiroyasu Yamahara, Munetoshi Seki, Hitoshi Tabata, Tetsuya Iizuka (Univ. of Tokyo, Japan)
Detailed information (abstract, keywords, etc)

2F-11 (Time: 14:05 - 14:10)

Title	Self-recovery hysteresis control based on-chip SC DC-DC converter robust to load fluctuation
Author	*Koji Kikuta, Takashi Hisakado (Kyoto Univ., Japan), Mahfuzul Islam (Tokyo Inst. of Tech., Japan)
Detailed information (abstract, keywords, etc)

2F-12 (Time: 14:10 - 14:15)

Title	A Tri-Mode Harmonic-Selection Mixer with Multiphase LO Supporting 24.25–71GHz for Multi-Band 5G NR
Author	*Dongfan Xu, Minzhe Tang, Yi Zhang, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada (Institute of Science Tokyo, Japan)
Detailed information (abstract, keywords, etc)

2F-13 (Time: 14:15 - 14:20)

Title	A D-Band CMOS Transceiver Chipset Supporting 640Gb/s Date Rate with 4×4 Line-of-Sight MIMO
Author	*Chenxin Liu, Zheng Li, Yudai Yamazaki, Hans Herdian, Chun Wang, Anyi Tian, Jun Sakamaki, Han Nie, Xi Fu, Sena Kato, Wenqian Wang, Hongye Huang (Tokyo Inst. of Tech., Japan), Shinsuke Hara, Akifumi Kasamatsu (NICT, Japan), Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada (Tokyo Inst. of Tech., Japan)
Detailed information (abstract, keywords, etc)

2F-14 (Time: 14:20 - 14:25)

Title	Low quiescent current LDO with FBPEC to improve PSRR specific frequency band for wearable EEG recording devices
Author	*Kenji Mii, Daisuke Kanemoto, Tetsuya Hirose (Osaka Univ., Japan)
Detailed information (abstract, keywords, etc)

2F-15 (Time: 14:25 - 14:30)

Title	Design of a 7.2-GHz CMOS Receiver Front-end for One-chip Transponders in Deep Space Probes
Author	*Sota Kano (Univ. of Tokyo, Japan), Naoto Usami, Atsushi Tomiki (JAXA, Japan), Tetsuya Iizuka (Univ. of Tokyo, Japan)
Detailed information (abstract, keywords, etc)

2F-16 (Time: 14:30 - 14:35)

Title	Design of 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always-Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording
Author	*Hiroaki Kitaike, Hironori Tagawa, Shufan Xu, Ruilin Zhang, Kunyang Liu, Kiichi Niitsu (Kyoto Univ., Japan)
Detailed information (abstract, keywords, etc)

2F-17 (Time: 14:35 - 14:40)

Title	0.36μW/channel Capacitively-coupled Chopper Instrumentation Amplifier for EEG Recording Wearable Devices with Compressed Sensing Framework
Author	Kenji Mii, *Daisuke Kanemoto, Tetsuya Hirose (Osaka Univ., Japan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 3A (SS-3) LLM Acceleration and Specialization for Circuit Design and Edge Applications
Time: 15:40 - 17:20, Tuesday, January 21, 2025
Location: Room Saturn
Chairs: Zheyu Yan (Zhejiang Univ., China), Cheng Zhuo (Zhejiang Univ., China)

3A-1 (Time: 15:40 - 16:05)

Title	(Invited Paper) Standard Cell Layout Generation: Review, Challenges, and Future Works
Author	*Chung-Kuan Cheng, Byeonggon Kang, Bill Lin, Yucheng Wang (Univ. of California, San Diego, USA)
Detailed information (abstract, keywords, etc)

3A-2 (Time: 16:05 - 16:30)

Title	(Invited Paper) ML-assisted SRAM Soft Error Rate Characterization: Opportunities and Challenges
Author	*Masanori Hashimoto, Ryuichi Yasuda, Kazusa Takami, Yuibi Gomi (Kyoto Univ., Japan), Kozo Takeuchi (JAXA, Japan)
Detailed information (abstract, keywords, etc)

3A-3 (Time: 16:30 - 16:55)

Title	(Invited Paper) Boosting Standard Cell Library Characterization with Machine Learning
Author	Zhengrui Chen, Chengjun Guo, Zixuan Song (Zhejiang Univ., China), Guozhu Feng (Zhejiang Univ./Empyrean Technology, China), Shizhang Wang (Zhejiang Univ., China), Li Zhang (Hubei Univ. of Tech., China), Xunzhao Yin, Zhenhua Wu, Zheyu Yan, *Cheng Zhuo (Zhejiang Univ., China)
Detailed information (abstract, keywords, etc)

3A-4 (Time: 16:55 - 17:20)

Title	(Invited Paper) Exploring Better Intra-Cell Routability for Layout Synthesis of Multi-Row Standard Cells
Author	Kairong Guo, Xiaohan Gao, Haoyi Zhang, Runsheng Wang, Ru Huang, *Yibo Lin (Peking Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 3B (T9-1) Timing Analysis and Optimization
Time: 15:40 - 17:45, Tuesday, January 21, 2025
Location: Room Uranus
Chair: Heechun Park (Ulsan National Inst. of Science and Tech., Republic of Korea)

3B-1 (Time: 15:40 - 16:05)

Title	Graph-Based Timing Prediction at Early-Stage RTL Using Large Language Model
Author	*Fahad Rahman Amik, Yousef Safari, Zhanguang Zhang (McGill Univ., Canada), Boris Vaisband (Univ. of California, Irvine, USA)
Detailed information (abstract, keywords, etc)

3B-2 (Time: 16:05 - 16:30)

Title	SI-Aware Wire Timing Prediction at Pre-Routing Stage with Multi-Corner Consideration
Author	Yushan Wang, *Xu He, Renjun Zhao (Hunan Univ., China), Yao Wang (Independent Researcher, China), Chang Liu, Yang Guo (National Univ. of Defense Tech., China)
Detailed information (abstract, keywords, etc)

3B-3 (Time: 16:30 - 16:55)

Title	iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis
Author	Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin (Univ. of Wisconsin, Madison, USA), Yang Sui (Rice Univ., USA), Chih-Chun Chang, Yi-Hua Chung, Wan Luan Lee (Univ. of Wisconsin, Madison, USA), Zizheng Guo, Yibo Lin (Peking Univ., USA), *Tsung-Wei Huang (Univ. of Wisconsin, Madison, USA)
Detailed information (abstract, keywords, etc)

3B-4 (Time: 16:55 - 17:20)

Title	PathGen: An Efficient Parallel Critical Path Generation Algorithm
Author	Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan-Luan Lee (Univ. of Wisconsin at Madison, USA), Zizheng Guo, Yibo Lin (Peking Univ., China), *Tsung-Wei Huang (Univ. of Wisconsin at Madison, USA)
Detailed information (abstract, keywords, etc)

3B-5 (Time: 17:20 - 17:45)

Title	Yield-driven Clock Skew Scheduling Based on Generalized Extreme Value Distribution
Author	*Kaixiang Zhu, Wai-shing Luk, Lingli Wang (Fudan Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 3C (T12-1) Side Channel Attacks and Trusted Execution Environment
Time: 15:40 - 17:45, Tuesday, January 21, 2025
Location: Room Venus
Chairs: Qiang Liu (Tianjin Univ., China), Song Chen (Univ. of Science and Tech. of China, China)

3C-1 (Time: 15:40 - 16:05)

Title	Making Legacy Hardware Robust against Side Channel Attacks via High-Level Synthesis
Author	Md Imtiaz Rashid, *Benjamin Carrion Schafer (Univ. of Texas, Dallas, USA)
Detailed information (abstract, keywords, etc)

3C-2 (Time: 16:05 - 16:30)

Title	Machine Learning-Based Real-Time Detection of Power Analysis Attacks Using Supply Voltage Comparisons
Author	Nan Wang, *Ruichao Liu, Yufeng Shan, Yu Zhu (East China Univ. of Science and Tech., China), Song Chen (Univ. of Science and Tech. of China, China)
Detailed information (abstract, keywords, etc)

3C-3 (Time: 16:30 - 16:55)

Title	Side-channel Collision Attacks on Hyper-Dimensional Computing based on Emerging Resistive Memories
Author	*Brojogopal Sapui, Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany)
Detailed information (abstract, keywords, etc)

3C-4 (Time: 16:55 - 17:20)

Title	Dep-TEE: Decoupled Memory Protection for Secure and Scalable Inter-enclave Communication on RISC-V
Author	*Shangjie Pan (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences/Zhongguancun Laboratory, China), Xuanyao Peng (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China), Zeyuan Man (ShanghaiTech Univ./Beijing Institute of Open Source Chip, China), Xiquan Zhao, Dongrong Zhang (Zhongguancun Laboratory, China), Bicheng Yang, Dong Du (Shanghai Jiao Tong Univ., China), Hang Lu (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences/Zhongguancun Laboratory, China), Yubin Xia (Shanghai Jiao Tong Univ., China), Xiaowei Li (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences/Zhongguancun Laboratory, China)
Detailed information (abstract, keywords, etc)

3C-5 (Time: 17:20 - 17:45)

Title	Through Fabric: A Cross-world Thermal Covert Channel on TEE-enhanced FPGA-MPSoC Systems
Author	*Hassan Nassar, Jeferson Gonzalez-Gomez, Varun Manjunath (KIT, Germany), Lars Bauer (-, Germany), Jörg Henkel (KIT, Germany)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 3D (T3-2) Frameworks and Modeling for Computing-In-Memory
Time: 15:40 - 17:20, Tuesday, January 21, 2025
Location: Room Mars/Mercury
Chairs: Zhenhua Zhu (Tsinghua Univ., China), Kentaro Yoshioka (Keio Univ., Japan)

3D-1 (Time: 15:40 - 16:05)

Title	Theoretical Optimal Specifications of Memcapacitors for Charge-Based In-Memory Computing
Author	*Zichen Qian, Rentao Wan (Columbia Univ., USA), Chin-Hsiang Liao, Steven Koester (Univ. of Minnesota, USA), Mingoo Seok (Columbia Univ., USA)
Detailed information (abstract, keywords, etc)

3D-2 (Time: 16:05 - 16:30)

Title	An Island Style Multi-Objective Evolutionary Framework for Synthesis of Memristor-Aided Logic
Author	Umar Afzaal, *Seunggyu Lee, Youngsoo Shin (Korea Advanced Inst. of Science and Tech. (KAIST), Republic of Korea)
Detailed information (abstract, keywords, etc)

3D-3 (Time: 16:30 - 16:55)

Title	PIMutation: Exploring the Potential of Real PIM Architecture for Quantum Circuit Simulation
Author	Dongin Lee (National Univ. of Singapore, Singapore), *Enhyeok Jang, Seungwoo Choi, Junwoong An, Cheolhwan Kim, Won Woo Ro (Yonsei Univ., Republic of Korea)
Detailed information (abstract, keywords, etc)

3D-4 (Time: 16:55 - 17:20)

Title	A Fail-Slow Detection Framework for HBM devices
Author	*Zikang Xu, Yiming Zhang, Zhirong Shen (XiaMen Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 3E (T4.1-1) AI/ML for Circuit Design and Prediction
Time: 15:40 - 17:45, Tuesday, January 21, 2025
Location: Innovation Hall
Chair: Jaeyong Chung (Yonsei Univ., Republic of Korea)

3E-1 (Time: 15:40 - 16:05)

Title	DeepSeq2: Enhanced Sequential Circuit Learning with Disentangled Representations
Author	*Sadaf Khan, Zhengyuan Shi, Ziyang Zheng (Chinese Univ. of Hong Kong, Hong Kong), Min Li (Huawei Noah's Ark Lab, China), Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong)
Detailed information (abstract, keywords, etc)

3E-2 (Time: 16:05 - 16:30)

Title	A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks
Author	*Wenji Fang, Shang Liu (Hong Kong Univ. of Science and Tech., Hong Kong), Hongce Zhang (Hong Kong Univ. of Science and Tech. (GZ), China), Zhiyao Xie (Hong Kong Univ. of Science and Tech., Hong Kong)
Detailed information (abstract, keywords, etc)

3E-3 (Time: 16:30 - 16:55)

Title	ParaFormer: A Hybrid Graph Neural Network and Transformer Approach for Pre-Routing Parasitic RC Prediction
Author	*Jongho Yoon, Jakang Lee, Donggyu Kim, Junseok Hur, Seokhyeong Kang (POSTECH, Republic of Korea)
Detailed information (abstract, keywords, etc)

3E-4 (Time: 16:55 - 17:20)

Title	Static IR Drop Prediction with Limited Data from Real Designs
Author	Lizi Zhang, *Azadeh Davoodi (Univ. of Wisconsin - Madison, USA)
Detailed information (abstract, keywords, etc)

3E-5 (Time: 17:20 - 17:45)

Title	Towards Big Data in AI for EDA Research: Generation of New Pseudo-Circuits at RTL Stage
Author	*Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie (HKUST, Hong Kong)
Detailed information (abstract, keywords, etc)

Wednesday, January 22, 2025

[To Session Table]

Session 2K 30th Anniversary and Keynote Session II
Time: 8:30 - 9:45, Wednesday, January 22, 2025
Location: Miraikan Hall
Chair: Shinji Kimura (Waseda Univ., Japan)

2K-1

Title	30th Anniversary
Detailed information

2K-2

Title	(Keynote Address) Compilation and Architecture Optimization for Quantum Computing
Author	Jason Cong (UCLA, USA)
Detailed information (abstract, etc)

[To Session Table]

Session 4A (T4.2-2) Advanced Methods in AI Hardware Co-Design
Time: 10:05 - 11:45, Wednesday, January 22, 2025
Location: Room Saturn
Chairs: Wanyeong Jung (Korea Advanced Inst. of Science and Tech. (KAIST)), Yeseong Kim (DGIST, Republic of Korea)

4A-1 (Time: 10:05 - 10:30)

Title	Accelerator for LLM-Enhanced GNN with Product Quantization and Unified Indexing
Author	*Jiaming Xu, Jinhao Li, Jun Liu, Hao Zhou, Guohao Dai (Shanghai Jiao Tong Univ., China)
Detailed information (abstract, keywords, etc)

4A-2 (Time: 10:30 - 10:55)

Title	MICSim: A Modular Simulator for Mixed-signal Compute-in-Memory based AI Accelerator
Author	*Cong Wang, Zeming Chen, Shanshi Huang (Hong Kong Univ. of Science and Tech. (GZ), China)
Detailed information (abstract, keywords, etc)

4A-3 (Time: 10:55 - 11:20)

Title	DIAG: A Refined Four-layer Agile Hardware Developing Flow for Generating Flexible Reconfigurable Architectures
Author	*Haojia Hui, Jiangyuan Gu, Xunbo Hu, Shaojun Wei, Shouyi Yin (Tsinghua Univ., China)
Detailed information (abstract, keywords, etc)

4A-4 (Time: 11:20 - 11:45)

Title	MPICC: Multiple-Precision Inter-Combined MAC Unit with Stochastic Rounding for Ultra-Low-Precision Training
Author	*Leran Huang (Tsinghua Shenzhen International Graduate School, China), Yongpan Liu, Xinyuan Lin, Chenhan Wei, Wenyu Sun, Zengwei Wang, Boran Cao, Chi Zhang, Xiaoxia Fu, Wentao Zhao (Tsinghua Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 4B (T1-2) Communication Networks
Time: 10:05 - 11:45, Wednesday, January 22, 2025
Location: Room Uranus
Chair: Jiang Xu (Hong Kong Univ. of Science and Tech. (GZ), Hong Kong)

4B-1 (Time: 10:05 - 10:30)

Title	Physically Aware Wavelength-Routed Optical NoC Design for Customized Topologies with Parallel Switching Elements and Sequence-Based Models
Author	*Wei-Yao Kao, Tai-Jung Lin, Yao-Wen Chang (National Taiwan Univ., Taiwan)
Detailed information (abstract, keywords, etc)

4B-2 (Time: 10:30 - 10:55)

Title	Zipper: Latency-Tolerant Optimizations for High-Performance Buses
Author	*Shibo Chen (Univ. of Michigan, USA), Hailun Zhang (Univ. of Wisconsin, USA), Todd Austin (Univ. of Michigan, USA)
Detailed information (abstract, keywords, etc)

4B-3 (Time: 10:55 - 11:20)

Title	A Buffer Reservation Scheduling Strategy for Enhancing Performance of NoC Router Bypassing
Author	*Zixuan Liu, Yaoyao Ye (Shanghai Jiao Tong Univ., China)
Detailed information (abstract, keywords, etc)

4B-4 (Time: 11:20 - 11:45)

Title	RUNoC: Re-inject into the Underground Network to Alleviate Congestion in Large-Scale NoC
Author	*Xinghao Zhu, Jiyuan Bai, Zifeng Zhao, Qirong Yu (Fudan Univ., China), Gengsheng Chen (Fudan Univ./Jiashan Fudan Institute, China), Xiaofang Zhou (Fudan Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 4C (T2-2) Design and Optimization of Emerging Embedded Applications
Time: 10:05 - 11:45, Wednesday, January 22, 2025
Location: Room Venus
Chair: Fang-Jing Wu (National Taiwan Univ., Taiwan)

4C-1 (Time: 10:05 - 10:30)

Title	A Hierarchical Dataflow-Driven Heterogeneous Architecture for Wireless Baseband Processing
Author	*Limin Jiang, Yi Shi, Yintao Liu, Qingyu Deng, Siyi Xu, Yihao Shen, Fangfang Ye, Shan Cao, Zhiyuan Jiang (Shanghai Univ., China)
Detailed information (abstract, keywords, etc)

4C-2 (Time: 10:30 - 10:55)

Title	Exploiting Differential-Based Data Encoding for Enhanced Query Efficiency
Author	*Fangxin Liu, Zongwu Wang, Peng Xu, Shiyuan Huang, Li Jiang (Shanghai Jiao Tong Univ., China)
Detailed information (abstract, keywords, etc)

4C-3 (Time: 10:55 - 11:20)

Title	Automated Power-saving User-interfaces for Application Designers
Author	*Huan-Chun Yeh, Yu-Zheng Su, Chun-Han Lin (National Taiwan Normal Univ., Taiwan)
Detailed information (abstract, keywords, etc)

4C-4 (Time: 11:20 - 11:45)

Title	An Edge AI and Adaptive Embedded System Design for Agricultural Robotics Applications
Author	*Chun-Hsian Huang (National Changhua Univ. of Education, Taiwan), Zhi-Rui Chen, Huai-Shu Hsu (National Taitung Univ., Taiwan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 4D (T11-1) Verification and Testing in Machine Lerning Era
Time: 10:05 - 11:45, Wednesday, January 22, 2025
Location: Room Mars/Mercury
Chair: Michihiro Shintani (Kyoto Inst. of Tech., Japan)

4D-1 (Time: 10:05 - 10:30)

Title	AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
Author	*Zhiyuan Yan (Hong Kong Univ. of Science and Tech. (GZ), China), Wenji Fang, Mengming Li (Hong Kong Univ. of Science and Tech., Hong Kong), Min Li (Huawei Technologies, China), Shang Liu, Zhiyao Xie (Hong Kong Univ. of Science and Tech., Hong Kong), Hongce Zhang (Hong Kong Univ. of Science and Tech. (GZ), China)
Detailed information (abstract, keywords, etc)

4D-2 (Time: 10:30 - 10:55)

Title	Learning Gate-level Netlist Testability in the Presence of Unknowns through Graph Neural Networks
Author	*Thai-Hoang Nguyen, Youngjin Ju, Dongsub Yoon, Hyojin Choi (Samsung Electronics, Republic of Korea)
Detailed information (abstract, keywords, etc)

4D-3 (Time: 10:55 - 11:20)

Title	Efficient ML-Based Transient Thermal Prediction for 3D-ICs
Author	Yun-Feng Yang, *Wei-Shen Wang, Yung-Jen Lee, James Chien-Mo Li (National Taiwan Univ., Taiwan), Norman Chang, Akhilesh Kumar, Ying-Shiun Li, Jessica Yen, Lang Lin (Ansys, USA)
Detailed information (abstract, keywords, etc)

4D-4 (Time: 11:20 - 11:45)

Title	Device-Aware Test for Anomalous Charge Trapping in FeFETs
Author	*Sicong Yuan (Technische Univ. Delft, Netherlands), Changhao Wang (Politecnico di Torino, Italy), Moritz Fieback, Hanzhi Xun, Mottaqiallah Taouil (Technische Univ. Delft, Netherlands), Xiuyan Li, Danyang Chen, Lin Wang (Shanghai Jiao Tong Univ., China), Nicolò Bellarmino, Riccardo Cantoro (Politecnico di Torino, Italy), Said Hamdioui (Technische Univ. Delft, Netherlands)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 4E (T3-3) Hybrid/Co-Designed Near/In Memory Computing
Time: 10:05 - 11:45, Wednesday, January 22, 2025
Location: Innovation Hall
Chairs: Bokyung Kim (Rutgers Univ., USA), Zhong Sun (Peking Univ., China)

4E-1 (Time: 10:05 - 10:30)

Title	3D-METRO: Deploy Large-Scale Transformer Model on a Chip Using Transistor-Less 3D-Metal-ROM-Based Compute-in-Memory Macro
Author	Yiming Chen, *Xirui Du, Guodong Yin, Wenjun Tang, Yongpan Liu, Huazhong Yang, Xueqing Li (Tsinghua Univ., China)
Detailed information (abstract, keywords, etc)

4E-2 (Time: 10:30 - 10:55)

Title	HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads
Author	*Shubham Negi, Utkarsh Saxena, Deepika Sharma, Kaushik Roy (Purdue Univ., USA)
Detailed information (abstract, keywords, etc)

4E-3 (Time: 10:55 - 11:20)

Title	MDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory Processing
Author	*Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing (Shanghai Jiao Tong Univ., China)
Detailed information (abstract, keywords, etc)

4E-4 (Time: 11:20 - 11:45)

Title	A 24.65 TOPS/W@INT8 Hybrid Analog-Digital Multi-core SRAM CIM Macro with Optimal Weight Dividing and Resource Allocation Strategies
Author	*Yitong Zhou, Wente Yi, Sifan Sun, Wenjia Wang, Jinyu Bai, He Zhang (Beihang Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 4F (SS-4) ML for IC Design and Manufacturing: When Is It Real?
Time: 10:05 - 11:45, Wednesday, January 22, 2025
Chairs: Yibo Lin (Peking Univ., China), Youngsoo Shin (KAIST, Republic of Korea)

4F-1 (Time: 10:05 - 10:30)

Title	(Invited Paper) Use Cases and Deployment of ML in IC Physical Design
Author	Amur Ghose, *Andrew B. Kahng, Sayak Kundu, Yiting Liu, Bodhisatta Pramanik, Zhiang Wang, Dooseok Yoon (Univ. of California, San Diego, USA)
Detailed information (abstract, keywords, etc)

4F-2 (Time: 10:30 - 10:55)

Title	(Invited Paper) Leveraging Machine Learning Techniques to Enhance Traditional EDA Workflows
Author	Jinoh Cho, Jaekyung Im, Jaeseung Lee, Kyungjun Min, Seonghyeon Park, Jaemin Seo, Jongho Yoon, *Seokhyeong Kang (POSTECH, Republic of Korea)
Detailed information (abstract, keywords, etc)

4F-3 (Time: 10:55 - 11:20)

Title	(Invited Paper) ML-Assisted RF IC Design Enablement: the New Frontier of AI for EDA
Author	Hyunsu Chae, Song Hang Chai (Univ. of Texas, Austin, USA), Taiyun Chi (Rice Univ., USA), Sensen Li, *David Z. Pan (Univ. of Texas, Austin, USA)
Detailed information (abstract, keywords, etc)

4F-4 (Time: 11:20 - 11:45)

Title	(Invited Paper) ML for Computational Lithography: Practical Recipes
Author	*Youngsoo Shin (KAIST, Republic of Korea)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 1W CEDA 20th Anniversary Panel
Time: 12:00 - 13:00, Wednesday, January 22, 2025
Location: Innovation Hall and more
Organizer: Tsung-Yi Ho (Chinese Univ. of Hong Kong, Hong Kong), Panel Moderator: Yu Wang (Tsinghua Univ., China)

1W-1 (Time: 12:00 - 13:00)

Title	(Panel Discussion) CEDA 20th Anniversary Panel
Author	Panelists: Yao-Wen Chang (National Taiwan Univ., Taiwan), Kwang-Ting Cheng (Hong Kong Univ. of Science and Tech., Hong Kong), Shinji Kimura (Waseda Univ., Japan), Jeong-Taek Kong (Sungkyunkwan Univ., Republic of Korea)
Detailed information (abstract, etc)

[To Session Table]

Session 5A (T5-2) Innovations in Deep Learning and Neural Network Acceleration
Time: 13:15 - 15:20, Wednesday, January 22, 2025
Location: Room Saturn
Chair: Shinya Takamaeda Yamazaki (Univ. of Tokyo, Japan)

5A-1 (Time: 13:15 - 13:40)

Title	Hardware Acceleration of Kolmogorov–Arnold Network (KAN) for Lightweight Edge Inference
Author	Wei-Hsing Huang, Jianwei Jia, Yuyao Kong, Faaiq Waqar (Georgia Tech, USA), Tai-Hao Wen (National Tsing Hua Univ., Taiwan), Meng-Fan Chang (National Tsing Hua Univ./TSMC Corporate Research, Taiwan), *Shimeng Yu (Georgia Tech, USA)
Detailed information (abstract, keywords, etc)

5A-2 (Time: 13:40 - 14:05)

Title	SUArch: Accelerating Layer-wise N:M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device
Author	*Xilong Kang, Qingwen Wei (Southeast Univ., China), Ningyuan Li (Harbin Engineering Univ., China), Xingyu Xu, Hao Cai, Bo Liu (Southeast Univ., China)
Detailed information (abstract, keywords, etc)

5A-3 (Time: 14:05 - 14:30)

Title	FactorFlow: Mapping GEMMs on Spatial Architectures through Adaptive Programming and Greedy Optimization
Author	*Marco Ronzani, Cristina Silvano (Politecnico di Milano, Italy)
Detailed information (abstract, keywords, etc)

5A-4 (Time: 14:30 - 14:55)

Title	LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference
Author	Yanyue Xie (Northeastern Univ., USA), Zhengang Li (Adobe, USA), Dana Diaconu, Suranga Handagala, Miriam Leeser, *Xue Lin (Northeastern Univ., USA)
Detailed information (abstract, keywords, etc)

5A-5 (Time: 14:55 - 15:20)

Title	A Layer-wised Mixed-Precision CIM Accelerator with Bit-level Sparsity-aware ADCs for NAS-Optimized CNNs
Author	Haoxiang Zhou, Zikun Wei, Dingbang Liu, Liuyang Zhang (Southern Univ. of Science and Tech., China), Chenchen Ding (Univ. of Hong Kong, China), Jiaqi Yang (Southern Univ. of Science and Tech., China), Wei Mao (Xidian Univ., China), *Hao Yu (Southern Univ. of Science and Tech., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 5B (T7-2) Neuromorphic and Emerging Computing Techniques
Time: 13:15 - 15:20, Wednesday, January 22, 2025
Location: Room Uranus
Chair: Georgios Zervakis (Univ. of Patras, Greece)

5B-1 (Time: 13:15 - 13:40)

Title	HyCOMP: A Compiler for ANN-SNN Hybrid Accelerators
Author	Yitian Zhou, Yue Li, *Yang Hong (Shanghai Jiao Tong Univ., China)
Detailed information (abstract, keywords, etc)

5B-2 (Time: 13:40 - 14:05)

Title	NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks
Author	*Haomin Li, Fangxin Liu (Shanghai Jiao Tong Univ., China), Zewen Sun (Tianjin Univ., China), Zongwu Wang, Shiyuan Huang, Ning Yang, Li Jiang (Shanghai Jiao Tong Univ., China)
Detailed information (abstract, keywords, etc)

5B-3 (Time: 14:05 - 14:30)

Title	SCSC: Leveraging Sparsity and Fault-Tolerance for Energy-Efficient Spiking Neural Networks
Author	Bo Li, *Yue Liu, Wei Liu, Jinghai Wang, Xiao Huang, Zhiyi Yu, Shanlin Xiao (Sun Yat-sen Univ., China)
Detailed information (abstract, keywords, etc)

5B-4 (Time: 14:30 - 14:55)

Title	OpticalHDC: Ultra-fast Photonic Hyperdimensional Computing Accelerator
Author	*Jiaqi Liu (Hong Kong Univ. of Science and Tech., Hong Kong), Yiwen Ma (Chinese Academy of Sciences, China)
Detailed information (abstract, keywords, etc)

5B-5 (Time: 14:55 - 15:20)

Title	Design and In-training Optimization of Binary Search ADC for Flexible Classifiers
Author	*Paula Carolina Lozano Duarte (Karlsruhe Inst. of Tech., Germany), Florentia Afentaki, Georgios Zervakis (Univ. of Patras, Greece), Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 5C (T9-2) Package and PCB
Time: 13:15 - 14:55, Wednesday, January 22, 2025
Location: Room Venus
Chair: Pei-Yu Lee (Mediatek, Taiwan)

5C-1 (Time: 13:15 - 13:40)

Title	Paired-Spacing-Constrained Package Routing with Net Ordering Optimization
Author	Yi-Sian Ciou, *Ying-Jie Jiang, Yi-Yu Liu, Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan), Wen-Hao Liu (NVIDIA, Taiwan)
Detailed information (abstract, keywords, etc)

5C-2 (Time: 13:40 - 14:05)

Title	Hybrid Detour Refinement Strategy for Package Substrate Routing
Author	*Ding-Hsun Lin, Tsubasa Koyama, Yu-Jen Chen (National Tsing Hua Univ., Taiwan), Keng-Tuan Chang, Chih-Yi Huang, Chen-Chao Wang (Advanced Semiconductor Engineering, Taiwan), Tsung-Yi Ho (Chinese Univ. of Hong Kong, Hong Kong)
Detailed information (abstract, keywords, etc)

5C-3 (Time: 14:05 - 14:30)

Title	On Awareness of Offset-Via and Teardrop in Advanced Packaging Interconnect Synthesis
Author	*Hao-Ju Chang, Yu-Hung Chen, Hao-Wei Huang, Yihua Yeh, Hung-Ming Chen, Chien-Nan Jimmy Liu (National Yang Ming Chiao Tung Univ., Taiwan)
Detailed information (abstract, keywords, etc)

5C-4 (Time: 14:30 - 14:55)

Title	PCBAgent: An Agent-based Framework for High-Density Printed Circuit Board Placement
Author	*Lin Chen (The Hong Kong Univ. of Science and Tech./Huawei Noah’s Ark Lab, Hong Kong), Ran Chen, Shoubo Hu (Huawei Noah’s Ark Lab, Hong Kong), Xufeng Yao (The Chinese Univ. of Hong Kong/Huawei Noah’s Ark Lab, Hong Kong), Zhentao Tang, Shixiong Kai, Siyuan Xu (Huawei Noah’s Ark Lab, China), Mingxuan Yuan (Huawei Noah’s Ark Lab, Hong Kong), Jianye Hao (Huawei Noah’s Ark Lab, China), Bei Yu (Chinese Univ. of Hong Kong, Hong Kong), Jiang Xu (Hong Kong Univ. of Science and Tech. (GZ), China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 5D (T12-2) Logic Locking and Hardware Watermarking
Time: 13:15 - 14:55, Wednesday, January 22, 2025
Location: Room Mars/Mercury
Chairs: Daisuke Fujimoto (NAIST, Japan), Amin Rezaei (California State Univ., Long Beach, USA)

5D-1 (Time: 13:15 - 13:40)

Title	NoXLock: SiP Activation and Licensing through Obfuscated on-Chip Network and Fuzzy Traffic
Author	Md Saad Ul Haque, Azim Uddin, Jingbo Zhou (Univ. of Florida, USA), Hadi Mardani Kamali (Univ. of Central Florida, USA), Farimah Farahmandi, *Mark Tehranipoor (Univ. of Florida, USA)
Detailed information (abstract, keywords, etc)

5D-2 (Time: 13:40 - 14:05)

Title	K-Gate Lock: Multi-Key Logic Locking Using Input Encoding Against Oracle-Guided Attacks
Author	Kevin Lopez, *Amin Rezaei (California State Univ. Long Beach, USA)
Detailed information (abstract, keywords, etc)

5D-3 (Time: 14:05 - 14:30)

Title	A Hybrid Machine Learning and Numeric Optimization Approach to Analog Circuit Deobfuscation
Author	*Dipali Jain, Guangwei Zhao, Rajesh Datta, Kaveh Shamsi (Univ. of Texas, Dallas, USA)
Detailed information (abstract, keywords, etc)

5D-4 (Time: 14:30 - 14:55)

Title	RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework
Author	*Kun Wang, Kaiyan Chang, Mengdi Wang, Xingqi Zou, Haobo Xu, Yinhe Han, Ying Wang (Chinese Academy of Sciences, China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 5E (T4.1-2) AI-Driven Innovative Design Methods
Time: 13:15 - 15:20, Wednesday, January 22, 2025
Location: Innovation Hall
Chair: Jaeduk Han (Hanyang Univ., Republic of Korea)

5E-1 (Time: 13:15 - 13:40)

Title	LIBMixer: An all-MLP Architecture for Cell Library Characterization towards Design Space Optimization
Author	*Jaeseung Lee, Sunggyu Jang, Jakang Lee, Seokhyeong Kang (Postech, Republic of Korea)
Detailed information (abstract, keywords, etc)

5E-2 (Time: 13:40 - 14:05)

Title	DefectTrackNet: Efficient Root Cause Analysis of Wafer Defects in Semiconductor Manufacturing Using a Lightweight CNN-Transformer Architecture
Author	*Lichao Zeng (Univ. of Science and Tech. of China, China), Zhouzhouzhou Mei (Zhejiang Univ., China), Zhongyu Shi (Univ. of Science and Tech. of China, China), Yining Chen (Zhejiang Univ., China)
Detailed information (abstract, keywords, etc)

5E-3 (Time: 14:05 - 14:30)

Title	Hybrid Compact Modeling Strategy: A Fully-Automated and Accurate Compact Model with Physical Consistency
Author	*JinYoung Choi, Hyunjoon Jeong, Jeong-Taek Kong, SoYoung Kim (Sungkyunkwan Univ., Republic of Korea)
Detailed information (abstract, keywords, etc)

5E-4 (Time: 14:30 - 14:55)

Title	CAR-Net: Solving Electrical Crosstalk Problem in Capacitive Sensing Array
Author	*Qinghang Zhao, Tao Li (Xidian Univ., China)
Detailed information (abstract, keywords, etc)

5E-5 (Time: 14:55 - 15:20)

Title	PC-Opt: Partition and Conquest-based Optimizer using Multi-Agents for Complex Analog Circuits
Author	*Youngchang Choi, Sejin Park, Ho-jin Lee, Kyongsu Lee, Jae-Yoon Sim, Seokhyeong Kang (POSTECH, Republic of Korea)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 5F (DF-1) Quantum Computing
Time: 13:15 - 14:30, Wednesday, January 22, 2025
Organizer: Takatsugu Ono (Kyushu Univ., Japan), Chair: Chihiro Yoshimura (Hitachi, Japan)

5F-1 (Time: 13:15 - 13:40)

Title	(Designers' Forum) Design of Superconducting Quantum Computers: Similarity and Dissimilarity
Author	*Yutaka Tabuchi (RIKEN Center for Quantum Computing, Japan)
Detailed information (abstract, etc)

5F-2 (Time: 13:40 - 14:05)

Title	(Designers' Forum) Challenges in Developing Practical Qubit Control Systems
Author	*Takefumi Miyoshi (QuEL/QIQB Osaka Univ./e-trees.Japan, Japan)
Detailed information (abstract, etc)

5F-3 (Time: 14:05 - 14:30)

Title	(Designers' Forum) A Layered Approach to Quantum Computing Software Platforms for the FTQC Era
Author	*Toru Kawakubo (QunaSys, Japan)
Detailed information (abstract, etc)

[To Session Table]

Session 6A (SS-5) Beyond Digital: Advancing Design Automation for Physical Computing Systems
Time: 15:40 - 17:20, Wednesday, January 22, 2025
Location: Room Saturn
Chair: Antonino Tumeo (PNNL, USA)

6A-1 (Time: 15:40 - 16:05)

Title	(Invited Paper) AI-Guided Codesign for Novel Computing Paradigms
Author	*Suma George Cardwell, J. Darby Smith (Sandia National Labs, USA), Karan Patel (Univ. of Tennessee, Knoxville, USA), Andrew Maicke, Jared Arzate, Samuel Liu, Jaesuk Kwon (Univ. of Texas, Austin, USA), Christopher R. Allemang, Douglas C. Crowder, Shashank Misra (Sandia National Labs, USA), Frances S. Chance (Sandia National Laboratories, USA, USA), Catherine D. Schuman (Univ. of Tennessee, Knoxville, USA), Jean Anne Incorvia (Univ. of Texas, Austin, USA), James B. Aimone (Sandia National Labs, USA)
Detailed information (abstract, keywords, etc)

6A-2 (Time: 16:05 - 16:30)

Title	(Invited Paper) Towards Design Optimization of Analog Compute Systems
Author	*Sara Achour (Stanford Univ., USA)
Detailed information (abstract, keywords, etc)

6A-3 (Time: 16:30 - 16:55)

Title	(Invited Paper) Nature-GL: A Revolutionary Learning Paradigm Unleashing Nature's Power in Real-World Spatial-Temporal Graph Learning
Author	Chuan Liu, Chunshu Wu, Ruibing Song (Univ. of Rochester, USA), Yousu Chen, Ang Li (Pacific Northwest National Laboratory, USA), Michael Huang, *Tony (Tong) Geng (Univ. of Rochester, USA)
Detailed information (abstract, keywords, etc)

6A-4 (Time: 16:55 - 17:20)

Title	(Invited Paper) ChemComp: A Compilation Framework for Computing with Chemical Reaction Networks
Author	Nicolas Bohm Agostini, Connah Johnson, William Cannon, *Antonino Tumeo (Pacific Northwest National Laboratory, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 6B (T9-3) Floorplan and Placement
Time: 15:40 - 17:45, Wednesday, January 22, 2025
Location: Room Uranus
Chair: Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan)

6B-1 (Time: 15:40 - 16:05)

Title	PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation
Author	Eunsol Jeong, Taewhan Kim (Seoul National Univ., Republic of Korea), *Heechun Park (Ulsan National Inst. of Science and Tech., Republic of Korea)
Detailed information (abstract, keywords, etc)

6B-2 (Time: 16:05 - 16:30)

Title	FTAFP: A Feedthrough-Aware Floorplanner for Hierarchical Design of Large-Scale SoCs
Author	Zirui Li, *Kanglin Tian, Jianwang Zhai, Zixuan Li (Beijing Univ. of Posts and Telecommunications, China), Shixiong Kai, Siyuan Xu (Huawei Noah's Ark Lab, China), Bei Yu (Chinese Univ. of Hong Kong, Hong Kong), Kang Zhao (Beijing Univ. of Posts and Telecommunications, China)
Detailed information (abstract, keywords, etc)

6B-3 (Time: 16:30 - 16:55)

Title	Mixed-Size Placement Prototyping Based on Reinforcement Learning with Semi-Concurrent Optimization
Author	*Cheng-Yu Chiang, Yi-Hsien Chiang, Chao-Chi Lan, Yang Hsu, Che-Ming Chang, Shao-Chi Huang, Sheng-Hua Wang, Yao-Wen Chang (National Taiwan Univ., Taiwan), Hung-Ming Chen (National Yang Ming Chiao Tung Univ., Taiwan)
Detailed information (abstract, keywords, etc)

6B-4 (Time: 16:55 - 17:20)

Title	ThePlace: Thermal-Aware Placement With Operator Learning-Based Ultra-Fast Simulator
Author	*Xinfei Liu (Univ. of Science and Tech. of China, China), Siting Liu, Bei Yu (Chinese Univ. of Hong Kong, Hong Kong), Song Chen, Qi Xu (Univ. of Science and Tech. of China, China)
Detailed information (abstract, keywords, etc)

6B-5 (Time: 17:20 - 17:45)

Title	An MIP-based Force-directed Large Scale Placement Refinement Algorithm
Author	*Zewen Li, Ke Tang (Nanjing Univ., China), Lang Feng (Sun Yat-sen Univ., China), Zhongfeng Wang (Nanjing Univ./Sun Yat-sen Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 6C (T13-1) Let’s Quantumize: Welcome to the World of Quantum
Time: 15:40 - 16:55, Wednesday, January 22, 2025
Location: Room Venus
Chairs: Chun-Yi Lee (National Taiwan Univ., Taiwan), Ulf Schlichtmann (Tech. Univ. of Munich, Germany)

6C-1 (Time: 15:40 - 16:05)

Title	IC-D²S: A Hybrid Ising-Classical-Machines Data-Driven QUBO Solver Method
Author	Armin Abdollahi, Mehdi Kamal, *Massoud Pedram (Univ. of Southern California, USA)
Detailed information (abstract, keywords, etc)

6C-2 (Time: 16:05 - 16:30)

Title	Compilation for Dynamically Field-Programmable Qubit Arrays with Efficient and Provably Near-Optimal Scheduling
Author	Daniel Bochen Tan (Univ. of California, Los Angeles/Harvard Univ., USA), Wan-Hsuan Lin, *Jason Cong (Univ. of California, Los Angeles, USA)
Detailed information (abstract, keywords, etc)

6C-3 (Time: 16:30 - 16:55)

Title	Back-end-aware Fault-tolerant Quantum Oracle Synthesis
Author	*Mingfei Yu, Alessandro Tempia Calvino (EPFL, Switzerland), Mathias Soeken (Microsoft Quantum, Switzerland), Giovanni De Micheli (EPFL, Switzerland)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 6D (T10-1) Innovative Techniques for Energy-Efficient and Reliable Hardware Systems
Time: 15:40 - 17:45, Wednesday, January 22, 2025
Location: Room Mars/Mercury
Chairs: Zhiyao Xie (Hong Kong Univ. of Science and Tech., Hong Kong), Qi Sun (Zhejiang Univ., China), Shanshi Huang (Hong Kong Univ. of Science and Tech. (GZ), China)

6D-1 (Time: 15:40 - 16:05)

Title	FEI: Fusion Processing of Sensing Energy and Information for Self-Sustainable Infrared Smart Vision System
Author	*Haijin Su (Beijing Jiaotong Univ., China), Xin Hong (Beijing Univ. of Tech., China), Maimaiti Nazhamaiti (Tsinghua Univ., China), Ce Zhang (Hong Kong Univ. of Science and Tech., Hong Kong), Li Luo (Beijing Jiaotong Univ., China), Qi Wei (Tsinghua Univ., China), Zheyu Liu (MakeSens AI, China), Wenjie Deng, Yongzhe Zhang (Beijing Univ. of Tech., China), Fei Qiao (Tsinghua Univ., China)
Detailed information (abstract, keywords, etc)

6D-2 (Time: 16:05 - 16:30)

Title	WITCH: WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth Memory
Author	Seoyoon Jang, *Sangouk Jeon, Kwanghyun Shin, Dongkwon Lee (Seoul National Univ., Republic of Korea), Hankyu Chi, Wookjin Shin, Changhyun Pyo (SK hynix, Republic of Korea), Jaeha Kim, Dongsuk Jeon (Seoul National Univ., Republic of Korea)
Detailed information (abstract, keywords, etc)

6D-3 (Time: 16:30 - 16:55)

Title	Compact Interleaved Thermal Control for Improving Throughput and Reliability of Networks-on-Chip
Author	*Tong Cheng, Zirui Xu, Xinyi Li, Li Li, Yuxiang Fu (Nanjing Univ., China)
Detailed information (abstract, keywords, etc)

6D-4 (Time: 16:55 - 17:20)

Title	E-QUARTIC: Energy Efficient Edge Ensemble of Convolutional Neural Networks for Resource-Optimized Learning
Author	Le Zhang, Onat Gungor, *Flavio Ponzina, Tajana Rosing (Univ. of California, San Diego, USA)
Detailed information (abstract, keywords, etc)

6D-5 (Time: 17:20 - 17:45)

Title	Hardware Error Detection with In-Situ Monitoring of Control Flow-Related Specifications
Author	*Tomonari Tanaka (Kyoto Univ., Japan), Takumi Uezono (Hitachi, Japan), Kohei Suenaga, Masanori Hashimoto (Kyoto Univ., Japan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 6E (T4.1-3) Leveraging Large Language Models in Hardware Design
Time: 15:40 - 17:45, Wednesday, January 22, 2025
Location: Innovation Hall
Chair: Cong Hao (Georgia Tech, USA)

6E-1 (Time: 15:40 - 16:05)

Title	LLSM: LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting, Hybrid Embedding and AIG-tailored Acceleration
Author	*Shan Huang, Jinhao Li, Zhen Yu, Jiancai Ye, Jiaming Xu, Ningyi Xu, Guohao Dai (Shanghai Jiao Tong Univ., China)
Detailed information (abstract, keywords, etc)

6E-2 (Time: 16:05 - 16:30)

Title	OPL4GPT: An Application Space Exploration of Optimal Programming Language for Hardware Design by LLM
Author	Kimia Tasnia, *Sazadur Rahman (Univ. of Central Florida, USA)
Detailed information (abstract, keywords, etc)

6E-3 (Time: 16:30 - 16:55)

Title	Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis
Author	Jiahao Gai (Univ. of Cambridge/Imperial College London, UK), *Hao Chen (Imperial College London, UK), Zhican Wang (Shanghai Jiaotong Univ., China), Hongyu Zhou (Univ. of Sydney, Australia), Wanru Zhao, Nicholas Lane (Univ. of Cambridge, UK), Hongxiang Fan (Imperial College London/Univ. of Cambridge, UK)
Detailed information (abstract, keywords, etc)

6E-4 (Time: 16:55 - 17:20)

Title	MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs
Author	*Manar Abdelatty, Jingxiao Ma, Sherief Reda (Brown Univ., USA)
Detailed information (abstract, keywords, etc)

6E-5 (Time: 17:20 - 17:45)

Title	SimEval: Investigating the Similarity Obstacle in LLM-based Hardware Code Generation
Author	Mohammad Akyash, *Hadi Mardani Kamali (Univ. of Central Florida, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 6F (DF-2) Advanced Sensor Technologies and Sensor Fusion
Time: 15:40 - 16:55, Wednesday, January 22, 2025
Organizer: Takashi Moue (Sony Semiconductor Solutions, Japan), Chair: Koichiro Yamashita (Fujitsu, Japan)

6F-1 (Time: 15:40 - 16:05)

Title	(Designers' Forum) Human Sensing Using Millimeter Wave Radar
Author	*Hongchun Li, Jun Tian, Qian Zhao, Lili Xie, Yingju Xia (Fujitsu Research & Development Center, China)
Detailed information (abstract, etc)

6F-2 (Time: 16:05 - 16:30)

Title	(Designers' Forum) 3D-Stacked 1Megapixel Time-Gated SPAD Image Sensor with 2D Interactive Gating Network for Image Alignment-Free Sensor Fusion
Author	Kazuhiro Morimoto, Naoki Isoda, Hiroshi Sekine, Tomoya Sasago, Yu Maehashi, Satoru Mikajiri, Kenzo Tojima, Mahito Shinohara, Ayman Abdelghafar, Hiroyuki Tsuchiya, Kazuma Inoue, Satoshi Omodani, *Kazuma Chida, Alice Ehara, Junji Iwata, Tetsuya Itano, Yasushi Matsuno, Katsuhito Sakurai, Takeshi Ichikawa (Canon, Japan)
Detailed information (abstract, etc)

6F-3 (Time: 16:30 - 16:55)

Title	(Designers' Forum) 1.22µm-pixel Back-illuminated Stacked RGB Hybrid Event-based Vision Sensor
Author	*Kazutoshi Kodama, Yusuke Sato, Yuhi Yorikado, Kyoji Mizoguchi, Takahiro Miyazaki, Masahiro Tsukamoto, Yoshihisa Matoba, Hirotaka Shinozaki, Atsumi Niwa, Tetsuji Yamaguchi (Sony Semiconductor Solutions, Japan), Christian Braendli (Sony Advanced Visual Sensing, Switzerland), Hayato Wakabayashi, Yusuke Oike (Sony Semiconductor Solutions, Japan)
Detailed information (abstract, etc)

Thursday, January 23, 2025

[To Session Table]

Session 3K Keynote Session III
Time: 9:00 - 9:45, Thursday, January 23, 2025
Location: Miraikan Hall
Chair: Atsushi Takahashi (Institute of Science Tokyo, Japan)

3K-1

Title	(Keynote Address) In-Memory Computing-based Deep Learning Accelerators: An Overview and Future Prospects
Author	Abu Sebastian (IBM Research Europe - Zurich, Switzerland)
Detailed information (abstract, etc)

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Session 7A (T1-3) Accelerator Design Methodologies
Time: 10:05 - 11:45, Thursday, January 23, 2025
Location: Room Saturn
Chair: Yaoyao Ye (Shanghai Jiao Tong Univ., China)

7A-1 (Time: 10:05 - 10:30)

Title	In-Storage Read-Centric Seed Location Filtering Using 3D-NAND Flash for Genome Sequence Analysis
Author	You-Kai Zheng (National Taiwan Univ., Taiwan), *Ming-Liang Wei (National Taiwan Univ./Macronix, Taiwan), Hsiang-Yun Cheng (Academia Sinica, Taiwan), Chia-Lin Yang, Ming-Hsiang Tsai, Chia-Chun Chien, Yuan-Hao Zhong (National Taiwan Univ., Taiwan), Po-Hao Tseng, Hsiang-Pang Li (Macronix, Taiwan)
Detailed information (abstract, keywords, etc)

7A-2 (Time: 10:30 - 10:55)

Title	A Synthesis Methodology for Intelligent Memory Interfaces in Accelerator Systems
Author	*Ankur Limaye, Nicolas Bohm Agostini, Claudio Barone, Vito Giovanni Castellana (Pacific Northwest National Laboratory, USA), Michele Fiorito, Fabrizio Ferrandi (Politecnico di Milano, Italy), Andres Marquez, Antonino Tumeo (Pacific Northwest National Laboratory, USA)
Detailed information (abstract, keywords, etc)

7A-3 (Time: 10:55 - 11:20)

Title	Towards Efficient Data Parallelism on Spatial CGRA via Constraint Satisfaction and Graph Coloring
Author	Yuan Dai, *Xuchen Gao, Chen Shen, Bingbing Peng, Wenbo Yin, Wai-Shing Luk, Lingli Wang (Fudan Univ., China)
Detailed information (abstract, keywords, etc)

7A-4 (Time: 11:20 - 11:45)

Title	HyperG: Multilevel GPU-Accelerated k-way Hypergraph Partitioner
Author	Wan Luan Lee, Dian-Lun Lin, Cheng-Hsiang Chiu (Univ. of Wisconsin at Madison, USA), Ulf Schlichtmann (TUM, Germany), *Tsung-Wei Huang (Univ. of Wisconsin at Madison, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 7B (T5-3) Advanced Architectures for Scientific and Edge Computing
Time: 10:05 - 11:45, Thursday, January 23, 2025
Location: Room Uranus
Chair: Hao Yu (SUSTech, China)

7B-1 (Time: 10:05 - 10:30)

Title	Exploring and Exploiting Runtime Reconfigurable Floating Point Precision in Scientific Computing: a Case Study for Solving PDEs
Author	*Cong Hao (Georgia Tech, USA)
Detailed information (abstract, keywords, etc)

7B-2 (Time: 10:30 - 10:55)

Title	A Holistic FPGA Architecture Exploration Framework for Deep Learning Acceleration
Author	*Jiadong Zhu, Dongsheng Zuo, Yuzhe Ma (Hong Kong Univ. of Science and Tech. (GZ), China)
Detailed information (abstract, keywords, etc)

7B-3 (Time: 10:55 - 11:20)

Title	OpenGeMM: A High-Utilization GeMM Accelerator Generator with Lightweight RISC-V Control and Tight Memory Coupling
Author	*Xiaoling Yi, Ryan Antonio, Joren Dumoulin, Jiacong Sun, Josse Van Delm (KU Leuven, Belgium), Guilherme Paim (KU Leuven/INESC-ID, Belgium), Marian Verhelst (KU Leuven, Belgium)
Detailed information (abstract, keywords, etc)

7B-4 (Time: 11:20 - 11:45)

Title	Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations
Author	*Qijun Zhang, Zhiyao Xie (Hong Kong Univ. of Science and Tech., Hong Kong)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 7C (T6-2) The Science of Light: the New Advancement of Photonic Computing
Time: 10:05 - 11:45, Thursday, January 23, 2025
Location: Room Venus
Chairs: Ryosuke Matsuo (Univ. of Tokyo, Japan), Yuanqing Cheng (Beihang Univ., China)

7C-1 (Time: 10:05 - 10:30)

Title	An Efficient General-Purpose Optical Accelerator for Neural Networks
Author	*Sijie Fei, Amro Eldebiky (Techinical Univ. of Munich, Germany), Grace Li Zhang (Technical Univ. of Darmstadt, Germany), Bing Li (Univ. of Siegen, Germany), Ulf Schlichtmann (Techinical Univ. of Munich, Germany)
Detailed information (abstract, keywords, etc)

7C-2 (Time: 10:30 - 10:55)

Title	Zero-Shot Automated Circuit Topology Search for Pareto-Optimal Photonic Tensor Cores
Author	Ziyang Jiang, Pingchuan Ma (Arizona State Univ., USA), Meng Zhang, Rena Huang (Rensselaer Polytechnic Institute, USA), *Jiaqi Gu (Arizona State Univ., USA)
Detailed information (abstract, keywords, etc)

7C-3 (Time: 10:55 - 11:20)

Title	Reuse and Blend: A Weight-Sharing Energy-Efficient Optical Neural Network
Author	*Bo Xu, Yuetong Fang (Hong Kong Univ. of Science and Tech. (GZ), China), Shaoliang Yu (Zhejiang Lab, China), Renjing Xu (Hong Kong Univ. of Science and Tech. (GZ), China)
Detailed information (abstract, keywords, etc)

7C-4 (Time: 11:20 - 11:45)

Title	PhotonGraph: High-performance Photonic Graph Processing Accelerator
Author	*Jiaqi Liu, Xianbin Li (Hong Kong Univ. of Science and Tech., Hong Kong)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 7D (T8-2) From Math to Circuits
Time: 10:05 - 11:20, Thursday, January 23, 2025
Location: Room Mars/Mercury
Chairs: Oliver Keszöcze (Tech. Univ. of Denmark, Denmark), Yukio Miyasaka (UC Berkeley, USA)

7D-1 (Time: 10:05 - 10:30)

Title	An Algebraic Approach to Partial Synthesis of Arithmetic Circuits
Author	Bhavani Sampathkumar, Ritaja Das, Bailey Martin (Univ. of Utah, USA), Florian Enescu (Georgia State Univ., USA), *Priyank Kalla (Univ. of Utah, USA)
Detailed information (abstract, keywords, etc)

7D-2 (Time: 10:30 - 10:55)

Title	Hardware Synthesizable Exceptions using Continuations
Author	*Paul Teng (McGill Univ., Canada), Christophe Dubach (McGill Univ./MILA, Canada)
Detailed information (abstract, keywords, etc)

7D-3 (Time: 10:55 - 11:20)

Title	Area-Oriented Optimization After Standard-Cell Mapping
Author	*Andrea Costamagna, Alessandro Tempia Calvino (EPFL, Switzerland), Alan Mishchenko (UC Berkeley, USA), Giovanni De Micheli (EPFL, Switzerland)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 7E (T4.2-3) Innovative Techniques in AI Model Optimization and Training
Time: 10:05 - 11:20, Thursday, January 23, 2025
Location: Innovation Hall
Chairs: Dongsuk Jeon (Seoul National Univ., Republic of Korea), Ik-Joon Chang (Kyung Hee Univ.)

7E-1 (Time: 10:05 - 10:30)

Title	ROBIN: A Novel Framework for Accelerating Robust Multi-Variant Training
Author	*Yan Wang, Xingbin Wang, Yulan Su, Sisi Zhang, Zechao Lin, Dan Meng, Rui Hou (Chinese Academy of Sciences, China)
Detailed information (abstract, keywords, etc)

7E-2 (Time: 10:30 - 10:55)

Title	Dual-branch cross-modal fusion with local-to-global learning for UAV object detection
Author	Binyi Fang, *Yixin Yang, Jingjing Chang, Ziyang Gao, Hai-Bao Chen (Shanghai Jiao Tong Univ., China)
Detailed information (abstract, keywords, etc)

7E-3 (Time: 10:55 - 11:20)

Title	H4H: Hybrid Convolution-Transformer Architecture Search for NPU-CIM Heterogeneous Systems for AR/VR Applications
Author	*Yiwei Zhao (Carnegie Mellon Univ., USA), Jinhui Chen (Reality Labs Research, Meta, USA), Sai Qian Zhang (New York Univ., USA), Syed Shakib Sarwar, Kleber Hugo Stangherlin, Jorge Tomas Gomez, Jae-Sun Seo, Barbara De Salvo, Chiao Liu (Reality Labs Research, Meta, USA), Phillip B. Gibbons (Carnegie Mellon Univ., USA), Ziyun Li (Reality Labs Research, Meta, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 7F (SS-6) Rapidus' Initiatives to Half Semiconductor Development Time
Time: 10:05 - 11:20, Thursday, January 23, 2025
Chair: Koki Tsurusaki (Rapidus, Japan)

7F-1 (Time: 10:05 - 10:30)

Title	(Invited Paper) Raads: Rapidus's AI/ML based assisted design flow to reduce design period halved
Author	*Koki Tsurusaki (Rapidus, Japan)
Detailed information (abstract, keywords, etc)

7F-2 (Time: 10:30 - 10:55)

Title	(Invited Paper) DMCO: A Strategy for Design-Manufacturing Co-optimization
Author	*Masaharu Kobayashi (Rapidus, Japan)
Detailed information (abstract, keywords, etc)

7F-3 (Time: 10:55 - 11:20)

Title	(Invited Paper) Advanced Packaging Technology and Design Methodology for Next Generation Chiplets
Author	*Hideki Sasaki (Rapidus, Japan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 8A (T1-4) System Level Modelling & Optimization
Time: 13:15 - 14:55, Thursday, January 23, 2025
Location: Room Saturn
Chair: Zhe Lin (Sun Yat-sen Univ., China)

8A-1 (Time: 13:15 - 13:40)

Title	FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling
Author	*Qijun Zhang, Mengming Li, Yao Lu, Zhiyao Xie (Hong Kong Univ. of Science and Tech., Hong Kong)
Detailed information (abstract, keywords, etc)

8A-2 (Time: 13:40 - 14:05)

Title	DISS: A Novel Data Invalidation Scheme for Swap-Data on Flash Storage Systems
Author	*Dingcui Yu, Longfei Luo, Han Wang (East China Normal Univ., China), Yina Lv (City Univ. of Hong Kong, Hong Kong), Liang Shi (East China Normal Univ., China)
Detailed information (abstract, keywords, etc)

8A-3 (Time: 14:05 - 14:30)

Title	Response Range Optimization for Run-Time Requirement Enforcement on MPSoCs
Author	*Khalil Esper, Stefan Wildermann, Jürgen Teich (Friedrich-Alexander-Univ. Erlangen-Nürnberg, Germany)
Detailed information (abstract, keywords, etc)

8A-4 (Time: 14:30 - 14:55)

Title	TL-CSE: Microarchitecture-Compiler Co-design Space Exploration via Transfer Learning
Author	*Zheng Wu, Jinyi Shen, Xuyang Zhao, Changxu Liu, Li Shang, Fan Yang (Fudan Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 8B (T5-4) Emerging Trends in Reconfigurable and Compute-in-Memory
Time: 13:15 - 14:55, Thursday, January 23, 2025
Location: Room Uranus
Chair: Guohao Dai (Shanghai Jiao Tong Univ., China)

8B-1 (Time: 13:15 - 13:40)

Title	RISC-V Driven Orchestration of Vector Processing Units and eFlash Compute-in-Memory Arrays for Fast and Accurate Keyword Spotting
Author	*Gunil Kang (Korea Univ. & Samsung Electronics, Republic of Korea), Dahoon Park, Hojin Lee (Korea Univ., Republic of Korea), Sangwoo Jung (DGIST, Republic of Korea), Jiyong Park (Korea Univ., Republic of Korea), Jung Gyu Min, Youngjoo Lee (POSTECH, Republic of Korea), Jaeha Kung (Korea Univ., Republic of Korea)
Detailed information (abstract, keywords, etc)

8B-2 (Time: 13:40 - 14:05)

Title	Efficient Arbitrary Precision Acceleration for Large Language Models on GPU Tensor Cores
Author	*Shaobo Ma, Chao Fang, Haikuo Shao, Zhongfeng Wang (Nanjing Univ., China)
Detailed information (abstract, keywords, etc)

8B-3 (Time: 14:05 - 14:30)

Title	Large-Scale AGV Routing Based on Multi-FPGA SQA Acceleration
Author	*Thinh Nguyen Quang, Kosuke Matsuyama, Keisuke Shimizu, Hiroki Sugano, Eiji Kurimoto (Sharp, Japan), Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masayuki Ohzeki (Tohoku Univ., Japan)
Detailed information (abstract, keywords, etc)

8B-4 (Time: 14:30 - 14:55)

Title	A Data-Driven Approach to Dataflow-Aware Online Scheduling for Graph Neural Network Inference
Author	Pol Puigdemont (Univ. Politècnica de Catalunya (UPC), Spain), *Enrico Russo (Univ. of Catania, Italy), Axel Wassington, Abhijit Das, Sergi Abadal (Univ. Politècnica de Catalunya (UPC), Spain), Maurizio Palesi (Univ. of Catania, Italy)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 8C (T3-4) Adaptive and Flexible Memory Architecture
Time: 13:15 - 14:55, Thursday, January 23, 2025
Location: Room Venus
Chairs: Chao Wu (Nanjing Univ. of Science and Tech., China), Yuzhe Ma (Hong Kong Univ. of Science and Tech. (GZ), China)

8C-1 (Time: 13:15 - 13:40)

Title	FPBA: Flexible Percentile-Based Allocation for Multiple-Bits-Per-Cell RRAM
Author	*Junfei Liu (Univ. of Rochester/Univ. of California, San Diego, USA), Anson Kahng (Univ. of Rochester, USA)
Detailed information (abstract, keywords, etc)

8C-2 (Time: 13:40 - 14:05)

Title	Mpache: Interaction Aware Multi-level Cache Bypassing on GPUs
Author	*Mengyue Xi, Tianyu Guo, Xuanteng Huang, Zejia Lin, Xianwei Zhang (Sun Yat-sen Univ., China)
Detailed information (abstract, keywords, etc)

8C-3 (Time: 14:05 - 14:30)

Title	A Novel Mixed-Signal Flash-based Finite Impulse Response (FFIR) Filter for IoT Applications
Author	Cheng-Yen Lee, *Sunil P. Khatri (Texas A&M Univ., USA), Ali Ghrayeb (Texas A&M Univ. at Qatar, Qatar)
Detailed information (abstract, keywords, etc)

8C-4 (Time: 14:30 - 14:55)

Title	TRIFP-DCIM: A Toggle-Rate-Immune Floating-point Digital Compute-in-Memory Design with Adaptive-Asymmetric Compute-Tree
Author	Xing Wang, Tianhui Jiao, Shaochen Li, Yuchen Ma, *Zhican Zhang, Zhichao Liu, Xi Chen, Xin Si (Southeast Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 8D (T9-4) Reliability in Physical Design
Time: 13:15 - 14:55, Thursday, January 23, 2025
Location: Room Mars/Mercury
Chair: Wenjian Yu (Tsinghua Univ., China)

8D-1 (Time: 13:15 - 13:40)

Title	Revisit MBFF: Efficient Early-Stage Multi-bit Flip-Flops Clustering with Physical and Timing Awareness
Author	*Yichen Cai, Linyu Zhu (Shanghai Jiao Tong Univ., China), Xinfei Guo (Shanghai Jiao Tong Univ./State Key Laboratory of Integrated Chips and Systems (SKLICS), China)
Detailed information (abstract, keywords, etc)

8D-2 (Time: 13:40 - 14:05)

Title	Pin Access-aware Multiple Via Pillar Co-Design for Routability Optimization
Author	*Man-Ling Hong, Ying-Jie Jiang, Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan)
Detailed information (abstract, keywords, etc)

8D-3 (Time: 14:05 - 14:30)

Title	ResCap: Fast-yet-Accurate Capacitance Extraction for Standard Cell Design by Physics-Guided Machine Learning
Author	Jiun-Cheng Tsai, *Hsuan-Ming Huang, Wei-Min Hsu, Pei-Ting Lee, Jen-Hang Yang, Heng-Liang Huang (MediaTek, Taiwan), Yen-Ju Su, Charles H. -P. Wen (NYCU, Taiwan)
Detailed information (abstract, keywords, etc)

8D-4 (Time: 14:30 - 14:55)

Title	CPONoC: Critical Path-aware Physical Implementation for Optical Networks-on-Chip
Author	Yan-Ting Chen (National Taiwan Univ. of Science and Tech., Taiwan), Zhidan Zheng (Tech. Univ. of Munich, Germany), *Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan), Tsun-Ming Tseng, Ulf Schlichtmann (Tech. Univ. of Munich, Germany)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 8E (SS-7) Hardware Authenticity towards a Trustworthy Society
Time: 13:15 - 14:55, Thursday, January 23, 2025
Location: Innovation Hall
Chairs: Jun Shiomi (Osaka Univ., Japan), Michihiro Shintani (Kyoto Inst. of Tech., Japan)

8E-1 (Time: 13:15 - 13:40)

Title	(Invited Paper) Hardware Trojan Detection by Fine-grained Power Domain Partitioning
Author	*Takahiro Ishikawa, Kose Yokooji, Yoshihiro Midoh, Noriyuki Miura (Osaka Univ., Japan), Michihiro Shintani (Kyoto Inst. of Tech., Japan), Jun Shiomi (Osaka Univ., Japan)
Detailed information (abstract, keywords, etc)

8E-2 (Time: 13:40 - 14:05)

Title	(Invited Paper) Cryo-HT: Hardware Trojan Activated at Cryogenic Temperatures
Author	*Ayano Takaya, Ryuichi Nakajima (Kyoto Inst. of Tech., Japan), Jun Shiomi (Osaka Univ., Japan), Michihiro Shintani (Kyoto Inst. of Tech., Japan)
Detailed information (abstract, keywords, etc)

8E-3 (Time: 14:05 - 14:30)

Title	(Invited Paper) Current Consumption Model for More Efficient Side-channel Tolerant Design at FPGA Design Stage
Author	*Daisuke Fujimoto, Yuichi Hayashi (NAIST, Japan)
Detailed information (abstract, keywords, etc)

8E-4 (Time: 14:30 - 14:55)

Title	(Invited Paper) White-box logic obfuscation: A Transparent Solution to Hardware Piracy and Reverse Engineering
Author	Leon Li, *Alex Orailoglu (Univ. of California, San Diego, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 8F (DF-3) Extending the Limits of Classical Computers using Emerging Device and Circuit Technology
Time: 13:15 - 14:30, Thursday, January 23, 2025
Organizer: Chihiro Yoshimura (Hitachi, Japan), Chair: Takatsugu Ono (Kyushu Univ., Japan)

8F-1 (Time: 13:15 - 13:40)

Title	(Designers' Forum) Amorphica: Fully Connected Metamorphic Annealing Processor with Programmable Optimization Strategy
Author	*Kazushi Kawamura (Institute of Science Tokyo, Japan), Jaehoon Yu (Samsung Advanced Inst. of Tech., Republic of Korea), Daiki Okonogi, Satoru Jimbo, Genta Inoue, Akira Hyodo (Institute of Science Tokyo, Japan), Ángel López García-Arias (NTT, Japan), Kota Ando, Bruno Hideki Fukushima-Kimura (Hokkaido Univ., Japan), Ryota Yasudo (Kyoto Univ., Japan), Thiem Van Chu, Masato Motomura (Institute of Science Tokyo, Japan)
Detailed information (abstract, etc)

8F-2 (Time: 13:40 - 14:05)

Title	(Designers' Forum) Nanophotonic Devices toward Opto-Electronic Accelerator
Author	*Akihiko Shinya (NTT, Japan)
Detailed information (abstract, etc)

8F-3 (Time: 14:05 - 14:30)

Title	(Designers' Forum) Highly Energy-Efficient Processing by Controlling Flexibility of Information Carrier using Superconductor Half-Flux Quantum Logic
Author	*Masamitsu Tanaka (Nagoya Univ., Japan)
Detailed information (abstract, etc)

[To Session Table]

Session 9A (T12-3) Homomorphic Encryption and Cloud Security
Time: 15:20 - 17:30, Thursday, January 23, 2025
Location: Room Saturn
Chairs: Junghee Lee (Korea Univ., Republic of Korea), Zhiyao Xie (Hong Kong Univ. of Science and Tech., Hong Kong)

9A-1 (Time: 15:20 - 15:45)

Title	Efficient and Secure Cloud-based Split Logic Synthesis
Author	Chaitali Sathe, Yiorgos Makris, *Benjamin Carrion Schafer (Univ. of Texas, Dallas, USA)
Detailed information (abstract, keywords, etc)

9A-2 (Time: 15:45 - 16:10)

Title	Efficient Key Switching Accelerator for Fully Homomorphic Encryption
Author	Seoyoon Jang, Sungjin Park, *Dongsuk Jeon (Seoul National Univ., Republic of Korea)
Detailed information (abstract, keywords, etc)

9A-3 (Time: 16:10 - 16:35)

Title	The Unlikely Hero: Nonidealities in Analog Photonic Neural Networks as Built-in Adversarial Defenders
Author	Haotian Lu, Ziang Yin, Partho Bhoumik, Sanmitra Banerjee, Krishnendu Chakrabarty, *Jiaqi Gu (Arizona State Univ., USA)
Detailed information (abstract, keywords, etc)

9A-4 (Time: 16:35 - 17:00)

Title	Low Multiplicative Depth Polynomial Evaluation Architectures for Homomorphic Encrypted Data
Author	*Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng (Xi’an Jiaotong Univ., China), Yang Su (Engineering Univ. of People’s Armed Police, China), Chen Yang (Xi’an Jiaotong Univ., China)
Detailed information (abstract, keywords, etc)

9A-5 (Time: 17:00 - 17:25)

Title	PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detection
Author	Chen-Chia Chang (Duke Univ., USA), Wan-Hsuan Lin (UCLA, USA), Jingyu Pan, Guanglei Zhou (Duke Univ., USA), Zhiyao Xie (HKUST, Hong Kong), Jiang Hu (TAMU, USA), *Yiran Chen (Duke Univ., USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 9B (T11-2) Advanced Modeling, Simulation, and Verification
Time: 15:20 - 17:30, Thursday, January 23, 2025
Location: Room Uranus
Chair: Yutaka Masuda (Nagoya Univ., Japan)

9B-1 (Time: 15:20 - 15:45)

Title	Efficient Hypergraph Modeling of VLSI Circuits for the MFS-Based Emulation and Simulation Acceleration
Author	*Jiahao Xu, Chunyan Pei, Shengbo Tong, Wenjian Yu (Tsinghua Univ., China)
Detailed information (abstract, keywords, etc)

9B-2 (Time: 15:45 - 16:10)

Title	ETPG: Efficient Transition Fault Simulation via Dual-Strategy Pattern Parallelism and Gate Restructuring
Author	*Mingjun Wang (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences/CASTEST, China), Hui Wang (CASTEST, China), Zizhen Liu (Chinese Academy of Sciences/CASTEST, China), Feng Gu (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences/CASTEST, China), Jianan Mu (Chinese Academy of Sciences/CASTEST, China), Jiaping Tang (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences/CASTEST, China), Jun Gao (CASTEST, China), Huawei Li, Jing Ye, Xiaowei Li (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences/CASTEST, China)
Detailed information (abstract, keywords, etc)

9B-3 (Time: 16:10 - 16:35)

Title	DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits
Author	*Arash Ardakani, Minwoo Kang, Kevin He (Univ. of California, Berkeley, United States Minor Outlying Islands), Qijing Huang (NVIDIA Research, United States Minor Outlying Islands), Vighnesh Iyer, Suhong Moon, John Wawrzynek (Univ. of California, Berkeley, United States Minor Outlying Islands)
Detailed information (abstract, keywords, etc)

9B-4 (Time: 16:35 - 17:00)

Title	Corvus: Efficient HW/SW Co-Verification Framework for RISC-V Instruction Extensions with FPGA Acceleration
Author	*Zijian Jiang (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China), Keran Zheng (Imperial College London, UK), David Boland (Univ. of Sydney, Australia), Yungang Bao, Kan Shi (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China)
Detailed information (abstract, keywords, etc)

9B-5 (Time: 17:00 - 17:25)

Title	SISCO: Selective Invariant Sharing, Clustering and Ordering for Effective Multi-Property Formal Verification
Author	*Sourav Das, Aritra Hazra (Indian Inst. of Tech. Kharagpur, India), Pallab Dasgupta, Himanshu Jain, Sudipta Kundu (Synopsys, USA)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 9C (T13-2) Carbon, Light, Fluids: Emerging Technologies
Time: 15:20 - 17:30, Thursday, January 23, 2025
Location: Room Venus
Chairs: Krishnendu Chakrabarty (Arizona State Univ., USA), Yangdi Lyu (HKUST (GZ), China)

9C-1 (Time: 15:20 - 15:45)

Title	CACTI-CNFET: an Analytical Tool for Timing, Power, and Area of SRAMs with Carbon Nanotube Field Effect Transistors
Author	*Shinobu Miwa, Eiichiro Sekikawa, Tongxin Yang (Univ. of Electro-Communications, Japan), Ryota Shioya (Univ. of Tokyo, Japan), Hayato Yamaki, Hiroki Honda (Univ. of Electro-Communications, Japan)
Detailed information (abstract, keywords, etc)

9C-2 (Time: 15:45 - 16:10)

Title	3M-DeSyn: Design Synthesis for Multi-Layer 3D-Printed Microfluidics with Timing and Volumetric Control
Author	*Yushen Zhang, Dragan Rašeta, Tsun-Ming Tseng, Ulf Schlichtmann (Tech. Univ. of Munich, Germany)
Detailed information (abstract, keywords, etc)

9C-3 (Time: 16:10 - 16:35)

Title	Dynamic Topology-Aware Flow Path Construction and Scheduling Optimization for Multilayered Continuous-Flow Microfluidic Biochips
Author	*Meng Lian, Shucheng Yang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann (Tech. Univ. of Munich, Germany)
Detailed information (abstract, keywords, etc)

9C-4 (Time: 16:35 - 17:00)

Title	A Backup Resource Customization and Allocation Method for Wavelength-Routed Optical Networks-on-Chip Topologies
Author	*Zhidan Zheng, You-Jen Chang, Liaoyuan Cheng, Tsun-Ming Tseng, Ulf Schlichtmann (Tech. Univ. of Munich, Germany)
Detailed information (abstract, keywords, etc)

9C-5 (Time: 17:00 - 17:25)

Title	GSNorm: An Efficient 3D Gaussian Rendering Accelerator with Splat Normalization and LUT-assist Rasterization
Author	*Yiyang Sun, Peiran Yan, Yiqi Jing, Le Ye, Tianyu Jia (Peking Univ., China)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 9D (T10-2) Advanced Techniques for Power Optimization and IR Prediction
Time: 15:20 - 17:30, Thursday, January 23, 2025
Location: Room Mars/Mercury
Chairs: Bei Yu (Chinese Univ. of Hong Kong, Hong Kong), Yu-Guang Chen (National Central Univ., Taiwan), Hongce Zhang (Hong Kong Univ. of Science and Tech. (GZ), China)

9D-1 (Time: 15:20 - 15:45)

Title	Via Fabrication with Multi-Row Guiding Templates Using Lamellar DSA
Author	*Yun-Na Tsai, Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan)
Detailed information (abstract, keywords, etc)

9D-2 (Time: 15:45 - 16:10)

Title	SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimization
Author	*Yikang Ouyang, Yuchao Wu, Dongsheng Zuo (Hong Kong Univ. of Science and Tech. (GZ), China), Subhendu Roy (Cadence Design Systems, USA), Tinghuan Chen (The Chinese Univ. of Hong Kong, Shenzhen, China), Zhiyao Xie (Hong Kong Univ. of Science and Tech., Hong Kong), Yuzhe Ma (Hong Kong Univ. of Science and Tech. (GZ), China)
Detailed information (abstract, keywords, etc)

9D-3 (Time: 16:10 - 16:35)

Title	Robust Technology-Transferable Static IR Drop Prediction Based on Image-to-Image Machine Learning
Author	*Chao-Chi Lan, Chuan-Chi Su, Yuan-Hsiang Lu, Yao-Wen Chang (National Taiwan Univ., Taiwan)
Detailed information (abstract, keywords, etc)

9D-4 (Time: 16:35 - 17:00)

Title	T-Fusion: Thermal Prediction of 3D ICs with Multi-fidelity Fusion
Author	Bingrui Zhang (Beihang Univ., China), *Wei Xing (Univ. of Sheffield, UK), Xin Zhao, Yuquan Sun (Beihang Univ., China)
Detailed information (abstract, keywords, etc)

9D-5 (Time: 17:00 - 17:25)

Title	Towards Functional Safety of Neural Network Hardware Accelerators: Concurrent Out-of-Distribution Detection in Hardware Using Power Side-Channel Analysis
Author	*Vincent Meyers (Karlsruhe Inst. of Tech., Germany), Michael Hefenbrock (RevoAI GmbH, Germany), Mahboobe Sadeghipourrudsari, Dennis Gnad, Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 9E (SS-8) Innovations and Challenges on Cryo-CMOS Devices, Circuits and Design Platforms
Time: 15:20 - 17:30, Thursday, January 23, 2025
Location: Innovation Hall
Chairs: Chika Tanaka (KIOXIA/Kyoto Inst. of Tech., Japan), Nobuyuki Momo (KIOXIA, Japan)

9E-1 (Time: 15:20 - 15:45)

Title	(Invited Paper) Physics-based Modeling to Extend a MOSFET Compact Model for Cryogenic Operation
Author	*Dondee Navarro (KIOXIA/Kyoto Inst. of Tech., Japan), Shin Taniguchi (Kyoto Inst. of Tech., Japan), Chika Tanaka (KIOXIA/Kyoto Inst. of Tech., Japan), Kazutoshi Kobayashi (Kyoto Inst. of Tech., Japan), Takashi Sato (Kyoto Univ., Japan), Michihiro Shintani (Kyoto Inst. of Tech., Japan)
Detailed information (abstract, keywords, etc)

9E-2 (Time: 15:45 - 16:10)

Title	(Invited Paper) Cryo-Compact Modeling Based on Sparse Gaussian Process
Author	*Tetsuro Iwasaki (Kyoto Inst. of Tech., Japan), Takashi Sato (Kyoto Univ., Japan), Michihiro Shintani (Kyoto Inst. of Tech., Japan)
Detailed information (abstract, keywords, etc)

9E-3 (Time: 16:10 - 16:35)

Title	(Invited Paper) Re-Consideration of Correlation Between Interface States and Bulk Traps Using Cryogenic Measurement
Author	*Yuichiro Mitani, Tatsuya Suzuki, Yohei Miyaki (Tokyo City Univ., Japan)
Detailed information (abstract, keywords, etc)

9E-4 (Time: 16:35 - 17:00)

Title	(Invited Paper) Random Telegraph Noise Observed on 65-nm Bulk pMOS Transistors at 3.8K
Author	*Takuma Kawakami, Takashi Sato, Hiromitsu Awano (Kyoto Univ., Japan)
Detailed information (abstract, keywords, etc)

9E-5 (Time: 17:00 - 17:25)

Title	(Invited Paper) Cryo-CMOS Analog Circuits for Spin Qubit Control
Author	*Takuji Miki (Kobe Univ., Japan)
Detailed information (abstract, keywords, etc)

[To Session Table]

Session 9F (DF-4) Integrated Circuit Design Methodologies using Open Source and Artificial Intelligence
Time: 15:20 - 16:35, Thursday, January 23, 2025
Organizer: Hiroyuki Uzawa (NTT, Japan), Chair: Takeshi Kuboki (Kumamoto Univ., Japan)

9F-1 (Time: 15:20 - 15:45)

Title	(Designers' Forum) A Challenge to Tape-Out in Open-Source Era
Author	*Akira Tsuchiya (Univ. of Shiga Prefecture, Japan)
Detailed information (abstract, etc)

9F-2 (Time: 15:45 - 16:10)

Title	(Designers' Forum) Analog Design Democratization for Small Volume LSI Fabrication
Author	*Seijiro Moriyama (Anagix, Japan), Shingo Ura, Tadaaki Tsuchiya (Logic Research, Japan)
Detailed information (abstract, etc)

9F-3 (Time: 16:10 - 16:35)

Title	(Designers' Forum) Automatic Design of an Analog Integrated Circuits using AI
Author	*Nobukazu Takai (Kyoto Inst. of Tech., Japan)
Detailed information (abstract, etc)

The 30th Asia and South Pacific Design Automation Conference Technical Program

Session Schedule

List of papers

The 30th Asia and South Pacific Design Automation Conference
Technical Program