Monday, January 22, 2024 |
Room 204 | Room 205 | Room 206 | Room 207 |
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9:30 - 12:30 |
9:30 - 12:30 |
9:30 - 12:30 |
9:30 - 12:30 |
12:30 - 14:00 |
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14:00 - 17:00 |
14:00 - 17:00 |
14:00 - 17:00 |
14:00 - 17:00 |
Tuesday, January 23, 2024 |
Wednesday, January 24, 2024 |
Thursday, January 25, 2024 |
Monday, January 22, 2024 |
Title | (Tutorial) Tutorial to NeuroSim: A Versatile Benchmark Framework for AI Hardware |
Author | Shimeng Yu (Georgia Tech, USA) |
Detailed information (abstract, keywords, etc) |
Title | (Tutorial) Toward Robust Neural Network Computation on Emerging Crossbar-based Hardware and Digital Systems |
Author | Yiyu Shi (Univ. of Notre Dame, USA), Masanori Hashimoto (Kyoto Univ., Japan) |
Detailed information (abstract, keywords, etc) |
Title | (Tutorial) Morpher: A Compiler and Simulator Framework for CGRA |
Author | Tulika Mitra, Zhaoying Li, Thilini Kaushalya Bandara (National Univ. of Singapore, Singapore) |
Detailed information (abstract, keywords, etc) |
Title | (Tutorial) Machine Learning for Computational Lithography |
Author | Yonghwi Kwon (Synopsys, USA), Haoyu Yang (NVIDIA Research, USA) |
Detailed information (abstract, keywords, etc) |
Title | (Tutorial) Low Power Design: Current Practice and Opportunities |
Author | Gang Qu (Univ. of Maryland, USA) |
Detailed information (abstract, keywords, etc) |
Title | (Tutorial) Leading the industry, Samsung CXL Technology |
Author | Jeonghyeon Cho, Jinin So, Kyungsan Kim (Samsung Electronics, Republic of Korea) |
Detailed information (abstract, keywords, etc) |
Title | (Tutorial) Sparse Acceleration for Artificial Intelligence: Progress and Trends |
Author | Guohao Dai (Shanghai Jiao Tong Univ., China), Xiaoming Chen (Chinese Academy of Sciences, China), Mingyu Gao, Zhenhua Zhu (Tsinghua Univ., China) |
Detailed information (abstract, keywords, etc) |
Title | (Tutorial) CircuitOps and OpenROAD: Unleashing ML EDA for Research and Education |
Author | Andrew B. Kahng (Univ. of California San Diego, USA), Vidya A. Chhabria (Arizona State Univ., USA) |
Detailed information (abstract, keywords, etc) |
Tuesday, January 23, 2024 |
Title | ASP-DAC 2024 Opening |
Detailed information |
Title | (Keynote Address) Advanced Technology and Design Enablement |
Author | Sei Seung Yoon (Samsung Electronics, Republic of Korea) |
Detailed information (abstract, etc) |
Title | CANSim: When to Utilize Synchronous and Asynchronous Routers in Large and Complex NoCs |
Author | *Tom Glint (IIT Gandhinagar, India), Manu Awasthi (Ashoka Univ., India), Joycee Mekie (IIT Gandhinagar, India) |
Page | pp. 1 - 6 |
Detailed information (abstract, keywords, etc) |
Title | PAIR: Periodically Alternate the Identity of Routers to Ensure Deadlock Freedom in NoC |
Author | *Zifeng Zhao, Xinghao Zhu, Jiyuan Bai, Gengsheng Chen (Fudan Univ., China) |
Page | pp. 7 - 12 |
Detailed information (abstract, keywords, etc) |
Title | SCNoCs: An Adaptive Heterogeneous Multi-NoC with Selective Compression and Power Gating |
Author | *Fan Jiang, Chengeng Li, Lin Chen, Jiaqi Liu, Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong), Jiang Xu (Hong Kong Univ. of Science and Tech. (GZ), China) |
Page | pp. 13 - 18 |
Detailed information (abstract, keywords, etc) |
Title | QuadraNet: Improving High-Order Neural Interaction Efficiency with Hardware-Aware Quadratic Neural Networks |
Author | *Chenhui Xu, Fuxun Yu, Zirui Xu (George Mason Univ., USA), Chenchen Liu (Univ. of Maryland, Baltimore County, USA), Jinjun Xiong (Univ. at Buffalo, USA), Xiang Chen (George Mason Univ., USA) |
Page | pp. 19 - 25 |
Detailed information (abstract, keywords, etc) |
Title | RobustDiCE: Robust and Distributed CNN Inference at the Edge |
Author | *Xiaotian Guo (Univ. of Amsterdam/Leiden Univ., Netherlands), Quan Jiang (Nanjing Agricultural Univ., China), Andy Pimentel (Univ. of Amsterdam, Netherlands), Todor Stefanov (Leiden Univ., Netherlands) |
Page | pp. 26 - 31 |
Detailed information (abstract, keywords, etc) |
Title | YoseUe: "trimming" Random Forest's training towards resource-constrained inference |
Author | *Alessandro Verosimile, Alessandro Tierno, Andrea Damiani, Marco Domenico Santambrogio (Politecnico di Milano, Italy) |
Page | pp. 32 - 37 |
Detailed information (abstract, keywords, etc) |
Title | P2LSG: Powers-of-2 Low-Discrepancy Sequence Generator for Stochastic Computing |
Author | Mehran Shoushtari Moghadam, Sercan Aygun, Mohsen Riahi Alam, *M Hassan Najafi (Univ. of Louisiana, Lafayette, USA) |
Page | pp. 38 - 45 |
Detailed information (abstract, keywords, etc) |
Title | PAAP-HD: PIM-Assisted Approximation for Efficient Hyper-Dimensional Computing |
Author | *Fangxin Liu, Haomin Li, Ning Yang (Shanghai Jiao Tong Univ., China), Yichi Chen (Tianjin Univ., China), Zongwu Wang (Shanghai Jiao Tong Univ., China), Tao Yang (Huawei Technologies, China), Li Jiang (Shanghai Jiao Tong Univ., China) |
Page | pp. 46 - 51 |
Detailed information (abstract, keywords, etc) |
Title | FPGA-Based HPC for Associative Memory System |
Author | *Deyu Wang (Fudan Univ., China), Yuning Wang (Univ. of Turku, Finland), Yu Yang, Dimitrios Stathis, Ahmed Hemani, Anders Lansner (Royal Inst. of Tech., Sweden), Jiawei Xu (Guangdong Institute of Intelligence Science and Technology, China), Li-Rong Zheng, Zhuo Zou (Fudan Univ., China) |
Page | pp. 52 - 57 |
Detailed information (abstract, keywords, etc) |
Title | Chipletizer: Repartitioning SoCs for Cost-Effective Chiplet Integration |
Author | *Fuping Li, Ying Wang, Yujie Wang, Mengdi Wang, Yinhe Han, Huawei Li, Xiaowei Li (Chinese Academy of Sciences, China) |
Page | pp. 58 - 64 |
Detailed information (abstract, keywords, etc) |
Title | CoPlace: Coherent Placement Engine with Layout-aware Partitioning for 3D ICs |
Author | *Bangqi Fu, Lixin Liu, Yang Sun, Wing-Ho Lau, Martin D.F. Wong, Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 65 - 70 |
Detailed information (abstract, keywords, etc) |
Title | O.O: Optimized One-die Placement for Face-to-face Bonded 3D ICs |
Author | *Xingyu Tong, Zhijie Cai, Peng Zou, Min Wei, Yuan Wen (Fudan Univ., China), Zhifeng Lin (Fuzhou Univ., China), Jianli Chen (Fudan Univ., China) |
Page | pp. 71 - 76 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) iEDA: An Open-source infrastructure of EDA |
Author | *Xingquan Li, Zengrong Huang, Simin Tao, Zhipeng Huang, Chunan Zhuang (Peng Cheng Laboratory, China), Hao Wang (Chinese Academy of Sciences, China), Yifan Li (Peng Cheng Laboratory, China), Yihang Qiu (Univ. of Chinese Academy of Sciences, China), Guojie Luo (Peking Univ., China), Huawei Li (Chinese Academy of Sciences, China), Haihua Shen (Univ. of Chinese Academy of Sciences, China), Mingyu Chen, Dongbo Bu (Chinese Academy of Sciences, China), Wenxing Zhu (Fuzhou Univ., China), Ye Cai (Shenzhen Univ., Chile), Xiaoming Xiong (Guangdong Univ. of Tech., China), Ying Jiang, Yi Heng (Sun Yat-sen Univ., China), Peng Zhang (Peng Cheng Laboratory, China), Bei Yu (Chinese Univ. of Hong Kong, China), Biwei Xie, Yungang Bao (Chinese Academy of Sciences, China) |
Page | pp. 77 - 82 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) iPD: An Open-source intelligent Physical Design Toolchain |
Author | Xingquan Li, Simin Tao, Shijian Chen, Zhisheng Zeng, Zhipeng Huang (Peng Cheng Laboratory, China), Hongxi Wu (Fuzhou Univ., China), Weiguo Li (Minnan Normal Univ., China), Zengrong Huang, Liwei Ni (Peng Cheng Laboratory, China), Xueyan Zhao (Chinese Academy of Sciences, China), He Liu (Peking Univ., China), Shuaiying Long (Peng Cheng Laboratory, China), Ruizhi Liu (Chinese Academy of Sciences, China), Xiaoze Lin, Bo Yang (Peng Cheng Laboratory, China), Fuxing Huang (Fuzhou Univ., China), Zonglin Yang (Shenzhen Univ., China), Yihang Qiu (Univ. of Chinese Academy of Sciences, China), Zheqing Shao (Univ. of Science and Tech. of China, China), Jikang Liu, Yuyao Liang (Shenzhen Univ., China), Biwei Xie, Yungang Bao (Chinese Academy of Sciences, China), *Bei Yu (Chinese Univ. of Hong Kong, China) |
Page | pp. 83 - 88 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) A Resource-efficient Task Scheduling System Using Reinforcement Learning |
Author | Chedi Morchdi (Univ. of Utah, USA), Cheng-Hsiang Chiu (Univ. of Wisconsin at Madison, USA), Yi Zhou (Univ. of Utah, USA), *Tsung-Wei Huang (Univ. of Wisconsin at Madison, USA) |
Page | pp. 89 - 95 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Machine learning and GPU accelerated sparse linear solvers for transistor-level circuit simulation: a perspective survey |
Author | *Zhou Jin, Wenhao Li, Yinuo Bai, Tengcheng Wang, Yicheng Lu, Weifeng Liu (China Univ. of Petroleum-Beijing, China) |
Page | pp. 96 - 101 |
Detailed information (abstract, keywords, etc) |
Title | (Designers' Forum) AI-Driven Solution for DFT Optimization |
Author | Soochang Park (EDA Group, Synopsys, USA) |
Detailed information (abstract, etc) |
Title | (Designers' Forum) Optimization of PDN and DTCO using Synopsys Machine Learning Framework |
Author | Kyoung-In Cho (EDA Group, Synopsys, USA) |
Detailed information (abstract, etc) |
Title | HomeSGN: A Smarter Home with Novel Rule Mining Enabled by a Scorer-Generator GAN |
Author | *Zehua Yuan, Junhao Pan, Xiaofan Zhang, Deming Chen (Univ. of Illinois at Urbana Champaign, USA) |
Page | pp. 102 - 108 |
Detailed information (abstract, keywords, etc) |
Title | Adaptive Workload Distribution for Accuracy-aware DNN Inference on Collaborative Edge Platforms |
Author | *Zain Taufique (Univ. of Turku, Finland), Antonio Miele (Politecnico di Milano, Italy), Pasi Liljeberg, Anil Kanduri (Univ. of Turku, Finland) |
Page | pp. 109 - 114 |
Detailed information (abstract, keywords, etc) |
Title | Extending Neural Processing Unit and Compiler for Advanced Binarized Neural Networks |
Author | Minjoon Song, Faaiz Asim, *Jongeun Lee (Ulsan National Inst. of Science and Tech. (UNIST), Republic of Korea) |
Page | pp. 115 - 120 |
Detailed information (abstract, keywords, etc) |
Title | JustQ: Automated Deployment of Fair and Accurate Quantum Neural Networks |
Author | Ruhan Wang, Fahiz Baba-Yara, *Fan Chen (Indiana Univ. Bloomington, USA) |
Page | pp. 121 - 126 |
Detailed information (abstract, keywords, etc) |
Title | Using Boolean Satisfiability for Exact Shuttling in Trapped-Ion Quantum Computers |
Author | *Daniel Schönberger (Tech. Univ. of Munich, Germany), Stefan Hillmich (Software Competence Center Hagenberg (SCCH) GmbH, Austria), Matthias Brandl (Infineon Technologies AG, Germany), Robert Wille (Tech. Univ. of Munich, Germany) |
Page | pp. 127 - 133 |
Detailed information (abstract, keywords, etc) |
Title | Optimizing Decision Diagrams for Measurements of Quantum Circuits |
Author | *Ryosuke Matsuo (Osaka Univ., Japan), Rudy Raymond (IBM, Japan), Shigeru Yamashita (Ritsumeikan Univ., Japan), Shin-ichi Minato (Kyoto Univ., Japan) |
Page | pp. 134 - 139 |
Detailed information (abstract, keywords, etc) |
Title | CTQr: Control and Timing-Aware Qubit Routing |
Author | *Ching-Yao Huang, Wai-Kei Mak (National Tsing Hua Univ., Taiwan) |
Page | pp. 140 - 145 |
Detailed information (abstract, keywords, etc) |
Title | BNN-Flip: Enhancing the Fault Tolerance and Security of Compute-in-Memory Enabled Binary Neural Network Accelerators |
Author | *Akul Malhotra, Chunguang Wang, Sumeet Kumar Gupta (Purdue Univ., USA) |
Page | pp. 146 - 152 |
Detailed information (abstract, keywords, etc) |
Title | ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns |
Author | *Yiming Chen, Guodong Yin, Hongtao Zhong, Mingyen Lee, Huazhong Yang (Tsinghua Univ., China), Sumitha George (North Dakota State Univ., USA), Vijaykrishnan Narayanan (Pennsylvania State Univ., USA), Xueqing Li (Tsinghua Univ., China) |
Page | pp. 153 - 158 |
Detailed information (abstract, keywords, etc) |
Title | A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators |
Author | *Yuan-Chun Luo, James Read, Anni Lu, Shimeng Yu (Georgia Tech, USA) |
Page | pp. 159 - 164 |
Detailed information (abstract, keywords, etc) |
Title | Design of Aging-Robust Clonable PUF Using an Insulator-Based ReRAM for Organic Circuits |
Author | *Kunihiro Oshima (Kyoto Univ., Japan), Kazunori Kuribara (AIST, Japan), Takashi Sato (Kyoto Univ., Japan) |
Page | pp. 165 - 170 |
Detailed information (abstract, keywords, etc) |
Title | Heterogeneous Graph Attention Network Based Statistical Timing Library Characterization with Parasitic RC Reduction |
Author | *Xu Cheng, Yuyang Ye, Guoqing He, Qianqian Song, Peng Cao (Southeast Univ., China) |
Page | pp. 171 - 176 |
Detailed information (abstract, keywords, etc) |
Title | An Optimization-aware Pre-Routing Timing Prediction Framework Based on Heterogeneous Graph Learning |
Author | *Guoqing He, Wenjie Ding, Yuyang Ye, Xu Cheng, Qianqian Song, Peng Cao (Southeast Univ., China) |
Page | pp. 177 - 182 |
Detailed information (abstract, keywords, etc) |
Title | BoCNT: A Bayesian Optimization Framework for Global CNT Interconnect Optimization |
Author | *Hang Wu, Ning Xu (Wuhan Univ. of Tech., China), Wei Xing, Yuanqing Cheng (Beihang Univ., China) |
Page | pp. 183 - 188 |
Detailed information (abstract, keywords, etc) |
Title | Timing Analysis beyond Complementary CMOS Logic Styles |
Author | *Jan Lappas, Mohamed Amine Riahi, Christian Weis, Norbert Wehn (Univ. of Kaiserslautern-Landau, Germany), Sani Nassif (Radyalis LLC, USA) |
Page | pp. 189 - 194 |
Detailed information (abstract, keywords, etc) |
Title | An In-Memory Computing SRAM Macro for Memory-Augmented Neural Network in 40nm CMOS |
Author | *Sunghoon Kim, Wonjae Lee, Sundo Kim, Sungjin Park, Dongsuk Jeon (Seoul National Univ., Republic of Korea) |
Detailed information (abstract, keywords, etc) |
Title | A Mobile 3D-CNN Processor with Hierarchical Sparsity-Aware Computation and Temporal Redundancy-aware Network |
Author | *Seungbin Kim, Kyuho Lee (Ulsan National Inst. of Science and Tech., Republic of Korea) |
Detailed information (abstract, keywords, etc) |
Title | A 740μW Real-Time Speech Enhancement Processor Using Band Optimization and Multiplier-Less PE Arrays for Hearing Assistive Devices |
Author | *Sungjin Park, Sunwoo Lee (Seoul National Univ., Republic of Korea), Jeongwoo Park (Sungkyunkwan Univ., Republic of Korea), Hyeong-Seok Choi (Supertone, Republic of Korea), Dongsuk Jeon (Seoul National Univ., Republic of Korea) |
Detailed information (abstract, keywords, etc) |
Title | StrongARM Latch-based Clocked Comparator Design for Improving Low Speed DRAM Testing Reliability |
Author | *Jongchan Lee, Chanheum Han, Ki-Soo Lee, Joo-Hyung Chae (Kwangwoon Univ., Republic of Korea) |
Detailed information (abstract, keywords, etc) |
Title | Nano-Watt High-Resolution Continuous-Time Delta-Sigma Modulator With On-Chip PMIC for Sensor Applications |
Author | *Jaedo Kim, Jiho Moon, Tian Guo, Chaeyoung Kang, Jeongjin Roh (Hanyang Univ., Republic of Korea) |
Detailed information (abstract, keywords, etc) |
Title | A 0.15-to-1.15V Output Range 270mA Self-Calibrating-Clocked Capacitor-Free LDO Using Rail-to-Rail Voltage-Difference-to-Time Converter with 0.183fs FoM |
Author | *Youngmin Park, Dongsuk Jeon (Seoul National Univ., Republic of Korea) |
Detailed information (abstract, keywords, etc) |
Title | A 0.37 V 126 nW 0.29 mm2 65-nm CMOS Biofuel-Cell-Modulated Biosensing System Featuring an FSK-PIM-Combined 2.4 GHz Transmitter for Continuous Glucose Monitoring Contact Lenses |
Author | Guowei Chen, Akiyoshi Tanaka (Nagoya Univ., Japan), *Kiichi Niitsu (Kyoto Univ., Japan) |
Detailed information (abstract, keywords, etc) |
Title | Power-Efficient FPGA Implementation of CNN-Based Object Detector |
Author | *Haein Lee, Inseong Hwang, Hyun Kim (Seoul National Univ. of Science and Tech., Republic of Korea) |
Detailed information (abstract, keywords, etc) |
Title | TransCoder: Efficient Hardware Implementation of Transformer Encoder |
Author | *Sangki Park, Chan-Hoon Kim, Soo-Min Rho, Jeong-Hyun Kim, Seo-Ho Chung, Ki-Seok Chung (Hanyang Univ., Republic of Korea) |
Detailed information (abstract, keywords, etc) |
Title | Implementation of a High-throughput and Accurate Gaussian-TinyYOLOv3 Hardware Accelerator |
Author | *Juntae Park, Subin Ki, Hyun Kim (Seoul National Univ. of Science and Tech., Republic of Korea) |
Detailed information (abstract, keywords, etc) |
Title | A 17.01 MOP/s/LUT Binary Neural Network Inference Processor Showing 87.81% CIFAR10 Accuracy with 2.6M-bit On-Chip Parameters in a 28nm FPGA |
Author | *Gil-Ho Kwak, Tae-Hwan Kim (Korea Aerospace Univ., Republic of Korea) |
Detailed information (abstract, keywords, etc) |
Title | (Designers' Forum) Building the programmable, high performance and energy-efficient AI chip for ChatGPT |
Author | Joon Ho Baek (FuriosaAI, Republic of Korea) |
Detailed information (abstract, keywords, etc) |
Title | (Designers' Forum) Enabling AI Innovation through Zero-touch SAPEON AI Inference System |
Author | Soojung Ryu (SAPEON, Republic of Korea) |
Detailed information (abstract, etc) |
Title | (Designers' Forum) Processing-in-Memory in Generative AI Era |
Author | Kyomin Sohn (Samsung Electronics, Republic of Korea) |
Detailed information (abstract, etc) |
Title | (Designers' Forum) AiMX: Cost-effective LLM accelerator using AiM (SK hynix’s PIM) |
Author | Euicheol Lim (SK Hynix, Republic of Korea) |
Detailed information (abstract, etc) |
Title | Collaborative Coalescing of Redundant Memory Access for GPU System |
Author | Fan Jiang, *Chengeng Li, Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong), Jiang Xu (Hong Kong Univ. of Science and Tech. (GZ), China) |
Page | pp. 195 - 200 |
Detailed information (abstract, keywords, etc) |
Title | WER: Maximizing Parallelism of Irregular Graph Applications Through GPU Warp EqualizeR |
Author | *En-Ming Huang, Bo-Wun Cheng (National Tsing Hua Univ., Taiwan), Meng-Hsien Lin (National Yang Ming Chiao Tung Univ., Taiwan), Chun-Yi Lee (National Tsing Hua Univ., Taiwan), Tsung Tai Yeh (National Yang Ming Chiao Tung Univ., Taiwan) |
Page | pp. 201 - 206 |
Detailed information (abstract, keywords, etc) |
Title | SoC-Tuner: An Importance-guided Exploration Framework for DNN-targeting SoC Design |
Author | *Shixin Chen, Su Zheng, Chen Bai, Wenqian Zhao, Shuo Yin, Yang Bai, Bei Yu (Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 207 - 212 |
Detailed information (abstract, keywords, etc) |
Title | ARS-Flow: A Design Space Exploration Flow for Accelerator-rich System based on Active Learning |
Author | *Shuaibo Huang, Yuyang Ye, Hao Yan, Longxing Shi (Southeast Univ., China) |
Page | pp. 213 - 218 |
Detailed information (abstract, keywords, etc) |
Title | Secco: Codesign for Resource Sharing in Regular-Expression Accelerators |
Author | *Jackson Woodruff, Sam Ainsworth, Micahel F.P. O'Boyle (Univ. of Edinburgh, UK) |
Page | pp. 219 - 224 |
Detailed information (abstract, keywords, etc) |
Title | SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration |
Author | *Chen Yin, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing (Shanghai Jiao Tong Univ., China) |
Page | pp. 225 - 230 |
Detailed information (abstract, keywords, etc) |
Title | APoX: Accelerate Graph-Based Deep Point Cloud Analysis via Adaptive Graph Construction |
Author | *Lei Dai (Chinese Academy of Sciences, China), Shengwen Liang, Ying Wang (SKLCA, Institute of Computing Technology, Univ. of Chinese Academy of Sciences; Zhongguancun National Laboratory, China), Huawei Li (SKLCA, Institute of Computing Technology, Univ. of Chinese Academy of Sciences; Peng Cheng Laboratory, China), Xiaowei Li (SKLCA, Institute of Computing Technology, Univ. of Chinese Academy of Sciences; Zhongguancun National Laboratory, China) |
Page | pp. 231 - 237 |
Detailed information (abstract, keywords, etc) |
Title | FuseFPS: Accelerating Farthest Point Sampling with Fusing KD-tree Construction for Point Clouds |
Author | *Meng Han, Liang Wang, Limin Xiao, Hao Zhang, Chenhao Zhang, Xilong Xie, Shuai Zheng (Beihang Univ., China), Jin Dong (Beijing Academy of Blockchain and Edge Computing, China) |
Page | pp. 238 - 243 |
Detailed information (abstract, keywords, etc) |
Title | A Fixed-Point Pre-Processing Hardware Architecture Design for Complex Independent Component Analysis |
Author | *Yashwant Moses, Madhav Rao (International Institute of Information Technology Bangalore, India) |
Page | pp. 244 - 249 |
Detailed information (abstract, keywords, etc) |
Title | Pearls Hide Behind Linearity: Simplifying Deep Convolutional Networks for Embedded Hardware Systems via Linearity Grafting |
Author | *Xiangzhong Luo (Nanyang Technological Univ., Singapore), Di Liu (Norwegian Univ. of Science and Tech., Norway), Hao Kong, Shuo Huai, Hui Chen, Shiqing Li, Guochu Xiong, Weichen Liu (Nanyang Technological Univ., Singapore) |
Page | pp. 250 - 255 |
Detailed information (abstract, keywords, etc) |
Title | On Decomposing Complex Test Cases for Efficient Post-silicon Validation |
Author | Harshitha C, Sundarapalli Harikrishna, Peddakotla Rohith, *Sandeep Chandran (Indian Inst. of Tech. Palakkad, India), Rajshekar Kalayappan (Indian Inst. of Tech. Dharwad, India) |
Page | pp. 256 - 261 |
Detailed information (abstract, keywords, etc) |
Title | DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction |
Author | *Guangyu Hu, Jianheng Tang (Hong Kong Univ. of Science and Tech., Hong Kong), Changyuan Yu (Hong Kong Univ. of Science and Tech. (GZ), China), Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong), Hongce Zhang (Hong Kong Univ. of Science and Tech. (GZ), China) |
Page | pp. 262 - 268 |
Detailed information (abstract, keywords, etc) |
Title | TIUP: Effective Processor Verification with Tautology-Induced Universal Properties |
Author | *Yufeng Li, Yiwei Ci, Qiusong Yang (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China) |
Page | pp. 269 - 274 |
Detailed information (abstract, keywords, etc) |
Title | Verifying Embedded Graphics Libraries leveraging Virtual Prototypes and Metamorphic Testing |
Author | *Christoph Hazott, Florian Stögmüller, Daniel Große (Johannes Kepler Univ. Linz, Austria) |
Page | pp. 275 - 281 |
Detailed information (abstract, keywords, etc) |
Title | MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory |
Author | Simranjeet Singh (Indian Inst. of Tech. Bombay, India), Chandan Kumar Jha (Univ. of Bremen, Germany), Ankit Bende, Vikas Rana (Forschungszentrum Jülich GmbH, Germany), Sachin Parkar (Indian Inst. of Tech. Bombay, India), Rolf Drechsler (Univ. of Bremen, Germany), *Farhad Merchant (Newcastle Univ., Newcastle upon Tyne, UK) |
Page | pp. 282 - 287 |
Detailed information (abstract, keywords, etc) |
Title | An Effective Netlist Planning Approach for Double-sided Signal Routing |
Author | *Tzu-Chuan Lin, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang (National Tsing Hua Univ., Taiwan) |
Page | pp. 288 - 293 |
Detailed information (abstract, keywords, etc) |
Title | An Analytical Placement Algorithm with Routing topology Optimization |
Author | *Min Wei, Xingyu Tong, Zhijie Cai, Peng Zou (Fudan Univ., China), Zhifeng Lin (Fuzhou Univ., China), Jianli Chen (Fudan Univ., China) |
Page | pp. 294 - 299 |
Detailed information (abstract, keywords, etc) |
Title | Effective Analytical Placement for Advanced Hybrid-Row-Height Circuit Designs |
Author | *Yuan Wen, Benchao Zhu (Fudan Univ., China), Zhifeng Lin (Fuzhou Univ., China), Jianli Chen (Fudan Univ., China) |
Page | pp. 300 - 305 |
Detailed information (abstract, keywords, etc) |
Title | Row Planning and Placement for Hybrid-Row-Height Designs |
Author | *Ching-Yao Huang, Wai-Kei Mak (National Tsing Hua Univ., Taiwan) |
Page | pp. 306 - 311 |
Detailed information (abstract, keywords, etc) |
Title | TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based Design |
Author | *Chen-Hao Hsu (Univ. of Texas, Austin, USA), Xiaoqing Xu, Hao Chen, Dino Ruic (X, USA), David Z. Pan (Univ. of Texas, Austin, USA) |
Page | pp. 312 - 318 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Towards Finding the Sources of Polymorphism in Polymorphic Gates |
Author | Timothy Dunlap, Zelin Lu, *Gang Qu (Univ. of Maryland, USA) |
Page | pp. 319 - 324 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) HOGE: Homomorphic Gate on An FPGA |
Author | *Kotaro Matsuoka (Kyoto Univ., Japan), Song Bian (Beihang Univ., China), Takashi Sato (Kyoto Univ., Japan) |
Page | pp. 325 - 332 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Sensors for Remote Power Attacks: New Developments and Challenges |
Author | *Brian Udugama (Univ. of New South Wales, Australia), Darshana Jayasinghe, Sri Parameswaran (Univ. of Sydney, Australia) |
Page | pp. 333 - 340 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) PRESS: Persistence Relaxation for Efficient and Secure Data Sanitization on Zoned Namespace Storage |
Author | Yun-Shan Hsieh (Academia Sinica, Taiwan), Bo-Jun Chen (National Tsing Hua Univ., Taiwan), *Po-Chun Huang (National Taipei Univ. of Tech., Taiwan), Yuan-Hao Chang (Academia Sinica, Taiwan) |
Page | pp. 341 - 348 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge |
Author | Weimin Fu (Kansas State Univ., USA), Shijie Li, Yifang Zhao (Univ. of Science and Tech. of China, China), Haocheng Ma (Tianjin Univ., China), Raj Dutta (Silicon Assurance, USA), Xuan Zhang (Washington Univ. in St. Louis, USA), Kaichen Yang (Michigan Technological Univ., USA), *Yier Jin (Univ. of Science and Tech. of China, China), Xiaolong Guo (Kansas State Univ., USA) |
Page | pp. 349 - 354 |
Detailed information (abstract, keywords, etc) |
Title | (Designers' Forum) Co-Design Considerations of Heterogeneous Integrated Packaging |
Author | Gu-Sung Kim (Kangnam Univ., Republic of Korea) |
Detailed information (abstract, etc) |
Title | (Designers' Forum) Don’t Close Your Eyes on Temperature: System Level Thermal Perspectives of 3D Stacked Chips |
Author | Sung Woo Chung (Korea Univ., Republic of Korea) |
Detailed information (abstract, etc) |
Title | (Designers' Forum) Introducing UCIe: The Global Chiplet Interconnect Standard |
Author | Youngbin Kwon (Samsung Electronics, Republic of Korea) |
Detailed information (abstract, etc) |
Title | (Designers' Forum) Addressing Modeling and Simulation Challenges in Chiplet Interfaces |
Author | Jaeha Kim (Seoul National Univ., Republic of Korea) |
Detailed information (abstract, etc) |
Wednesday, January 24, 2024 |
Title | FormalFuzzer: Formal Verification Assisted Fuzz Testing for SoC Vulnerability Detection |
Author | Nusrat Farzana Dipu, Muhammad Monir Hossain, Kimia Zamiri Azar, Farimah Farahmandi, *Mark Tehranipoor (Univ. of Florida, USA) |
Page | pp. 355 - 361 |
Detailed information (abstract, keywords, etc) |
Title | DeepIncept: Diversify Performance Counters with Deep Learning to Detect Malware |
Author | Zhuoran Li (Old Dominion Univ., USA), *Dan Zhao (Univ. of Arizona, USA) |
Page | pp. 362 - 367 |
Detailed information (abstract, keywords, etc) |
Title | Resource- and Workload-aware Malware Detection through Distributed Computing in IoT Networks |
Author | *Sreenitha Kasarapu, Sanket Shukla, Sai Manoj PD (George Mason Univ., USA) |
Page | pp. 368 - 373 |
Detailed information (abstract, keywords, etc) |
Title | APPLE: An Explainer of ML Predictions on Circuit Layout at the Circuit-Element Level |
Author | *Tao Zhang (Hong Kong Univ. of Science and Tech., Hong Kong), Haoyu Yang (Nvidia, USA), Kang Liu (Huazhong Univ. of Science and Tech., China), Zhiyao Xie (Hong Kong Univ. of Science and Tech., Hong Kong) |
Page | pp. 374 - 379 |
Detailed information (abstract, keywords, etc) |
Title | E2E-Check: End to End GPU-Accelerated Design Rule Checking with Novel Mask Boolean Algorithms |
Author | *Yifei Zhou, Zijian Wang, Chao Wang (Southeast Univ., China) |
Page | pp. 380 - 385 |
Detailed information (abstract, keywords, etc) |
Title | CIS: Conditional Importance Sampling for Yield Optimization of Analog and SRAM Circuits |
Author | *Yanfang Liu (Beihang Univ., China), Wei Xing (Univ. of Sheffield, UK) |
Page | pp. 386 - 391 |
Detailed information (abstract, keywords, etc) |
Title | FineMap: A Fine-grained GPU-parallel LUT Mapping Engine |
Author | *Tianji Liu (Chinese Univ. of Hong Kong, Hong Kong), Lei Chen, Xing Li, Mingxuan Yuan (Huawei Noah's Ark Lab, Hong Kong SAR, Hong Kong), Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 392 - 397 |
Detailed information (abstract, keywords, etc) |
Title | Transduction Method for AIG Minimization |
Author | *Yukio Miyasaka (UC Berkeley, USA) |
Page | pp. 398 - 403 |
Detailed information (abstract, keywords, etc) |
Title | In Medio Stat Virtus: Combining Boolean and Pattern Matching |
Author | Gianluca Radi, *Alessandro Tempia Calvino, Giovanni De Micheli (EPFL, Switzerland) |
Page | pp. 404 - 410 |
Detailed information (abstract, keywords, etc) |
Title | A Transferable GNN-based Multi-Corner Performance Variability Modeling for Analog ICs |
Author | *Hongjian Zhou (ShanghaiTech Univ., China), Yaguang Li (Texas A&M Univ., USA), Xin Xiong, Pingqiang Zhou (ShanghaiTech Univ., China) |
Page | pp. 411 - 416 |
Detailed information (abstract, keywords, etc) |
Title | An Efficient Transfer Learning Assisted Global Optimization Scheme for Analog/RF Circuits |
Author | *Zhikai Wang (Tsinghua Univ., China), Jingbo Zhou (Baidu Research, China), Xiaosen Liu, Yan Wang (Tsinghua Univ., China) |
Page | pp. 417 - 422 |
Detailed information (abstract, keywords, etc) |
Title | MACRO: Multi-agent Reinforcement Learning-based Cross-layer Optimization of Operational Amplifier |
Author | *Zihao Chen, Songlei Meng, Fan Yang, Li Shang, Xuan Zeng (Fudan Univ., China) |
Page | pp. 423 - 428 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Applications of LLM for Chip Design |
Author | Haoxing (Mark) Ren (NVIDIA, USA) |
Detailed information |
Title | (Invited Paper) TinyChat for On-device LLM |
Author | Song Han (MIT, USA) |
Detailed information |
Title | (Invited Paper) FL-NAS: Towards Fairness of NAS for Resource Constrained Devices via Large Language Models |
Author | Ruiyang Qin (Univ. of Notre Dame, USA), Yuting Hu (Univ. at Buffalo, USA), Zheyu Yan (Univ. of Notre Dame, USA), *Jinjun Xiong (Univ. at Buffalo, USA), Ahmed Abbasi, Yiyu Shi (Univ. of Notre Dame, USA) |
Page | pp. 429 - 434 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Software/Hardware Co-design for LLM and Its Application for Design Verification |
Author | Lily Jiaxin Wan, Yingbing Huang, Yuhong Li, Hanchen Ye, Jinghua Wang (UIUC, USA), Xiaofan Zhang (Google, USA), *Deming Chen (UIUC, USA) |
Page | pp. 435 - 441 |
Detailed information (abstract, keywords, etc) |
Title | (Keynote Address) Present and Future Challenges of High-Bandwidth Memory |
Author | Myeong-Jae Park (SK Hynix, Republic of Korea) |
Detailed information (abstract, etc) |
Title | wearMeter: an Accurate Wear Metric for NAND Flash Memory |
Author | *Min Ye (City Univ. of Hong Kong, Hong Kong), Qiao Li (Xiamen Univ., China), Daniel Wen (YEESTOR Microelectronics, China), Tei-Wei Kuo (National Taiwan Univ., Mohamed bin Zayed Univ. of Artificial Intelligence, Taiwan), Chun Jason Xue (City Univ. of Hong Kong, Hong Kong) |
Page | pp. 442 - 447 |
Detailed information (abstract, keywords, etc) |
Title | Overlapping Aware Zone Allocation for LSM Tree-Based Store on ZNS SSDs |
Author | *Jingcheng Shen, Lang Yang, Linbo Long, Renping Liu, Zhenhua Tan (Chongqing Univ. of Posts and Telecommunications, China), Congming Gao (Xiamen Univ., China), Yi Jiang (Chongqing Univ. of Posts and Telecommunications, China) |
Page | pp. 448 - 453 |
Detailed information (abstract, keywords, etc) |
Title | Hardware-Software Co-Design of a Collaborative DNN Accelerator for 3D Stacked Memories with Multi-Channel Data |
Author | *Tom Glint (IIT Gandhinagar, India), Manu Awasthi (Ashoka Univ., India), Joycee Mekie (IIT Gandhinagar, India) |
Page | pp. 454 - 459 |
Detailed information (abstract, keywords, etc) |
Title | Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture |
Author | *Liyan Chen, Jianfei Jiang, Qin Wang, Zhigang Mao, Naifeng Jing (Shanghai Jiao Tong Univ., China) |
Page | pp. 460 - 465 |
Detailed information (abstract, keywords, etc) |
Title | Variational Label-Correlation Enhancement for Congestion Prediction |
Author | *Biao Liu, Congyu Qiao, Ning Xu, Xin Geng, Ziran Zhu, Jun Yang (Southeast Univ., China) |
Page | pp. 466 - 471 |
Detailed information (abstract, keywords, etc) |
Title | Fast Cell Library Characterization for Design Technology Co-Optimization Based on Graph Neural Networks |
Author | Tianliang Ma, Zhihui Deng, Xuguang Sun, *Leilai Shao (Shanghai Jiaotong Univ., China) |
Page | pp. 472 - 477 |
Detailed information (abstract, keywords, etc) |
Title | Automated synthesis of mixed-signal ML inference hardware under accuracy constraints |
Author | Kishor Kunal, Jitesh Poojary, S Ramprasath, Ramesh Harjani, *Sachin S. Sapatnekar (Univ. of Minnesota Twin Cities, USA) |
Page | pp. 478 - 483 |
Detailed information (abstract, keywords, etc) |
Title | LayNet: Layout Size Prediction for Memory Design Using Graph Neural Networks in Early Design Stage |
Author | *Hye Rim Ji, Jong Seong Kim, Jung Yun Choi (Samsung Electronics, Republic of Korea), Jee Hyong Lee (Sungkyunkwan Univ., Republic of Korea) |
Page | pp. 484 - 490 |
Detailed information (abstract, keywords, etc) |
Title | QcAssert: Quantum Device Testing with Concurrent Assertions |
Author | *Hasini Dilanka Witharana, Daniel Volya, Prabhat Mishra (Univ. of Florida, USA) |
Page | pp. 491 - 496 |
Detailed information (abstract, keywords, etc) |
Title | HybMT: Hybrid Meta-Predictor based ML Algorithm for Fast Test Vector Generation |
Author | *Shruti Pandey, Jayadeva, Smruti R. Sarangi (Indian Inst. of Tech. Delhi, India) |
Page | pp. 497 - 502 |
Detailed information (abstract, keywords, etc) |
Title | A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver |
Author | *Zhiteng Chao (State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences/CASTEST, China), Xindi Zhang (Univ. of Chinese Academy of Sciences/Chinese Academy of Sciences, China), Junying Huang (Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China), Jing Ye (State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences/CASTEST, China), Shaowei Cai (Univ. of Chinese Academy of Sciences/Chinese Academy of Sciences, China), Huawei Li, Xiaowei Li (State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences/CASTEST, China) |
Page | pp. 503 - 508 |
Detailed information (abstract, keywords, etc) |
Title | A Dynamic Testing Scheme for Resistive-Based Computation-In-Memory Architectures |
Author | *Sina Bakhtavari Mamaghani, Priyanjana Pal, Mehdi Baradaran Tahoori (Karlsruhe Inst. of Tech., Germany) |
Page | pp. 509 - 514 |
Detailed information (abstract, keywords, etc) |
Title | SWAT: An Efficient Swin Transformer Accelerator Based on FPGA |
Author | *Qiwei Dong, Xiaoru Xie, Zhongfeng Wang (Nanjing Univ., China) |
Page | pp. 515 - 520 |
Detailed information (abstract, keywords, etc) |
Title | TransFRU: Efficient Deployment of Transformers on FPGA with Full Resource Utilization |
Author | *Hongji Wang, Yueyin Bai, Jun Yu, Kun Wang (Fudan Univ., China) |
Page | pp. 521 - 526 |
Detailed information (abstract, keywords, etc) |
Title | Booth-NeRF: An FPGA Accelerator for Instant-NGP Inference with Novel Booth-Multiplier |
Author | *Zihang Ma, Zeyu Li, Yuanfang Wang, Yu Li, Jun Yu, Kun Wang (Fudan Univ., China) |
Page | pp. 527 - 532 |
Detailed information (abstract, keywords, etc) |
Title | ACane: An Efficient FPGA-based Embedded Vision Platform with Accumulation-as-Convolution Packing for Autonomous Mobile Robots |
Author | *Jinho Yang, Sungwoong Yune, Sukbin Lim, Donghyuk Kim, Joo-Young Kim (KAIST, Republic of Korea) |
Page | pp. 533 - 538 |
Detailed information (abstract, keywords, etc) |
Title | (Designers' Forum) AI for Chip Design & EDA: Everything, Everywhere, All at Once (?) |
Author | David Pan (Univ. of Texas, Austin, USA) |
Detailed information (abstract, etc) |
Title | (Designers' Forum) How Engineers can Leverage AI Solutions in Chip Design |
Author | Erick Chao (Cadence Design Systems, Taiwan) |
Detailed information (abstract, etc) |
Title | (Designers' Forum) AI/ML Empowered Semiconductor Memory Design: An Industry Vision |
Author | Hyojin Choi (Samsung Electronics, Republic of Korea) |
Detailed information (abstract, etc) |
Title | (Designers' Forum) ML for Computational Lithography: What Will Work and What Will Not? |
Author | Youngsoo Shin (KAIST, Republic of Korea) |
Detailed information (abstract, etc) |
Title | OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration |
Author | *Yung-Chin Chen (National Taiwan Univ./Keio Univ., Taiwan), Shimpei Ando, Daichi Fujiki (Keio Univ., Japan), Shinya Takamaeda-Yamazaki (Univ. of Tokyo, Japan), Kentaro Yoshioka (Keio Univ., Japan) |
Page | pp. 539 - 544 |
Detailed information (abstract, keywords, etc) |
Title | BFP-CIM: Data-Free Quantization with Dynamic Block-Floating-Point Arithmetic for Energy-Efficient Computing-In-Memory-based Accelerator |
Author | *Cheng-Yang Chang, Chi-Tse Huang, Yu-Chuan Chuang, Kuang-Chao Chou, An-Yeu (Andy) Wu (National Taiwan Univ., Taiwan) |
Page | pp. 545 - 550 |
Detailed information (abstract, keywords, etc) |
Title | A Heuristic and Greedy Weight Remapping Scheme with Hardware Optimization for Irregular Sparse Neural Networks Implemented on CIM Accelerator in Edge AI Applications |
Author | *Lizhou Wu, Chenyang Zhao (Fudan Univ., China), Jingbo Wang (Tongji Univ., China), Xueru Yu, Shoumian Chen, Chen Li (Shanghai Integrated Circuits R&D Center, China), Jun Han, Xiaoyong Xue, Xiaoyang Zeng (Fudan Univ., China) |
Page | pp. 551 - 556 |
Detailed information (abstract, keywords, etc) |
Title | PRIMATE: Processing in Memory Acceleration for Dynamic Token-pruning Transformers |
Author | *Yue Pan, Minxuan Zhou (Univ. of California, San Diego, USA), Chonghan Lee, Zheyu Li, Rishika Kushwah, Vijaykrishnan Narayanan (Pennsylvania State Univ., USA), Tajana Rosing (Univ. of California, San Diego, USA) |
Page | pp. 557 - 563 |
Detailed information (abstract, keywords, etc) |
Title | Adaptive Control-Logic Routing for Fully Programmable Valve Array Biochips Using Deep Reinforcement Learning |
Author | *Huayang Cai, Genggeng Liu, Wenzhong Guo (Fuzhou Univ., China), Zipeng Li (Silicon Engineering Group, Apple, Cupertino, CA, USA), Tsung-Yi Ho (Chinese Univ. of Hong Kong, Hong Kong), Xing Huang (Northwestern Polytechnical Univ., China) |
Page | pp. 564 - 569 |
Detailed information (abstract, keywords, etc) |
Title | Towards Automated Testing of Multiplexers in Fully Programmable Valve Array Biochips |
Author | Genggeng Liu, *Yuqin Zeng, Yuhan Zhu, Huayang Cai, Wenzhong Guo (Fuzhou Univ., China), Zipeng Li (Silicon Engineering Group, Apple, Cupertino, CA, USA), Tsung-Yi Ho (Chinese Univ. of Hong Kong, Hong Kong), Xing Huang (Northwestern Polytechnical Univ., China) |
Page | pp. 570 - 575 |
Detailed information (abstract, keywords, etc) |
Title | The Need for Speed: Efficient Exact Simulation of Silicon Dangling Bond Logic |
Author | *Jan Drewniok, Marcel Walter (Tech. Univ. of Munich, Germany), Robert Wille (Technical Univ. of Munich/Software Competence Center Hagenberg GmbH, Germany) |
Page | pp. 576 - 581 |
Detailed information (abstract, keywords, etc) |
Title | Towards Multiphase Clocking in Single-Flux Quantum Systems |
Author | *Rassul Bairamkulov, Giovanni De Micheli (EPFL, Switzerland) |
Page | pp. 582 - 587 |
Detailed information (abstract, keywords, etc) |
Title | Algebraic and Boolean Methods for SFQ Superconducting Circuits |
Author | *Alessandro Tempia Calvino, Giovanni De Micheli (EPFL, Switzerland) |
Page | pp. 588 - 593 |
Detailed information (abstract, keywords, etc) |
Title | LOOPLock 3.0: A Robust Cyclic Logic Locking Approach |
Author | Pei-Pei Chen, Xiang-Min Yang, *Yu-Cheng He (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (National Taiwan Univ. of Science and Tech., Taiwan), Yi-Ting Li, Chun-Yao Wang (National Tsing Hua Univ., Taiwan) |
Page | pp. 594 - 599 |
Detailed information (abstract, keywords, etc) |
Title | Logic Locking over TFHE for Securing User Data and Algorithms |
Author | *Kohei Suemitsu, Kotaro Matsuoka, Takashi Sato, Masanori Hashimoto (Kyoto Univ., Japan) |
Page | pp. 600 - 605 |
Detailed information (abstract, keywords, etc) |
Title | LIPSTICK: Corruptibility-Aware and Explainable Graph Neural Network-based Oracle-Less Attack on Logic Locking |
Author | Yeganeh Aghamohammadi (Univ. of California, Santa Barbara, USA), *Amin Rezaei (California State Univ., Long Beach, USA) |
Page | pp. 606 - 611 |
Detailed information (abstract, keywords, etc) |
Title | Power Side-Channel Analysis and Mitigation for Neural Network Accelerators based on Memristive Crossbars |
Author | *Brojogopal Sapui, Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany) |
Page | pp. 612 - 617 |
Detailed information (abstract, keywords, etc) |
Title | Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits |
Author | *Kazuki Minamiguchi, Yoshihiro Midoh, Noriyuki Miura, Jun Shiomi (Osaka Univ., Japan) |
Page | pp. 618 - 624 |
Detailed information (abstract, keywords, etc) |
Title | SPIRAL: Signal-Power Integrity Co-Analysis for High-Speed Inter-Chiplet Serial Links Validation |
Author | *Xiao Dong, Songyu Sun, Yangfan Jiang (Zhejiang Univ., China), Jingtong Hu (Univ. of Pittsburgh, USA), Dawei Gao (Zhejiang Univ./Zhejiang ICsprout Semiconductor, China), Cheng Zhuo (Zhejiang Univ./Key Laboratory of Collaborative Sensing and Autonomous Unmanned Systems of Zhejiang Province, China) |
Page | pp. 625 - 630 |
Detailed information (abstract, keywords, etc) |
Title | Nested Dissection Based Parallel Transient Power Grid Analysis on Public Cloud Virtual Machines |
Author | *Jiawen Cheng, Zhiqiang Liu, Lingjie Li, Wenjian Yu (Tsinghua Univ., China) |
Page | pp. 631 - 637 |
Detailed information (abstract, keywords, etc) |
Title | Efficient Sublogic-Cone-Based Switching Activity Estimation using Correlation Factor |
Author | *Kexin Zhu (Tongji Univ., China), Runjie Zhang (Phlexing, China), Qing He (Tongji Univ., China) |
Page | pp. 638 - 643 |
Detailed information (abstract, keywords, etc) |
Title | ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning |
Author | *Hyunsu Chae, Keren Zhu (Univ. of Texas, Austin, USA), Bhyrav Mutnury (Dell Infrastructure Solutions Group, USA), Zixuan Jiang (Univ. of Texas, Austin, USA), Daniel de Araujo (Siemens EDA, USA), Douglas Wallace, Douglas Winterberg (Dell Infrastructure Solutions Group, USA), Adam Klivans, David Z. Pan (Univ. of Texas, Austin, USA) |
Page | pp. 644 - 650 |
Detailed information (abstract, keywords, etc) |
Title | Physics-Informed Learning for EPG-Based TDDB Assessment |
Author | Dinghao Chen, *Wenjie Zhu, Xiaoman Yang, Pengpeng Ren, Zhigang Ji, Hai-Bao Chen (Shanghai Jiao Tong Univ., China) |
Page | pp. 651 - 656 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Toward End-to-End Analog Design Automation with ML and Data-Driven Approaches |
Author | Supriyo Maji (Univ. of Texas, Austin, USA), Ahmet F. Budak (Univ. of Texas, Austin/Analog Devices, USA), Souradip Poddar, *David Z. Pan (Univ. of Texas, Austin, USA) |
Page | pp. 657 - 664 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Reinforcing the Connection between Analog Design and EDA |
Author | Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, Ramprasath S, Arvind K. Sharma, Ramesh Harjani, *Sachin S. Sapatnekar (Univ. of Minnesota, USA) |
Page | pp. 665 - 670 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation |
Author | *Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi (Fudan Univ., China), Keren Zhu (Chinese Univ. of Hong Kong, China), Fan Yang, Changhao Yan (Fudan Univ., China), Dian Zhou (Univ. of Texas, Dallas, USA), Xuan Zeng (Fudan Univ., China) |
Page | pp. 671 - 678 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Performance-Driven Analog Layout Automation: Current Status and Future Directions |
Author | Peng Xu, Jintao Li, Tsung-Yi Ho, Bei Yu, *Keren Zhu (Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 679 - 685 |
Detailed information (abstract, keywords, etc) |
Title | (Keynote Address) AI/ML and EDA: Current Status and Perspectives on the Future |
Author | Andrew B. Kahng (Univ. of California San Diego, USA) |
Detailed information (abstract, etc) |
Thursday, January 25, 2024 |
Title | The Optimal Quantum of Temporal Decoupling |
Author | *Niko Zurstraßen, Ruben Brandhofer, José Cubero-Cascante, Nils Bosbach (RWTH Aachen Univ., Germany), Lukas Jünger (MachineWare GmbH, Germany), Rainer Leupers (RWTH Aachen Univ., Germany) |
Page | pp. 686 - 691 |
Detailed information (abstract, keywords, etc) |
Title | Towards a Highly Interactive Design-Debug-Verification Cycle |
Author | *Lucas Klemmer, Daniel Groβe (Johannes Kepler Univ. Linz, Austria) |
Page | pp. 692 - 697 |
Detailed information (abstract, keywords, etc) |
Title | Beyond Time-Quantum: A Basic-Block FDA Approach for Accurate System Computing Performance Estimation |
Author | Hsuan-Yi Lin, *Ren-Song Tsay (National Tsing Hua Univ., Taiwan) |
Page | pp. 698 - 703 |
Detailed information (abstract, keywords, etc) |
Title | BoostIID: Fault-agnostic Online Detection of WCET Changes in Autonomous Driving |
Author | *Saehanseul Yi, Nikil Dutt (Univ. of California, Irvine, USA) |
Page | pp. 704 - 709 |
Detailed information (abstract, keywords, etc) |
Title | KalmanHD: Robust On-Device Time Series Forecasting with Hyperdimensional Computing |
Author | *Ivannia Gomez Moreno (CETYS Univ. Campus Tijuana, Mexico), Xiaofan Yu, Tajana Rosing (Univ. of California, San Diego, USA) |
Page | pp. 710 - 715 |
Detailed information (abstract, keywords, etc) |
Title | HyperFeel: An Efficient Federated Learning Framework Using Hyperdimensional Computing |
Author | *Haomin Li, Fangxin Liu (Shanghai Jiao Tong Univ., China), Yichi Chen (Tianjin Univ., China), Li Jiang (Shanghai Jiao Tong Univ., China) |
Page | pp. 716 - 721 |
Detailed information (abstract, keywords, etc) |
Title | RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model |
Author | *Yao Lu, Shang Liu, Qijun Zhang, Zhiyao Xie (Hong Kong Univ. of Science and Tech., Hong Kong) |
Page | pp. 722 - 727 |
Detailed information (abstract, keywords, etc) |
Title | LSTP : A Logic Synthesis Timing Predictor |
Author | *Haisheng Zheng (Shanghai AI Laboratory, China), Zhuolun He, Fangzhou Liu, Zehua Pei (Shanghai AI Laboratory/Chinese Univ. of Hong Kong, Hong Kong), Bei Yu (Chinese Univ. of Hong Kong, Hong Kong) |
Page | pp. 728 - 733 |
Detailed information (abstract, keywords, etc) |
Title | Bridging the Design Methodologies of Burst-Mode Specifications and Signal Transition Graphs |
Author | *Alex Chan (Newcastle Univ., UK), Danil Sokolov, Victor Khomenko (Dialog Semiconductor (Renasas), UK), Alex Yakovlev (Newcastle Univ., UK) |
Page | pp. 734 - 739 |
Detailed information (abstract, keywords, etc) |
Title | Signature Driven Post-Manufacture Testing and Tuning of RRAM Spiking Neural Networks for Yield Recovery |
Author | Anurup Saha, Chandramouli Amarnath, *Kwondo Ma, Abhijit Chatterjee (Georgia Tech, USA) |
Page | pp. 740 - 745 |
Detailed information (abstract, keywords, etc) |
Title | Physics-Informed Learning for Versatile RRAM Reset and Retention Simulation |
Author | *Tianshu Hou (Shanghai Jiao Tong Univ., China), Yuan Ren, Wenyong Zhou, Can Li, Zhongrui Wang (Univ. of Hong Kong, Hong Kong), Hai-Bao Chen (Shanghai Jiao Tong Univ., China), Ngai Wong (Univ. of Hong Kong, Hong Kong) |
Page | pp. 746 - 751 |
Detailed information (abstract, keywords, etc) |
Title | Hard Error Correction in STT-MRAM |
Author | *Surendra Hemaram, Mehdi B Tahoori (Karlsruhe Inst. of Tech. (KIT), Germany), Francky Catthoor, Siddharth Rao, Sebastien Couet, Gouri Sankar Kar (IMEC, Belgium) |
Page | pp. 752 - 757 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Exploiting 2.5D/3D Heterogeneous Integration for AI Computing |
Author | Zhenyu Wang, Jingbo Sun (Arizona State Univ., USA), Alper Goksoy (Univ. of Wisconsin-Madison, USA), Sumit Kumar Mandal (Indian Institute of Science, India), Yaotian Liu (Arizona State Univ., USA), Jae-sun Seo (Cornell Tech, USA), Chaitali Chakrabarti (Arizona State Univ., USA), Umit Y. Ogras (Univ. of Wisconsin-Madison, USA), Vidya Chhabria, Jeff Zhang (Arizona State Univ., USA), *Yu Cao (Univ. of Minnesota, USA) |
Page | pp. 758 - 764 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Challenges and Opportunities to Enable Large-scale Computing via Heterogeneous Chiplets |
Author | Zhuoping Yang, Shixin Ji, Xingzhen Chen, Jinming Zhuang (Univ. of Pittsburgh, USA), *Weifeng Zhang (Lightelligence Inc, USA), Dharmesh Jani (Meta, USA), Peipei Zhou (Univ. of Pittsburgh, USA) |
Page | pp. 765 - 770 |
Detailed information (abstract, keywords, etc) |
Title | (Invited Paper) Heterogeneous Microelectronics Codesign for Edge Sensing at Deep Cryogenic Temperatures |
Author | Jeff Fredenburg (Fermilab, USA) |
Detailed information |
Title | (Invited Paper) Towards Automated Generation of Chiplet-Based System |
Author | *Ankur Limaye, Claudio Barone, Nicolas Bohm Agostini, Marco Minutoli, Joseph Manzano, Vito Giovanni Castellana (Pacific Northwest National Laboratory, USA), Giovanni Gozzi, Michele Fiorito, Serena Curzel (Politecnico di Milano, Italy), Fabrizio Ferrandi (Politecnico di Milano, USA), Antonino Tumeo (Pacific Northwest National Laboratory, USA) |
Page | pp. 771 - 776 |
Detailed information (abstract, keywords, etc) |
Title | (Keynote Address) Unleashing the Future of IC Design with AI Innovation |
Author | Erick Chao (Cadence Design Systems, Taiwan) |
Detailed information (abstract, etc) |
Title | Flexible Spatio-Temporal Energy-Efficient Runtime Management |
Author | *Robert Khasanov, Marc Dietrich, Jeronimo Castrillon (TU Dresden, Germany) |
Page | pp. 777 - 784 |
Detailed information (abstract, keywords, etc) |
Title | Sparse-Sparse Matrix Multiplication Accelerator on FPGA featuring Distribute-Merge Product Dataflow |
Author | *Yuta Nagahara, Jiale Yan, Kazushi Kawamura, Masato Motomura, Thiem Van Chu (Tokyo Inst. of Tech., Japan) |
Page | pp. 785 - 791 |
Detailed information (abstract, keywords, etc) |
Title | Meeting Job-Level Dependencies by Task Merging |
Author | *Matthias Becker (Royal Inst. of Tech., Sweden) |
Page | pp. 792 - 798 |
Detailed information (abstract, keywords, etc) |
Title | A CGRA Front-end Compiler Enabling Extraction of General Control and Dedicated Operators |
Author | *Xuchen Gao, Yunhui Qiu, Yuan Dai, Wenbo Yin, Lingli Wang (Fudan Univ., China) |
Page | pp. 799 - 804 |
Detailed information (abstract, keywords, etc) |
Title | LOSSS- Logic Synthesis based on Several Stateful logic gates for high time-efficient computing |
Author | Yihong Hu (National Univ. of Defense Tech., China), *Nuo Xu, Chaochao Feng (National Univ. of Defense Tech./Key Laboratory of Advanced Microprocessor Chips and Systems, China), Wei Tong (Huazhong Univ. of Science and Tech., China), Kang Liu, Liang Fang (National Univ. of Defense Tech., China) |
Page | pp. 805 - 811 |
Detailed information (abstract, keywords, etc) |
Title | Towards Area-Efficient Path-Based In-Memory Computing using Graph Isomorphisms |
Author | Sven Thijssen, *Muhammad Rashedul Haq Rashed, Hao Zheng (Univ. of Central Florida, USA), Sumit Kumar Jha (Florida International Univ., USA), Rickard Ewetz (Univ. of Central Florida, USA) |
Page | pp. 812 - 817 |
Detailed information (abstract, keywords, etc) |
Title | READ-based In-Memory Computing using Sentential Decision Diagrams |
Author | Sven Thijssen, *Muhammad Rashedul Haq Rashed (Univ. of Central Florida, USA), Sumit Kumar Jha (Florida International Univ., USA), Rickard Ewetz (Univ. of Central Florida, USA) |
Page | pp. 818 - 823 |
Detailed information (abstract, keywords, etc) |
Title | ConvFIFO: A Crossbar Memory PIM Architecture for ConvNets Featuring First-In-First-Out Dataflow |
Author | *Liang Zhao, Yu Qian, Fanzi Meng, Xiapeng Xu, Xunzhao Yin, Cheng Zhuo (Zhejiang Univ., China) |
Page | pp. 824 - 829 |
Detailed information (abstract, keywords, etc) |
Title | MINT: Multiplier-less Integer Quantization for Energy Efficient Spiking Neural Networks |
Author | *Ruokai Yin, Yuhang Li, Abhishek Moitra, Priyadarshini Panda (Yale Univ., USA) |
Page | pp. 830 - 835 |
Detailed information (abstract, keywords, etc) |
Title | TQ-TTFS: High-Accuracy and Energy-Efficient Spiking Neural Networks Using Temporal Quantization Time-to-First-Spike Neuron |
Author | *Yuxuan Yang, Zihao Xuan, Yi Kang (Univ. of Science and Tech. of China, China) |
Page | pp. 836 - 841 |
Detailed information (abstract, keywords, etc) |
Title | TEAS: Exploiting Spiking Activity for Temporal-wise Adaptive Spiking Neural Networks |
Author | *Fangxin Liu, Haomin Li, Ning Yang, Zongwu Wang (Shanghai Jiao Tong Univ., China), Tao Yang (Huawei Technologies, China), Li Jiang (Shanghai Jiao Tong Univ., China) |
Page | pp. 842 - 847 |
Detailed information (abstract, keywords, etc) |
Title | SOLSA: Neuromorphic Spatiotemporal Online Learning for Synaptic Adaptation |
Author | Zhenhang Zhang, Jingang Jin, Haowen Fang, *Qinru Qiu (Syracuse Univ., USA) |
Page | pp. 848 - 853 |
Detailed information (abstract, keywords, etc) |
Title | Signed Convolution in Photonics with Phase-Change Materials using Mixed-Polarity Bitstreams |
Author | *Raphael Cardoso, Clément Zrounba (Institut des Nanotechnologies de Lyon, France), Mohab Abdalla (RMIT Univ., France), Paul Jimenez, Mauricio Gomes de Queiroz (Institut des Nanotechnologies de Lyon, France), Benoît Charbonnier (Univ. Grenoble Alpes/CEA LETI, France), Fabio Pavanello (Institut des Nanotechnologies de Lyon/Univ. Grenoble Alpes/Univ. Savoie Mont Blanc, France), Ian O'Connor (Institut des Nanotechnologies de Lyon, France), Sébastien Le Beux (Univ. of Concordia, Canada) |
Page | pp. 854 - 859 |
Detailed information (abstract, keywords, etc) |
Title | An Efficient Branch-and-Bound Routing Algorithm for Optical NoCs |
Author | *Yihao Liu, Yaoyao Ye (Shanghai Jiao Tong Univ., China) |
Page | pp. 860 - 865 |
Detailed information (abstract, keywords, etc) |
Title | Boosting Graph Spectral Sparsification via Parallel Sparse Approximate Inverse of Cholesky Factor |
Author | *Baiyu Chen, Zhiqiang Liu, Yibin Zhang, Wenjian Yu (Tsinghua Univ., China) |
Page | pp. 866 - 871 |
Detailed information (abstract, keywords, etc) |
Title | Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing |
Author | *Xuyang Zhao, Zhaori Bi, Changhao Yan, Fan Yang, Ye Lu (Fudan Univ., China), Dian Zhou (Univ. of Texas, Dallas, USA), Xuan Zeng (Fudan Univ., China) |
Page | pp. 872 - 877 |
Detailed information (abstract, keywords, etc) |
Title | (Joint Workshop) Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors |
Author | Jeong-taek Kong, SoYoung Kim (Sungkyunkwan Univ., Republic of Korea) |
Detailed information |
Title | (Joint Workshop) Fast Timing/Power Library Generation Using Machine Learning |
Author | Daijoon Hyun (Sejong Univ., Republic of Korea) |
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Title | (Joint Workshop) Clustering-Based Methodology for Fast and Improved Placement of Large-Scale Designs |
Author | Andrew Kahng (UCSD, USA) |
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Title | (Joint Workshop) Routability Prediction and Optimization Using Machine Learning Techniques |
Author | Seokhyeong Kang (POSTECH, Republic of Korea) |
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Title | Quantization-aware Optimization Approach for CNNs Inference on CPUs |
Author | *Jiasong Chen, Zeming Xie, Weipeng Liang, Bosheng Liu, Xin Zheng, Jigang Wu, Xiaoming Xiong (Guangdong Univ. of Tech., China) |
Page | pp. 878 - 883 |
Detailed information (abstract, keywords, etc) |
Title | TSTC: Enabling Efficient Training via Structured Sparse Tensor Compilation |
Author | *Shiyuan Huang, Fangxin Liu (Shanghai Jiao Tong Univ., China), Tian Li (Huawei Technologies, China), Zongwu Wang, Haomin Li, Li Jiang (Shanghai Jiao Tong Univ., China) |
Page | pp. 884 - 889 |
Detailed information (abstract, keywords, etc) |
Title | An automated approach for improving the inference latency and energy efficiency of pretrained CNNs by removing irrelevant pixels with focused convolutions |
Author | Caleb Tung, Nicholas Eliopoulos, Purvish Jajal, Gowri Ramshankar, Chen-Yun Yang (Purdue Univ., USA), Nicholas Synovic (Loyola Univ. Chicago, USA), Xuecen Zhang, Vipin Chaudhary (Case Western Reserve Univ., USA), *George K. Thiruvathukal (Loyola Univ. Chicago, USA), Yung-Hsiang Lu (Purdue Univ., USA) |
Page | pp. 890 - 895 |
Detailed information (abstract, keywords, etc) |
Title | PIONEER: Highly Efficient and Accurate Hyperdimensional Computing using Learned Projection |
Author | *Fatemeh Asgarinejad (Univ. of California San Diego/San Diego State Univ., USA), Justin Morris (California State Univ. San Marcos, USA), Tajana Rosing (Univ. of California San Diego, USA), Baris Aksanli (San Diego State Univ., USA) |
Page | pp. 896 - 901 |
Detailed information (abstract, keywords, etc) |
Title | Logic Design of Neural Networks for High-Throughput and Low-Power Applications |
Author | *Kangwei Xu (Tech. Univ. of Munich, Germany), Grace Li Zhang (Technical Univ. of Darmstadt, Germany), Ulf Schlichtmann, Bing Li (Tech. Univ. of Munich, Germany) |
Page | pp. 902 - 907 |
Detailed information (abstract, keywords, etc) |
Title | Exact Scheduling to Minimize Off-Chip Data Movement for Deep Learning Accelerators |
Author | Yi Li, Aarti Gupta, *Sharad Malik (Princeton Univ., USA) |
Page | pp. 908 - 914 |
Detailed information (abstract, keywords, etc) |
Title | Run-time Non-uniform Quantization for Dynamic Neural Networks in Wireless Communication |
Author | *Priscilla Sharon Allwin, Manil Dev Gomony, Marc Geilen (Eindhoven Univ. of Tech., Netherlands) |
Page | pp. 915 - 920 |
Detailed information (abstract, keywords, etc) |
Title | PipeFuser: Building Flexible Pipeline Architecture for DNN Accelerators via Layer Fusion |
Author | Xilang Zhou, *Shuyang Li (Fudan Univ., China), Haodong Lu (Nanjing Univ. of Posts and Telecommunications, China), Kun Wang (Fudan Univ., China) |
Page | pp. 921 - 926 |
Detailed information (abstract, keywords, etc) |
Title | A Precision-Scalable RISC-V DNN Processor with On-Device Learning Capability at the Extreme Edge |
Author | *Longwei Huang, Chao Fang, Qiong Li, Jun Lin, Zhongfeng Wang (Nanjing Univ., China) |
Page | pp. 927 - 932 |
Detailed information (abstract, keywords, etc) |
Title | Microscope: Causality Inference Crossing the Hardware and Software Boundary from Hardware Perspective |
Author | Zhaoxiang Liu, Kejun Chen (Kansas State Univ., USA), Dean Sullivan (Univ. of New Hampshire, USA), Orlando Arias (Univ. of Massachusetts Lowel, USA), Raj Dutta (Silicon Assurance, USA), *Yier Jin (Univ. of Science and Tech. of China, USA), Xiaolong Guo (Kansas State Univ., USA) |
Page | pp. 933 - 938 |
Detailed information (abstract, keywords, etc) |
Title | d-GUARD: Thwarting Denial-of-Service Attacks via Hardware Monitoring of Information Flow using Language Semantics in Embedded Systems |
Author | Garett Cunningham, Harsha Chenji, *David Juedes, Avinash Karanth (Ohio Univ., USA) |
Page | pp. 939 - 944 |
Detailed information (abstract, keywords, etc) |
Title | Security Coverage Metrics for Information Flow at the System Level |
Author | *Ece Nur Demirhan Coşkun (DFKI GmbH, Germany), Sallar Ahmadi-Pour (Univ. of Bremen, Germany), Muhammad Hassan, Rolf Drechsler (Univ. of Bremen/DFKI GmbH, Germany) |
Page | pp. 945 - 950 |
Detailed information (abstract, keywords, etc) |
Title | Theoretical Patchability Quantification for IP-Level Hardware Patching Designs |
Author | *Wei-Kai Liu (Duke Univ., USA), Benjamin Tan (Univ. of Calgary, Canada), Jason M. Fung (Intel, USA), Krishnendu Chakrabarty (Arizona State Univ., USA) |
Page | pp. 951 - 956 |
Detailed information (abstract, keywords, etc) |
Title | Multiplierless Design of High-Speed Very Large Constant Multiplications |
Author | *Levent Aksoy (Tallinn Univ. of Tech., Estonia), Debapriya Basu Roy (Indian Inst. of Tech. Kanpur, India), Malik Imran, Samuel Pagliarini (Tallinn Univ. of Tech., Estonia) |
Page | pp. 957 - 962 |
Detailed information (abstract, keywords, etc) |
Title | V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting |
Author | *Ping Zhang, Pengju Yao (Fuzhou Univ., China), Xingquan Li (Pengcheng Laboratory, China), Bei Yu (Chinese Univ. of Hong Kong, Hong Kong), Wenxing Zhu (Fuzhou Univ., China) |
Page | pp. 963 - 968 |
Detailed information (abstract, keywords, etc) |
Title | A Fast and Robust Global Router with Capacity Reduction Techniques |
Author | *Yun-Kai Fang, Ye-Chih Lin, Ting-Chi Wang (National Tsing Hua Univ., Taiwan) |
Page | pp. 969 - 974 |
Detailed information (abstract, keywords, etc) |
Title | A High Performance Detailed Router Based on Integer Programming with Adaptive Route Guides |
Author | Zhongdong Qi, *Shizhe Hu, Qi Peng, Hailong You, Chao Han, Zhangming Zhu (Xidian Univ., China) |
Page | pp. 975 - 980 |
Detailed information (abstract, keywords, etc) |
Title | (Joint Workshop) ML Assisted DTCO Framework & Physical Design Optimization using DSO |
Author | Kyumyung Choi, Taewhan Kim (Seoul National Univ., Republic of Korea) |
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Title | (Joint Workshop) Differential Design Search: A Learning-Based Optimization Framework for EDA |
Author | Jaeyong Jung (Incheon National Univ., Republic of Korea) |
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Title | (Joint Workshop) AI-Based Design Optimization of SRAM-MRAM Hybrid Cache and On-Chip Interconnection Network |
Author | Eui-young Chung (Yonsei Univ., Republic of Korea) |
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Title | (Joint Workshop) ML/AI and Cross Layer Optimizations for Electronic and Photonic Design Automation |
Author | David Pan (Univ. of Texas, Austin, USA) |
Detailed information |