| Monday, January 16, 2023 |
| Tuesday, January 17, 2023 |
| Wednesday, January 18, 2023 |
| Thursday, January 19, 2023 |
| Monday, January 16, 2023 |
| Title | (Tutorial) Optimization Problems for Design Automation of Microfluidic Biochips: Scope of Machine Learning |
| Author | Sudip Roy (Indian Inst. of Tech. Roorkee, India), Shigeru Yamashita (Ritsumeikan Univ., Japan), Debraj Kundu (Indian Inst. of Tech. Roorkee, India) |
| Detailed information (abstract, etc) | |
| Title | (Tutorial) Cryogenic Memory Technologies: A Device-to-System Perspective |
| Author | Ahmedullah Aziz (Univ. of Tennessee Knoxville, USA) |
| Detailed information (abstract, etc) | |
| Title | (Tutorial) Quantum Annealing for EDA and Its Hands-on Training |
| Author | Takuji Hiraoka (Fixstars Amplify, Japan), Koji Mizumatsu (Fixstars, Japan), Takahisa Todoroki (Fixstars Amplify, Japan), Yukihide Kohira (Univ. of Aizu, Japan) |
| Detailed information (abstract, etc) | |
| Title | (Tutorial) The Evolution of Functional Verification: SystemVerilog, UVM, and Portable Stimulus |
| Author | Tom Fitzpatrick (Siemens Digital Industries Software) |
| Detailed information (abstract, etc) | |
| Title | (Tutorial) Design Methods and Computing Paradigms based on Flexible Inorganic Printed Electronics |
| Author | Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany) |
| Detailed information (abstract, etc) | |
| Title | (Tutorial) HW/SW Codesign for Reliable In-Memory Computing on Unreliable Technologies: Journey from Beyond-CMOS to Beyond-von Neumann |
| Author | Hussam Amrouch (Univ. of Stuttgart, Germany) |
| Detailed information (abstract, etc) | |
| Title | (Tutorial) Agile Hardware and Software Co-Design |
| Author | Yun Eric Liang (Peking Univ., China), Cheng Zhuo (Zhejiang Univ., China), Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong) |
| Detailed information (abstract, etc) | |
| Tuesday, January 17, 2023 |
| Title | ASP-DAC 2023 Opening |
| Detailed information | |
| Title | (Keynote Address) More Moore, More than Moore, More People |
| Author | Tadahiro Kuroda (Univ. of Tokyo, Japan) |
| Detailed information (abstract, etc) | |
| Title | A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees using Matrix Exponential |
| Author | *Pavlos Stoikos, George Floros, Dimitrios Garyfallou, Nestor Evmorfopoulos, George Stamoulis (Univ. of Thessaly, Greece) |
| Page | pp. 1 - 6 |
| Detailed information (abstract, keywords, etc) | |
| Title | Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal Consideration |
| Author | *Hong-Wen Chiou, Jia-Hao Jiang, Yu-Teng Chang, Yu-Min Lee, Chi-Wen Pan (National Yang Ming Chiao Tung Univ., Taiwan) |
| Page | pp. 7 - 12 |
| Detailed information (abstract, keywords, etc) | |
| Title | An On-line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs |
| Author | *Yu-Guang Chen, Po-Yeh Huang, Jin-Fu Li (National Central Univ., Taiwan) |
| Page | pp. 13 - 18 |
| Detailed information (abstract, keywords, etc) | |
| Title | Automated Equivalence Checking Method for Majority based In-Memory Computing on ReRAM Crossbars |
| Author | *Arighna Deb (School of Electronics Engineering, KIIT DU, India), Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh (German Research Centre for Artificial Intelligence (DFKI), Germany), Rolf Drechsler (Univ. of Bremen, Germany) |
| Page | pp. 19 - 25 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Equivalence Checking Framework for Agile Hardware Design |
| Author | *Yanzhao Wang, Fei Xie (Portland State Univ., USA), Zhenkun Yang, Pasquale Cocchini, Jin Yang (Intel Labs, USA) |
| Page | pp. 26 - 32 |
| Detailed information (abstract, keywords, etc) | |
| Title | Towards High-Bandwidth-Utilization SpMV on FPGAs via Partial Vector Duplication |
| Author | *Bowen Liu, Dajiang Liu (Chongqing Univ., China) |
| Page | pp. 33 - 38 |
| Detailed information (abstract, keywords, etc) | |
| Title | Safety-driven Interactive Planning for Neural Network-based Lane Changing |
| Author | *Xiangguo Liu, Ruochen Jiao (Northwestern Univ., USA), Bowen Zheng, Dave Liang (Pony.ai, USA), Qi Zhu (Northwestern Univ., USA) |
| Page | pp. 39 - 45 |
| Detailed information (abstract, keywords, etc) | |
| Title | Safety-Aware Flexible Schedule Synthesis for Cyber-Physical Systems using Weakly-Hard Constraints |
| Author | *Shengjie Xu, Bineet Ghosh, Clara Hobbs (Univ. of North Carolina, Chapel Hill, USA), P. S. Thiagarajan (Chennai Mathematical Institute, India/Univ. of North Carolina, Chapel Hill, USA), Samarjit Chakraborty (Univ. of North Carolina, Chapel Hill, USA) |
| Page | pp. 46 - 51 |
| Detailed information (abstract, keywords, etc) | |
| Title | Mixed-Traffic Intersection Management Utilizing Connected and Autonomous Vehicles as Traffic Regulators |
| Author | *Pin-Chun Chen (National Taiwan Univ., Taiwan), Xiangguo Liu (Northwestern Univ., USA), Chung-Wei Lin (National Taiwan Univ., Taiwan), Chao Huang (Univ. of Liverpool, UK), Qi Zhu (Northwestern Univ., USA) |
| Page | pp. 52 - 57 |
| Detailed information (abstract, keywords, etc) | |
| Title | Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction |
| Author | *Chen-Chia Chang, Jingyu Pan (Duke Univ., USA), Zhiyao Xie (Hong Kong Univ. of Science and Tech., Hong Kong), Yaguang Li, Yishuang Lin, Jiang Hu (Texas A&M Univ., USA), Yiran Chen (Duke Univ., USA) |
| Page | pp. 58 - 63 |
| Detailed information (abstract, keywords, etc) | |
| Title | Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models |
| Author | *Fabio Passos (Instituto de Telecomunicacoes, Portugal), Nuno Lourenco (Instituto de Telecomunicacoes and Univ. de Evora, Portugal), Luis Mendes (Instituto de Telecomunicacoes and Politecnico de Leiria, Portugal), Ricardo Martins (Instituto de Telecomunicacoes, Portugal), Joao Vaz, Nuno Horta (Univ. de Lisboa, Portugal) |
| Page | pp. 64 - 69 |
| Detailed information (abstract, keywords, etc) | |
| Title | APOSTLE: Asynchronously Parallel Optimization for Sizing Analog Transistors using DNN Learning |
| Author | *Ahmet Faruk Budak (Univ. of Texas, Austin, USA), David Smart, Brian Swahn (Analog Devices, USA), David Pan (Univ. of Texas, Austin, USA) |
| Page | pp. 70 - 75 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) ML to the Rescue: Reliability Estimation from Self-Heating and Aging in Transistors all the Way up Processors |
| Author | *Hussam Amrouch, Florian Klemme (Univ. of Stuttgart, Germany) |
| Page | pp. 76 - 82 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs |
| Author | *Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu (New York Univ. Abu Dhabi, United Arab Emirates) |
| Page | pp. 83 - 90 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) Detection and Classification of Malicious Bitstreams for FPGAs in Cloud Computing |
| Author | Jayeeta Chaudhuri, *Krishnendu Chakrabarty (Duke Univ., USA) |
| Page | pp. 91 - 97 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) Learning Based Spatial Power Characterization and Full-Chip Power Estimation for Commercial TPUs |
| Author | *Jincong Lu, Jinwei Zhang, Wentian Jin, Sachin Sachdeva, Sheldon X.-D. Tan (Univ. of California, Riverside, USA) |
| Page | pp. 98 - 103 |
| Detailed information (abstract, keywords, etc) | |
| Title | DECC: Differential ECC for Read Performance Optimization on High-Density NAND Flash Memory |
| Author | *Yunpeng Song, Yina Lv, Liang Shi (East China Normal Univ., China) |
| Page | pp. 104 - 109 |
| Detailed information (abstract, keywords, etc) | |
| Title | Optimizing Data Layout for Racetrack Memory in Embedded Systems |
| Author | *Peng Hui, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Rui Xu, Han Wang (East China Normal Univ., China) |
| Page | pp. 110 - 115 |
| Detailed information (abstract, keywords, etc) | |
| Title | Exploring Architectural Implications to Boost Performance for in-NVM B+-tree |
| Author | *Yanpeng Hu, Qisheng Jiang, Chundong Wang (ShanghaiTech Univ., China) |
| Page | pp. 116 - 121 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Efficient Near-Bank Processing Architecture for Personalized Recommendation System |
| Author | *Yuqing Yang, Weidong Yang, Qin Wang, Naifeng Jing, Jianfei Jiang, Zhigang Mao, Weiguang Sheng (Shanghai Jiao Tong Univ., China) |
| Page | pp. 122 - 127 |
| Detailed information (abstract, keywords, etc) | |
| Title | PAALM: Power Density Aware Approximate Logarithmic Multiplier Design |
| Author | *Shuyuan Yu, Sheldon Tan (Univ. of California, Riverside, USA) |
| Page | pp. 128 - 133 |
| Detailed information (abstract, keywords, etc) | |
| Title | Approximate Floating-Point FFT Design with Wide Precision-Range and High Energy Efficiency |
| Author | *Chenyi Wen, Ying Wu, Xunzhao Yin, Cheng Zhuo (Zhejiang Univ., China) |
| Page | pp. 134 - 139 |
| Detailed information (abstract, keywords, etc) | |
| Title | RUCA: RUntime Configurable Approximate Circuits with Self-Correcting Capability |
| Author | *Jingxiao Ma, Sherief Reda (Brown Univ., USA) |
| Page | pp. 140 - 145 |
| Detailed information (abstract, keywords, etc) | |
| Title | Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee |
| Author | Chun-Ting Lee, *Yi-Ting Li (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (National Taiwan Univ. of Science and Tech., Taiwan), Chun-Yao Wang (National Tsing Hua Univ., Taiwan) |
| Page | pp. 146 - 151 |
| Detailed information (abstract, keywords, etc) | |
| Title | Depth-optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits |
| Author | *Alessandro Tempia Calvino, Giovanni De Micheli (EPFL, Switzerland) |
| Page | pp. 152 - 158 |
| Detailed information (abstract, keywords, etc) | |
| Title | Area-driven FPGA Logic Synthesis Using Reinforcement Learning |
| Author | *Guanglei Zhou, Jason H. Anderson (Univ. of Toronto, Canada) |
| Page | pp. 159 - 165 |
| Detailed information (abstract, keywords, etc) | |
| Title | Optimization of Reversible Logic Networks with Gate Sharing |
| Author | *Yung-Chih Chen, Feng-Jie Chao (National Taiwan Univ. of Science and Tech., Taiwan) |
| Page | pp. 166 - 171 |
| Detailed information (abstract, keywords, etc) | |
| Title | Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization |
| Author | *Stephanie Soldavini, Donatella Sciuto, Christian Pilato (Politecnico di Milano, Italy) |
| Page | pp. 172 - 177 |
| Detailed information (abstract, keywords, etc) | |
| Title | ViraEye: An Energy-Efficient Stereo Vision Accelerator with Binary Neural Network in 55 nm CMOS |
| Author | *Yu Zhang, Gang Chen, Tao He, Qian Huang, Kai Huang (Sun Yat-sen Univ., China) |
| Page | pp. 178 - 179 |
| Detailed information (abstract, keywords, etc) | |
| Title | A 1.2nJ/Classification Fully Synthesized All-Digital Asynchronous Wired-Logic Processor Using Quantized Non-linear Function Blocks in 0.18µm CMOS |
| Author | *Rei Sumikawa, Kota Shiba, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda (Univ. of Tokyo, Japan) |
| Page | pp. 180 - 181 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Fully Synthesized 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Data-Reusing Wired-Logic Processor Using Non-Linear Neural Network |
| Author | *Yao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda (Univ. of Tokyo, Japan) |
| Page | pp. 182 - 183 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Multimode Hybrid Memristor-CMOS Prototyping Platform Supporting Digital and Analog Projects |
| Author | *Kamel-Eddine Harabi, Clement Turck, Marie Drouhin, Adrien Renaudineau, Thomas Bersani--Veroni, Damien Querlioz (Univ. Paris-Saclay, CNRS, France), Tifenn Hirtzlin, Elisa Vianello (CEA-LETI, Univ. Grenoble-Alpes, France), Marc Bocquet, Jean-Michel Portal (Aix-Marseille Univ., CNRS, France) |
| Page | pp. 184 - 185 |
| Detailed information (abstract, keywords, etc) | |
| Title | A fully synchronous digital LDO with built-in adaptive frequency modulation and implicit dead-zone control |
| Author | *Shun Yamaguchi, Mahfuzul Islam, Takashi Hisakado, Osami Wada (Kyoto Univ., Japan) |
| Page | pp. 186 - 187 |
| Detailed information (abstract, keywords, etc) | |
| Title | Demonstration of Order Statistics Based Flash ADC in a 65nm Process |
| Author | *Mahfuzul Islam, Takehiro Kitamura, Takashi Hisakado, Osami Wada (Kyoto Univ., Japan) |
| Page | pp. 188 - 189 |
| Detailed information (abstract, keywords, etc) | |
| Title | A SAT Encoding for Optimal Clifford Circuit Synthesis |
| Author | Sarah Schneider, *Lukas Burgholzer (Johannes Kepler Univ. Linz, Austria), Robert Wille (Tech. Univ. of Munich, Germany) |
| Page | pp. 190 - 195 |
| Detailed information (abstract, keywords, etc) | |
| Title | An SMT-Solver-based Synthesis of NNA-Compliant Quantum Circuits Consisting of CNOT, H and T Gates |
| Author | *Kyohei Seino, Shigeru Yamashita (Ritsumeikan Univ., Japan) |
| Page | pp. 196 - 201 |
| Detailed information (abstract, keywords, etc) | |
| Title | Compilation of Entangling Gates for High-Dimensional Quantum Systems |
| Author | *Kevin Mato (Tech. Univ. of Munich, Germany), Martin Ringbauer (Univ. of Innsbruck, Austria), Stefan Hillmich (Johannes Kepler Univ. Linz, Austria), Robert Wille (Technical Univ. of Munich/Competence Center Hagenberg (SCCH) GmbH, Germany) |
| Page | pp. 202 - 208 |
| Detailed information (abstract, keywords, etc) | |
| Title | WIT-Greedy: Hardware System Design of Weighted ITerative Greedy Decoder for Surface Code |
| Author | *Wang Liao (Univ. of Tokyo, Japan), Yasunari Suzuki (NTT, Japan), Teruo Tanimoto (Kyushu Univ., Japan), Yosuke Ueno (Univ. of Tokyo, Japan), Yuuki Tokunaga (NTT, Japan) |
| Page | pp. 209 - 215 |
| Detailed information (abstract, keywords, etc) | |
| Title | Quantum Data Compression for Efficient Generation of Control Pulses |
| Author | Daniel Volya, *Prabhat Mishra (Univ. of Florida, USA) |
| Page | pp. 216 - 221 |
| Detailed information (abstract, keywords, etc) | |
| Title | Toward Energy-Efficient Sparse Matrix-Vector Multiplication with Near STT-MRAM Computing Architecture |
| Author | *Yueting Li, He Zhang, Xueyan Wang (Beihang Univ., China), Hao Cai (Southeast Univ., China), Yundong Zhang (Vimicro, China), Shuqin Lv, Renguang Liu (TMC, China), Weisheng Zhao (Beihang Univ., China) |
| Page | pp. 222 - 227 |
| Detailed information (abstract, keywords, etc) | |
| Title | RIMAC: An Array-level ADC/DAC-free ReRAM-based In-Memory DNN Processor with Analog Cache and Computation |
| Author | *Peiyu Chen, Meng Wu, Yufei Ma, Le Ye, Ru Huang (Peking Univ., China) |
| Page | pp. 228 - 233 |
| Detailed information (abstract, keywords, etc) | |
| Title | Crossbar-Aligned & Integer-Only Neural Network Compression for Efficient In-Memory Acceleration |
| Author | *Shuo Huai, Di Liu, Xiangzhong Luo, Hui Chen, Weichen Liu (Nanyang Technological Univ., Singapore), Ravi Subramaniam (HP, USA) |
| Page | pp. 234 - 239 |
| Detailed information (abstract, keywords, etc) | |
| Title | Discovering the In-Memory Kernels of 3D Dot-Product Engines |
| Author | *Muhammad Rashedul Haq Rashed (Univ. of Central Florida, USA), Sumit Kumar Jha (Univ. of Texas, San Antonio, USA), Rickard Ewetz (Univ. of Central Florida, USA) |
| Page | pp. 240 - 245 |
| Detailed information (abstract, keywords, etc) | |
| Title | RVComp: Analog Variation Compensation for RRAM-based In-Memory Computing |
| Author | *Jingyu He, Yucong Huang (Hong Kong Univ. of Science and Tech., Hong Kong), Miguel Lastras (Univ. Autónoma de San Luis Potosí, Mexico), Terry Tao Ye (Southern Univ. of Science and Tech., China), Chi Ying Tsui, Kwang-Ting Cheng (Hong Kong Univ. of Science and Tech., Hong Kong) |
| Page | pp. 246 - 251 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Special Talk) VLSI Mask Optimization: How Learning Can Help |
| Author | Bei Yu (Chinese Univ. of Hong Kong, Hong Kong) |
| Detailed information | |
| Title | (Special Talk) Modeling and Simulation of CMOS Image Sensors in SystemVerilog |
| Author | Jaeha Kim (Seoul National Univ., Republic of Korea) |
| Detailed information | |
| Title | (Special Talk) Transistor Count Optimization |
| Author | Ricardo Reis (UFRGS, Brazil) |
| Detailed information | |
| Title | (Special Talk) EDA for additive printed electronics |
| Author | Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany) |
| Detailed information | |
| Title | (Special Talk) Memory Safety Environment for RISC-V processors |
| Author | Sri Parameswaran (Univ. of New South Wales, Australia) |
| Detailed information (abstract, etc) | |
| Title | Rethink before Releasing your Model: ML Model Extraction Attack in EDA |
| Author | *Chen-Chia Chang, Jingyu Pan (Duke Univ., USA), Zhiyao Xie (Hong Kong Univ. of Science and Tech., Hong Kong), Jiang Hu (Texas A&M Univ., USA), Yiran Chen (Duke Univ., USA) |
| Page | pp. 252 - 257 |
| Detailed information (abstract, keywords, etc) | |
| Title | MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy |
| Author | *Yifan Chen, Jing Mai, Xiaohan Gao, Muhan Zhang, Yibo Lin (Peking Univ., China) |
| Page | pp. 258 - 263 |
| Detailed information (abstract, keywords, etc) | |
| Title | BufFormer: A Generative ML Framework for Scalable Buffering |
| Author | *Rongjian Liang, Siddhartha Nath, Anand Rajaram (NVIDIA, USA), Jiang Hu (Texas A&M Univ., USA), Haoxing Ren (NVIDIA, USA) |
| Page | pp. 264 - 270 |
| Detailed information (abstract, keywords, etc) | |
| Title | Decoupling Capacitor Insertion Minimizing IR-Drop Violations and Routing DRVs |
| Author | Daijoon Hyun (Cheongju Univ., Republic of Korea), *Younggwang Jung, Insu Cho, Youngsoo Shin (KAIST, Republic of Korea) |
| Page | pp. 271 - 276 |
| Detailed information (abstract, keywords, etc) | |
| Title | DPRoute: Deep Learning Framework for Package Routing |
| Author | Yeu-Haw Yeh (National Yang Ming Chiao Tung Univ., Taiwan), Simon Yi-Hung Chen (Mediatek, Taiwan), *Hung-Ming Chen (National Yang Ming Chiao Tung Univ., Taiwan), Deng-Yao Tu, Guan-Qi Fang, Yun-Chih Kuo, Po-Yang Chen (Mediatek, Taiwan) |
| Page | pp. 277 - 282 |
| Detailed information (abstract, keywords, etc) | |
| Wednesday, January 18, 2023 |
| Title | (Keynote Address) Analog Synthesis 3.0: AI/ML to Boost Automated Design and Test of Analog/Mixed-Signal ICs |
| Author | Georges G.E. Gielen (KU Leuven, Belgium) |
| Detailed information (abstract, etc) | |
| Title | High Dimensional Yield Estimation using Shrinkage Deep Features and Maximization of Integral Entropy Reduction |
| Author | *Shuo Yin (Beihang Univ., China), Guohao Dai (Shenzhen Univ., China), Wei W. Xing (Beihang Univ., China) |
| Page | pp. 283 - 289 |
| Detailed information (abstract, keywords, etc) | |
| Title | MIA-aware Detailed Placement and VT Reassignment for Leakage Power Optimization |
| Author | *Hung-Chun Lin, Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan) |
| Page | pp. 290 - 295 |
| Detailed information (abstract, keywords, etc) | |
| Title | SLOGAN: SDC Probability Estimation Using Structured Graph Attention Network |
| Author | *Junchi Ma, Sulei Huang, Zongtao Duan, Lei Tang, Luyang Wang (Chang'an Univ., China) |
| Page | pp. 296 - 301 |
| Detailed information (abstract, keywords, etc) | |
| Title | Microarchitecture Power Modeling via Artificial Neural Network and Transfer Learning |
| Author | Jianwang Zhai, Yici Cai (Tsinghua Univ., China), *Bei Yu (Chinese Univ. of Hong Kong, China) |
| Page | pp. 302 - 307 |
| Detailed information (abstract, keywords, etc) | |
| Title | MUGNoC: A Software-configured Multicast-Unicast-Gather NoC for Accelerating CNN Dataflows |
| Author | *Hui Chen, Di Liu, Shiqing Li, Shuo Huai, Xiangzhong Luo, Weichen Liu (Nanyang Technological Univ., Singapore) |
| Page | pp. 308 - 313 |
| Detailed information (abstract, keywords, etc) | |
| Title | COLAB: Collaborative and Efficient Processing of Replicated Cache Requests in GPU |
| Author | *Bo-Wun Cheng, En-Ming Huang, Chen-Hao Chao, Wei-Fang Sun (National Tsing Hua Univ., Taiwan), Tsung-Tai Yeh (National Yang Ming Chiao Tung Univ., Taiwan), Chun-Yi Lee (National Tsing Hua Univ., Taiwan) |
| Page | pp. 314 - 319 |
| Detailed information (abstract, keywords, etc) | |
| Title | Mixed-Criticality with Integer Multiple WCETs and Dropping Relations: New Scheduling Challenges |
| Author | *Federico Reghenzani, William Fornaciari (Politecnico di Milano, Italy) |
| Page | pp. 320 - 325 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Exact Schedulability Analysis for Global Fixed-Priority Scheduling of the AER Task Model |
| Author | *Thilanka Thilakasiri, Matthias Becker (Royal Inst. of Tech., Sweden) |
| Page | pp. 326 - 332 |
| Detailed information (abstract, keywords, etc) | |
| Title | Skyrmion Vault: Maximizing Skyrmion Lifespan for Enabling Low-Power Skyrmion Racetrack Memory |
| Author | Syue-Wei Lu (National Tsing Hua Univ., Taiwan), *Shuo-Han Chen (National Taipei Univ. of Tech., Taiwan), Yu-Pei Liang (National Chung Cheng Univ., Taiwan), Yuan-Hao Chang (Academia Sinica, Taiwan), Kang Wang (Beihang Univ., China), Tseng-Yi Chen (National Central Univ., Taiwan), Wei-Kuan Shih (National Tsing Hua Univ., Taiwan) |
| Page | pp. 333 - 338 |
| Detailed information (abstract, keywords, etc) | |
| Title | Parallel Incomplete LU Factorization Based Iterative Solver for Fixed-Structure Linear Equations in Circuit Simulation |
| Author | *Lingjie Li, Zhiqiang Liu, Kan Liu, Shan Shen, Wenjian Yu (Tsinghua Univ., China) |
| Page | pp. 339 - 345 |
| Detailed information (abstract, keywords, etc) | |
| Title | Accelerated Capacitance Simulation of 3-D Structures With Considerable Amounts of General Floating Metals |
| Author | *Jiechen Huang, Wenjian Yu, Mingye Song, Ming Yang (Tsinghua Univ., China) |
| Page | pp. 346 - 351 |
| Detailed information (abstract, keywords, etc) | |
| Title | On Automating Finger-Cap Array Synthesis with Optimal Parasitic Matching for Custom SAR ADC |
| Author | *Cheng-Yu Chiang, Chia-Lin Hu, Mark Po-Hung Lin, Yu-Szu Chung, Shyh-Jye Jou, Jieh-Tsorng Wu (National Yang Ming Chiao Tung Univ., Taiwan), Shiuh-hua Wood Chiang (Brigham Young Univ., Taiwan), Chien-Nan Jimmy Liu, Hung-Ming Chen (National Yang Ming Chiao Tung Univ., Taiwan) |
| Page | pp. 352 - 357 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) Remote Power Attacks on ML Accelerators in Multi-Tenant FPGAs |
| Author | Jakub Szefer (Yale Univ., USA) |
| Detailed information (abstract, etc) | |
| Title | (Invited Paper) FPGANeedle: Precise Remote Fault Attacks from FPGA to CPU |
| Author | *Mathieu Gross (Tech. Univ. of Munich, Germany), Jonas Krautter, Dennis Gnad (Karlsruhe Inst. of Tech., Germany), Michael Gruber, Georg Sigl (Tech. Univ. of Munich, Germany), Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany) |
| Page | pp. 358 - 364 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) FPGA Based Countermeasures against Side channel Attacks on Block Ciphers |
| Author | Darshana Jayasinghe, Brian Udugama, *Sri Parameswaran (Univ. of New South Wales, Australia) |
| Page | pp. 365 - 371 |
| Detailed information (abstract, keywords, etc) | |
| Title | Block-Wise Dynamic-Precision Neural Network Training Acceleration via Online Quantization Sensitivity Analytics |
| Author | *Ruoyang Liu, Chenhan Wei, Yixiong Yang, Wenxun Wang, Huazhong Yang, Yongpan Liu (Tsinghua Univ., China) |
| Page | pp. 372 - 377 |
| Detailed information (abstract, keywords, etc) | |
| Title | Quantization Through Search: A Novel Scheme to Quantize Convolutional Neural Networks in Finite Weight Space |
| Author | *Qing Lu (Univ. of Notre Dame, USA), Weiwen Jiang (George Mason Univ., USA), Xiaowei Xu (Guangdong Provincial People's Hospital, USA), Jingtong Hu (Univ. of Pittsburgh, USA), Yiyu Shi (Univ. of Notre Dame, USA) |
| Page | pp. 378 - 383 |
| Detailed information (abstract, keywords, etc) | |
| Title | Multi-Wavelength Parallel Training and Quantization-Aware Tuning for WDM-Based Optical Convolutional Neural Networks Considering Wavelength-Relative Deviations |
| Author | *Ying Zhu (State Key Laboratory of Optical Communication Technologies and Networks, China Information Communication Technologies Group (CICT), China), Min Liu, Lu Xu, Lei Wang (National Information Optoelectronics Innovation Center and China Information Communication Technologies Group (CICT), China), Xi Xiao, Shaohua Yu (State Key Laboratory of Optical Communication Technologies and Networks, China Information Communication Technologies Group (CICT), China) |
| Page | pp. 384 - 389 |
| Detailed information (abstract, keywords, etc) | |
| Title | Semantic Guided Fine-grained Point Cloud Quantization Framework for 3D Object Detection |
| Author | *Xiaoyu Feng, Chen Tang, Zongkai Zhang, Wenyu Sun, Yongpan Liu (Tsinghua Univ., China) |
| Page | pp. 390 - 395 |
| Detailed information (abstract, keywords, etc) | |
| Title | ReMeCo: Reliable Memristor-Based In-Memory Neuromorphic Computation |
| Author | *Ali BanaGozar (Eindhoven Univ. of Tech., Netherlands), Seyed Hossein Hashemi Shadmehri (Univ. of Tehran, Iran), Sander Stuijk (Eindhoven Univ. of Tech., Netherlands), Mehdi Kamal (Univ. of Southern California, USA), Ali Afzali-Kusha (Univ. of Tehran, Iran), Henk Corporaal (Eindhoven Univ. of Tech., Netherlands) |
| Page | pp. 396 - 401 |
| Detailed information (abstract, keywords, etc) | |
| Title | SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators with Generative Networks |
| Author | Rohit Ranjan, *Salim Ullah, Siva Satyendra Sahoo, Akash Kumar (TU Dresden, Germany) |
| Page | pp. 402 - 409 |
| Detailed information (abstract, keywords, etc) | |
| Title | Approximating HW Accelerators through Partial Extractions onto Shared Artificial Neural Networks |
| Author | Prattay Chowdhury (Univ. of Texas, Dallas, USA), Jorge Castro Godínez (Costa Rica Inst. of Tech., Costa Rica), *Benjamin Carrion Schaefer (Univ. of Texas, Dallas, USA) |
| Page | pp. 410 - 415 |
| Detailed information (abstract, keywords, etc) | |
| Title | DependableHD: A Hyperdimensional Learning Framework for Edge-oriented Voltage-scaled Circuits |
| Author | *Dehua Liang (Osaka Univ., Japan), Hiromitsu Awano (Kyoto Univ., Japan), Noriyuki Miura, Jun Shiomi (Osaka Univ., Japan) |
| Page | pp. 416 - 422 |
| Detailed information (abstract, keywords, etc) | |
| Title | EDDY: A Multi-Core BDD Package With Dynamic Memory Management and Reduced Fragmentation |
| Author | *Rune Krauss, Mehran Goli, Rolf Drechsler (Univ. of Bremen, Germany) |
| Page | pp. 423 - 428 |
| Detailed information (abstract, keywords, etc) | |
| Title | Exploiting Reversible Computing for Verification: Potential, Possible Paths, and Consequences |
| Author | Lukas Burgholzer (Johannes Kepler Univ. Linz, Austria), *Robert Wille (Tech. Univ. of Munich, Germany) |
| Page | pp. 429 - 435 |
| Detailed information (abstract, keywords, etc) | |
| Title | Automatic Test Pattern Generation and Compaction for Deep Neural Networks |
| Author | *Dina A. Moussa, Michael Hefenbrock, Christopher Münch, Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany) |
| Page | pp. 436 - 441 |
| Detailed information (abstract, keywords, etc) | |
| Title | Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects |
| Author | *Takuma Nagao (NAIST, Japan), Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki (Sony Semiconductor Manufacturing, Japan), Michiko Inoue (NAIST, Japan), Michihiro Shintani (Kyoto Inst. of Tech., Japan) |
| Page | pp. 442 - 448 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Designers' Forum) DF Keynote: The Impact of AI in Intelligent System Design |
| Author | Simon Chang (Cadence) |
| Detailed information (abstract, etc) | |
| Title | (Designers' Forum) General-Purpose Scalar/Vector Processor for Accelerating Wide Range of Tasks Including Automotive and Industrial Applications |
| Author | Masayuki Ito (NSITEXE, Japan) |
| Detailed information (abstract, etc) | |
| Title | (Designers' Forum) 16x16 Photonic Analog Vector Matrix Multipliers Based on Silicon Photonics |
| Author | Shota Kita (NTT, Japan) |
| Detailed information (abstract, etc) | |
| Title | (Designers' Forum) Research Activities toward Larger-Scale Cryogenic Quantum Computer Systems |
| Author | Teruo Tanimoto (Kyushu Univ., Japan) |
| Detailed information (abstract, etc) | |
| Title | (Designers' Forum) Cryogenic Bias Voltage Control Circuits for Large Scale Qubit Arrays |
| Author | Takuji Miki (Kobe Univ., Japan) |
| Detailed information (abstract, etc) | |
| Title | (Invited Paper) Hardware Security Primitives using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs |
| Author | Simranjeet Singh (Indian Inst. of Tech. Bombay, India), *Furqan Zahoor, Gokulnath Rajendran (Nanyang Technological Univ., Singapore), Sachin Patkar (Indian Inst. of Tech. Bombay, India), Anupam Chattopadhyay (Nanyang Technological Univ., Singapore), Farhad Merchant (RWTH Aachen Univ., Germany) |
| Page | pp. 449 - 454 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) Data Sanitization on eMMCs |
| Author | *Aya Fukami (Univ. of Amsterdam and Netherlands Forensic Institute, Netherlands), Francesco Regazzoni (Univ. of Amsterdam and Univ. della Svizzera italiana, Netherlands), Zeno Geradts (Univ. of Amsterdam and Netherlands Forensic Institute, Netherlands) |
| Page | pp. 455 - 460 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) Fundamentally Understanding and Solving RowHammer |
| Author | *Onur Mutlu, Ataberk Olgun, Abdullah Giray Yağlıkcı (ETH Zürich, Switzerland) |
| Page | pp. 461 - 468 |
| Detailed information (abstract, keywords, etc) | |
| Title | Hardware-Software Codesign of DNN Accelerators using Approximate Posit Multipliers |
| Author | Tom Glint, *Kailash Prasad, Jinay Dagli (IIT Gandhinagar, India), Krishil Gandhi (SVNIT, India), Aryan Gupta, Vrajesh Patel, Neel Shah, Joycee Mekie (IIT Gandhinagar, India) |
| Page | pp. 469 - 474 |
| Detailed information (abstract, keywords, etc) | |
| Title | Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-based DNN Accelerators |
| Author | *Susmita Dey Manasi (Univ. of Minnesota Twin Cities, USA), Suvadeep Banerjee, Abhijit Davare, Anton A. Sorokin, Steven M. Burns, Desmond A. Kirkpatrick (Intel, USA), Sachin S. Sapatnekar (Univ. of Minnesota Twin Cities, USA) |
| Page | pp. 475 - 482 |
| Detailed information (abstract, keywords, etc) | |
| Title | BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU |
| Author | *MohammadHossein AskariHemmat (Ecole Polytechnique Montreal, Canada), Sean Wagner (IBM, Canada), Olexa Bilaniuk (MILA, Canada), Yassine Hariri (CMC, Canada), Yvon Savaria, Jean-Pierre David (Ecole Polytechnique Montreal, Canada) |
| Page | pp. 483 - 489 |
| Detailed information (abstract, keywords, etc) | |
| Title | Agile Hardware and Software Co-design for RISC-V-based Multi-precision Deep Learning Microprocessor |
| Author | Zicheng He (UCLA/Southern Univ. of Science and Tech., USA), Ao Shen, *Qiufeng Li (Southern Univ. of Science and Tech., China), Quan Cheng (Kyoto Univ., Japan), Hao Yu (Southern Univ. of Science and Tech., China) |
| Page | pp. 490 - 495 |
| Detailed information (abstract, keywords, etc) | |
| Title | Hardware Trojan Detection Using Shapley Ensemble Boosting |
| Author | Zhixin Pan, *Prabhat Mishra (Univ. of Florida, USA) |
| Page | pp. 496 - 503 |
| Detailed information (abstract, keywords, etc) | |
| Title | ASSURER: A PPA-friendly Security Closure Framework for Physical Design |
| Author | *Guangxin Guo, Hailong You, ZhengGuang Tang, Benzheng Li, Cong Li (Xidian Univ., China), Xiaojue Zhang (GIGA Design Automation, China) |
| Page | pp. 504 - 509 |
| Detailed information (abstract, keywords, etc) | |
| Title | Static Probability Analysis Guided RTL Hardware Trojan Test Generation |
| Author | *Haoyi Wang, Qiang Zhou, Yici Cai (Tsinghua Univ., China) |
| Page | pp. 510 - 515 |
| Detailed information (abstract, keywords, etc) | |
| Title | Hardware Trojan Detection and High-Precision Localization in NoC-based MPSoC using Machine Learning |
| Author | *Haoyu Wang, Basel Halak (Univ. of Southampton, UK) |
| Page | pp. 516 - 521 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Integrated Circuit Partitioning and TDM Assignment Optimization Framework for Multi-FPGA Systems |
| Author | *Dan Zheng, Evangeline F. Y. Young (Chinese Univ. of Hong Kong, Hong Kong) |
| Page | pp. 522 - 528 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Robust FPGA Router with Concurrent Intra-CLB Rerouting |
| Author | *Jiarui Wang, Jing Mai (Peking Univ., China), Zhixiong Di (Southwest Jiaotong Univ., China), Yibo Lin (Peking Univ./Beijing Advanced Innovation Center for Integrated Circuits, China) |
| Page | pp. 529 - 534 |
| Detailed information (abstract, keywords, etc) | |
| Title | Efficient Global Optimization for Large Scaled Ordered Escape Routing |
| Author | Chuandong Chen, *Dishi Lin, Rongshan Wei, Qinghai Liu (Fuzhou Univ., China), Ziran Zhu (Southeast Univ., China), Jianli Chen (Fudan Univ., China) |
| Page | pp. 535 - 540 |
| Detailed information (abstract, keywords, etc) | |
| Title | An Adaptive Partition Strategy of Galerkin Boundary Element Method for Capacitance Extraction |
| Author | *Shengkun Wu (Peng Cheng Laboratory, China), Biwei Xie (Chinese Academy of Sciences, China), Xingquan Li (Minnan Normal Univ., China) |
| Page | pp. 541 - 546 |
| Detailed information (abstract, keywords, etc) | |
| Title | Graph-Learning-Driven Path-Based Timing Analysis Results Predictor from Graph-Based Timing Analysis |
| Author | *Yuyang Ye (Southeast Univ., China), Tinghuan Chen (Chinese Univ. of Hong Kong, Hong Kong), Yifei Gao, Hao Yan (Southeast Univ., China), Bei Yu (Chinese Univ. of Hong Kong, Hong Kong), Longxing Shi (Southeast Univ., China) |
| Page | pp. 547 - 552 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Designers' Forum) Advanced Technologies of an Organic-Photoconductive-Film CMOS Image Sensor |
| Author | Naoki Shimasaki (Panasonic Holdings, Japan) |
| Detailed information (abstract, etc) | |
| Title | (Designers' Forum) A 0.37W 143dB-Dynamic-Range 1Mpixel Backside-Illuminated Charge-Focusing SPAD Image Sensor with Pixel-Wise Exposure Control and Adaptive Clocked Recharging |
| Author | Yasuharu Ota, K. Morimoto (Canon, Japan) |
| Detailed information (abstract, etc) | |
| Title | (Designers' Forum) A 1200x84-pixels 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation |
| Author | Tuan Thanh Ta (Toshiba R&D Center, Japan) |
| Detailed information (abstract, etc) | |
| Thursday, January 19, 2023 |
| Title | (Keynote Address) Innovation by Design and Technology Co-Optimization |
| Author | Takuya Yasui (TSMC Japan Design Center, Japan) |
| Detailed information (abstract, etc) | |
| Title | (Invited Paper) Beyond von Neumann Era: Brain-inspired Hyperdimensional Computing to the Rescue |
| Author | *Hussam Amrouch, Paul R. Genssler (Univ. of Stuttgart, Germany), Mohsen Imani, Mariam Issa (UC Irvine, USA), Xun Jiao (Villanova Univ., USA), Wegdan Mohammed, Glorian Sepanta (Univ. of Stuttgart, Germany), Ruixuan Wang (Villanova Univ., USA) |
| Page | pp. 553 - 560 |
| Detailed information (abstract, keywords, etc) | |
| Title | System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms |
| Author | *Rafael Medina, Joshua Klein, Giovanni Ansaloni (École Polytechnique Fédérale de Lausanne, Switzerland), Marina Zapater (Haute École Spécialisée de Suisse Occidentale, Switzerland), Sergi Abadal, Eduard Alarcón (Univ. Politčcnica de Catalunya, Spain), David Atienza (École Polytechnique Fédérale de Lausanne, Switzerland) |
| Page | pp. 561 - 566 |
| Detailed information (abstract, keywords, etc) | |
| Title | Efficient System-Level Design Space Exploration for High-Level Synthesis using Pareto-Optimal Subspace Pruning |
| Author | Yuchao Liao, *Tosiron Adegbija, Roman Lysecky (Univ. of Arizona, USA) |
| Page | pp. 567 - 572 |
| Detailed information (abstract, keywords, etc) | |
| Title | Automatic Generation of Complete Polynomial Interpolation Design Space for Hardware Architectures |
| Author | Bryce Orloski (Intel, USA), *Samuel Coward (Intel, UK), Theo Drane (Intel, USA) |
| Page | pp. 573 - 578 |
| Detailed information (abstract, keywords, etc) | |
| Title | SHarPen: SoC Security Verification by Hardware Penetration Test |
| Author | Hasan Al-Shaikh, Arash Vafaei, Mridha Md Mashahedur Rahman, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, *Mark Tehranipoor (Univ. of Florida, USA) |
| Page | pp. 579 - 584 |
| Detailed information (abstract, keywords, etc) | |
| Title | SecHLS: Enabling Security Awareness in High-Level Synthesis |
| Author | Shang Shi, Nitin Pundir, Hadi Mardani Kamali, Mark Tehranipoor, *Farimah Farahmandi (Univ. of Florida, USA) |
| Page | pp. 585 - 590 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Flexible ASIC-oriented Design for a Full NTRU Accelerator |
| Author | *Francesco Antognazza, Alessandro Barenghi, Gerardo Pelosi (Politecnico di Milano, Italy), Ruggero Susella (STMicroelectronics, Italy) |
| Page | pp. 591 - 597 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) Robust Hyperdimensional Computing Against Cyber Attacks and Hardware Errors: A Survey |
| Author | Dongning Ma, Sizhe Zhang, *Xun Jiao (Villanova Univ., USA) |
| Page | pp. 598 - 605 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) In-Memory Computing Accelerators for Emerging Learning Paradigms |
| Author | *Dayane Reis (Univ. of South Florida, USA), Ann Franchesca Laguna (De La Salle Univ., Philippines), Michael Niemier, Xiaobo S. Hu (Univ. of Notre Dame, USA) |
| Page | pp. 606 - 611 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) Toward Fair and Efficient Hyperdimensional Computing |
| Author | *Yi Sheng, Junhuan Yang, Weiwen Jiang, Lei Yang (George Mason Univ., USA) |
| Page | pp. 612 - 617 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) Improving the Robustness and Efficiency of PIM-based Architecture by SW/HW Co-design |
| Author | Xiaoxuan Yang, Shiyu Li, Qilin Zheng, *Yiran Chen (Duke Univ., USA) |
| Page | pp. 618 - 623 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) Hardware-Software Co-Design for On-Chip Learning in AI Systems |
| Author | L. M. Varshika, Abhishek Kumar Mishra, Nagarajan Kandasamy, *Anup Das (Drexel Univ., USA) |
| Page | pp. 624 - 631 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) Towards On-Chip Learning for Low Latency Reasoning with End-to-End Synthesis |
| Author | *Vito Giovanni Castellana (Pacific Northwest National Laboratory, USA), Nicolas Bohm Agostini (Northeastern Univ. and Pacific Northwest National Laboratory, USA), Ankur Limaye (Pacific Northwest National Laboratory, USA), Serena Curzel, Michele Fiorito (Politecnico di Milano, Italy), Vinay Amatya, Marco Minutoli, Joseph Manzano (Pacific Northwest National Laboratory, USA), Fabrizio Ferrandi (Politecnico di Milano, Italy), Antonino Tumeo (Pacific Northwest National Laboratory, USA) |
| Page | pp. 632 - 638 |
| Detailed information (abstract, keywords, etc) | |
| Title | Knowledge Distillation in Quantum Neural Network using Approximate Synthesis |
| Author | Mahabubul Alam, Satwik Kundu, *Swaroop Ghosh (Pennsylvania State Univ., USA) |
| Page | pp. 639 - 644 |
| Detailed information (abstract, keywords, etc) | |
| Title | NTGAT: A Graph Attention Network Accelerator with Runtime Node Tailoring |
| Author | Wentao Hou, *Kai Zhong, Shulin Zeng, Guohao Dai, HuaZhong Yang, Yu Wang (Tsinghua Univ., China) |
| Page | pp. 645 - 650 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Low-Bitwidth Integer-STBP Algorithm for Efficient Training and Inference of Spiking Neural Networks |
| Author | *Pai-Yu Tan, Cheng-Wen Wu (National Tsing Hua Univ., Taiwan) |
| Page | pp. 651 - 656 |
| Detailed information (abstract, keywords, etc) | |
| Title | TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers |
| Author | *Alireza Amirshahi, Joshua Alexander Harrison Klein, Giovanni Ansaloni, David Atienza (EPFL, Switzerland) |
| Page | pp. 657 - 663 |
| Detailed information (abstract, keywords, etc) | |
| Title | PMU-Leaker: Performance Monitor Unit-based Realization of Cache Side-Channel Attacks |
| Author | Pengfei Qiu, Qiang Gao (Key Laboratory of Trustworthy Distributed Computing and Service (BUPT), Ministry of Education/Tsinghua Univ., China), Dongsheng Wang, Yongqiang Lyu (Tsinghua Univ., China), Chunlu Wang (Key Laboratory of Trustworthy Distributed Computing and Service (BUPT), Ministry of Education, China), Chang Liu (Tsinghua Univ., China), Rihui Sun (Harbin Inst. of Tech., China), *Gang Qu (Univ. of Maryland, College Park, USA) |
| Page | pp. 664 - 669 |
| Detailed information (abstract, keywords, etc) | |
| Title | EO-Shield: A Multi-function Protection Scheme against Side Channel and Focused Ion Beam Attacks |
| Author | *Ya Gao, Qizhi Zhang, Haocheng Ma, Jiaji He, Yiqiang Zhao (Tianjin Univ., China) |
| Page | pp. 670 - 675 |
| Detailed information (abstract, keywords, etc) | |
| Title | CompaSeC: A Compiler-assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V |
| Author | *Johannes Geier (Tech. Univ. of Munich, Germany), Lukas Auer (Fraunhofer Institute for Applied and Integrated Security (AISEC), Germany), Daniel Müller-Gritschneder, Uzair Sharif, Ulf Schlichtmann (Tech. Univ. of Munich, Germany) |
| Page | pp. 676 - 682 |
| Detailed information (abstract, keywords, etc) | |
| Title | Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - a RISC-V Case Study |
| Author | *Sajjad Parvin (Univ. of Bremen, Germany), Mehran Goli (Univ. of Bremen/German Research Centre for Artificial Intelligence, Germany), Frank Sill Torres (German Aerospace Center (DLR), Germany), Rolf Drechsler (Univ. of Bremen/German Research Centre for Artificial Intelligence, Germany) |
| Page | pp. 683 - 689 |
| Detailed information (abstract, keywords, etc) | |
| Title | Graph Partitioning Approach for Fast Quantum Circuit Simulation |
| Author | *Jaekyung Im, Seokhyeong Kang (POSTECH, Republic of Korea) |
| Page | pp. 690 - 695 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Robust Approach to Detecting Non-equivalent Quantum Circuits Using Specially Designed Stimuli |
| Author | Hsiao-Lun Liu, *Yi-Ting Li (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (National Taiwan Univ. of Science and Tech., Taiwan), Chun-Yao Wang (National Tsing Hua Univ., Taiwan) |
| Page | pp. 696 - 701 |
| Detailed information (abstract, keywords, etc) | |
| Title | Equivalence Checking of Parameterized Quantum Circuits: Verifying the Compilation of Variational Quantum Algorithms |
| Author | *Tom Peham (Tech. Univ. of Munich, Germany), Lukas Burgholzer (Johannes Kepler Univ. Linz, Austria), Robert Wille (Tech. Univ. of Munich, Germany) |
| Page | pp. 702 - 708 |
| Detailed information (abstract, keywords, etc) | |
| Title | Software Tools for Decoding Quantum Low-Density Parity Check Codes |
| Author | *Lucas Berent (Tech. Univ. of Munich, Germany), Lukas Burgholzer (Johannes Kepler Univ. Linz, Austria), Robert Wille (Tech. Univ. of Munich, Germany) |
| Page | pp. 709 - 714 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Designers' Forum) Neuromorphic Computing Expanding AI Coverage at the Edge with Ultra-Low Energy Consumption |
| Author | Kazuhisa Fujimoto (Hitachi, Japan) |
| Detailed information (abstract, etc) | |
| Title | (Designers' Forum) HERO: Hessian-Enhanced Robust Optimization for Unifying and Improving Generalization and Quantization Performance |
| Author | Huanrui Yang (Univ. of California, Berkeley, USA) |
| Detailed information (abstract, etc) | |
| Title | (Designers' Forum) Object-Based Fusion System in ADAS |
| Author | Yan Zheng (Huayu Automotive Systems, China) |
| Detailed information (abstract, etc) | |
| Title | (Designers' Forum) Millimeter-Wave Radar: A New Approach for Privacy Protection Human Sensing |
| Author | Jun Tian (Fujitsu R&D Center, China) |
| Detailed information (abstract, etc) | |
| Title | (Invited Paper) Enabling Scalable AI Computational Lithography with Physics-Inspired Models |
| Author | *Haoyu Yang, Haoxing Ren (NVIDIA, USA) |
| Page | pp. 715 - 720 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) Canceled |
| Detailed information | |
| Title | (Invited Paper) Data-Driven Approaches for Process Simulation and Optical Proximity Correction |
| Author | Hao-Chiang Shao (National Chung Hsing Univ., Taiwan), Chia-Wen Lin (National Tsing Hua Univ., Taiwan), *Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan) |
| Page | pp. 721 - 726 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Invited Paper) Mixed-Type Wafer Failure Pattern Recognition |
| Author | *Hao Geng (ShanghaiTech Univ., China), Qi Sun, Tinghuan Chen (Chinese Univ. of Hong Kong, Hong Kong), Qi Xu (USTC, China), Tsung-Yi Ho, Bei Yu (Chinese Univ. of Hong Kong, Hong Kong) |
| Page | pp. 727 - 732 |
| Detailed information (abstract, keywords, etc) | |
| Title | Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-sharing Approach |
| Author | *Bosheng Liu, Hongyi Liang, Jigang Wu (Guangdong Univ. of Tech., China), Xiaoming Chen (Chinese Academy of Sciences, China), Peng Liu (Guangdong Univ. of Tech., China), Yinhe Han (Chinese Academy of Sciences, China) |
| Page | pp. 733 - 738 |
| Detailed information (abstract, keywords, etc) | |
| Title | Mortar: Morphing the Bit Level Sparsity for General Purpose Deep Learning Acceleration |
| Author | Yunhung Gao (Peking Univ., China), Hongyan Li (Univ. of Chinese Academy of Sciences, China), Kevin Zhang (Peking Univ., China), Xueru Yu (Shanghai Integrated Circuits R&D Center, China), *Hang Lu (Univ. of Chinese Academy of Sciences, China) |
| Page | pp. 739 - 744 |
| Detailed information (abstract, keywords, etc) | |
| Title | Data-Model-Circuit Tri-design for Ultra-light Video Intelligence on Edge Devices |
| Author | Yimeng Zhang (Michigan State Univ., USA), *Akshay Karkal Kamath (Georgia Tech, USA), Qiucheng Wu (Univ. of California, Santa Barbara, USA), Zhiwen Fan, Wuyang Chen, Zhangyang Wang (Univ. of Texas, Austin, USA), Shiyu Chang (Univ. of California, Santa Barbara, USA), Sijia Liu (Michigan State Univ., USA), Cong Hao (Georgia Tech, USA) |
| Page | pp. 745 - 750 |
| Detailed information (abstract, keywords, etc) | |
| Title | Latent Weight-based Pruning for Small Binary Neural Networks |
| Author | *Tianen Chen (Univ. of Wisconsin-Madison, USA), Noah Anderson (Stanford Univ., USA), Younghyun Kim (Univ. of Wisconsin-Madison, USA) |
| Page | pp. 751 - 756 |
| Detailed information (abstract, keywords, etc) | |
| Title | AutoFlex: Unified Evaluation and Design Framework for Flexible Hybrid Electronics |
| Author | *Tianliang Ma, Zhihui Deng, Leilai Shao (Shanghai Jiaotong Univ., China) |
| Page | pp. 757 - 762 |
| Detailed information (abstract, keywords, etc) | |
| Title | CNFET7: An Open Source Cell Library for 7-nm CNFET Technology |
| Author | *Chenlin Shi, Shinobu Miwa (Univ. of Electro-Communications, Japan), Tongxin Yang, Ryota Shioya (Univ. of Tokyo, Japan), Hayato Yamaki, Hiroki Honda (Univ. of Electro-Communications, Japan) |
| Page | pp. 763 - 768 |
| Detailed information (abstract, keywords, etc) | |
| Title | A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits |
| Author | *Rongliang Fu (Chinese Univ. of Hong Kong, Hong Kong), Mengmeng Wang (Yokohama National Univ., Japan), Yirong Kan (NAIST, Japan), Nobuyuki Yoshikawa (Yokohama National Univ., Japan), Tsung-Yi Ho (Chinese Univ. of Hong Kong, Hong Kong), Olivia Chen (Tokyo City Univ., Japan) |
| Page | pp. 769 - 774 |
| Detailed information (abstract, keywords, etc) | |
| Title | FLOW-3D: Flow-Based Computing on 3D Nanoscale Crossbars with Minimal Semiperimeter |
| Author | *Sven Thijssen (Univ. of Central Florida, USA), Sumit Kumar Jha (Univ. of Texas, San Antonio, USA), Rickard Ewetz (Univ. of Central Florida, USA) |
| Page | pp. 775 - 780 |
| Detailed information (abstract, keywords, etc) | |
| Title | (Panel Discussion) Aiming Direction of DX System Design from Hardware to Application |
| Author | Panelists: Masayuki Ito (NSITEXE, Japan), Teruo Tanimoto (Kyushu Univ., Japan), Takuji Miki (Kobe Univ., Japan), Naoki Shimasaki (Panasonic Holdings, Japan), Yasuharu Ota (Canon, Japan), Tuan Thanh Ta (Toshiba R&D Center, Japan), Kazuhisa Fujimoto (Hitachi, Japan), Huanrui Yang (Univ. of California, Berkeley, USA), Yan Zheng (Huayu Automotive Systems, China), Jun Tian (Fujitsu R&D Center, China) |
| Detailed information (abstract, etc) | |