The 23rd Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Tuesday, January 23, 2018

Room 302	Room 401	Room 402A	Room 402B
1K (Halla HALL) Opening & Keynote I 9:00 - 10:30
Coffee Break 10:30 - 11:00
1A (SS-1) Deep Learning for Applications that Live on Big Data 11:00 - 12:15	1B System Level Management and Optimization 11:00 - 12:15	1C Advances in Bio-Chip and Bio-Data-Processing 11:00 - 12:15	1D Resource-Constrained Scheduling 11:00 - 12:15
Lunch Break 12:15 - 13:45
2A (SS-2) New Advances in Hardware Security 13:45 - 15:25	2B Energy-Efficient CNN Accelerators 13:45 - 15:25	2C Networks on Chips and Beyond 13:45 - 15:25	2D Timing Exploration: Modeling, Analysis and Optimization 13:45 - 15:25
Coffee Break 15:25 - 15:55
3A Machine Learning Architecture Design and Its Applications 15:55 - 17:35	3B Advanced Memory Architecture 15:55 - 17:35	3C Advanced Testing and Diagnosis Techniques 15:55 - 17:35	3D Split Manufacturing, Logic Obfuscation and Camouflaging 15:55 - 17:35
Break 17:35 - 18:00
ACM SIGDA Student Research Forum (Samda Hall) 18:00 - 20:00

Wednesday, January 24, 2018

Room 302	Room 401	Room 402A	Room 402B
2K (Halla HALL) Keynote II 9:00 - 10:00
Coffee Break 10:00 - 10:30
4A University Design Contest 10:30 - 12:10	4B System Architectures 10:30 - 12:10	4C Emerging Technologies for Energy Efficient Computing 10:30 - 12:10	4D Design for Manufacturability and Reliability 10:30 - 12:10
Lunch Break / UDC Posters 12:10 - 13:40
5A (IS) Machine/Deep Learning for Semiconductor Design, EDA Technologies, and Application 13:40 - 15:45	5B System Design Methodologies 13:40 - 15:45	5C Synthesis, Routing and Timing 13:40 - 15:45	5D Advanced Placement and Routing Techniques 13:40 - 15:45
Coffee Break 15:45 - 16:15
6A (SS-3) Training Deep Neural Networks: Algorithms and Architectures 16:15 - 17:30	6B Emerging Memory Management Techniques 16:15 - 17:30	6C Intelligent System Designs with Neuromorphic and Stochastic Technologies 16:15 - 17:30	6D New Flavors of Logic and Arithmetic Synthesis 16:15 - 17:30
Break 17:30 - 18:00
Banquet (Tamna Hall, ICC 5F) 18:00 - 20:00

Thursday, January 25, 2018

Room 302	Room 401	Room 402A	Room 402B
3K (Halla HALL) Keynote III 8:30 - 10:00
Coffee Break 10:00 - 10:30
7A Multiplier Design: From Accurate to Approximate 10:30 - 11:45	7B (SS-4) Reliability and Aging-Aware Designs for sub-10nm ICs 10:30 - 11:45	7C (SS-5) Design Automation and Methodology for Flexible Electronics 10:30 - 11:45	7D Novel Synthesis Techniques for Quantum Circuits 10:30 - 11:45
Lunch Break 11:45 - 13:15
8A Energy Efficient System Design 13:15 - 14:30	Embedded Workshop I (EDA Winter Workshop)	Embedded Workshop II (Workshop on Memory and Storage Devices and Systems)
Coffee Break 14:30 - 15:00
9A Hardware Security Primitive Design and Implementation 15:00 - 16:15
Coffee Break 16:15 - 16:45
10A Deep Learning and Architectural Security 16:45 - 18:00

IS: Industry Session, SS: Special Session

List of papers

Remark: The presenter of each paper is marked with "*".

Tuesday, January 23, 2018

Session 1K Opening & Keynote I
Time: 9:00 - 10:30 Tuesday, January 23, 2018
Location: Halla HALL
Chair: Youngsoo Shin (KAIST, Republic of Korea)

1K-1 (Time: 9:30 - 10:30)

Title	(Keynote Address) Designing Heterogeneous Systems in the AI Era: Challenges and Opportunities
Author	Jeff Burns (IBM, U.S.A.)
Detailed information (abstract, keywords, etc)

Session 1A (SS-1) Deep Learning for Applications that Live on Big Data
Time: 11:00 - 12:15 Tuesday, January 23, 2018
Location: Room 302
Organizer: Deming Chen (Univ. of Illinois, Urbana-Champaign)

1A-1 (Time: 11:00 - 11:25)

Title	(Invited Paper) Quantized Deep Neural Networks for Energy Efficient Hardware-based Inference
Author	Ruizhou Ding, Zeye Liu, *R. D. (Shawn) Blanton, Diana Marculescu (Carnegie Mellon Univ., U.S.A.)
Page	pp. 1 - 8
Detailed information (abstract, keywords, etc)

1A-2 (Time: 11:25 - 11:50)

Title	(Invited Paper) Intelligent Corner Synthesis via Cycle-Consistent Generative Adversarial Networks for Efficient Validation of Autonomous Driving Systems
Author	Handi Yu (Duke Univ., U.S.A.), *Xin Li (Duke Univ. / Duke Kunshan Univ., U.S.A.)
Page	pp. 9 - 15
Detailed information (abstract, keywords, etc)

1A-3 (Time: 11:50 - 12:15)

Title	(Invited Paper) Deep Learning for Better Variant Calling for Cancer Diagnosis and Treatment
Author	Anand Ramachandran, Huiren Li, Eric Klee, Steven S. Lumetta, *Deming Chen (UIUC, U.S.A.)
Page	pp. 16 - 21
Detailed information (abstract, keywords, etc)

Session 1B System Level Management and Optimization
Time: 11:00 - 12:15 Tuesday, January 23, 2018
Location: Room 401
Chairs: Ji-Hoon Kim (Seoul National Univ. of Science and Tech., Republic of Korea), Youngjoo Lee (POSTECH, Republic of Korea)

1B-1 (Time: 11:00 - 11:25)

Title	Multi-Device Collaborative Management Through Knowledge Sharing
Author	*Zhongyuan Tian (Hong Kong Univ. of Science and Tech., Hong Kong), Zhe Wang (Huawei Technologies, China), Haoran Li, Peng Yang, Rafael Kioji Vivas Maeda, Jiang Xu (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 22 - 27
Detailed information (abstract, keywords, etc)

1B-2 (Time: 11:25 - 11:50)

Title	SQLiteKV: An Efficient LSM-tree-based SQLite-like Database Engine for Mobile Devices
Author	*Yuanjing Shi, Zhaoyan Shen, Zili Shao (Hong Kong Polytechnic Univ., Hong Kong)
Page	pp. 28 - 33
Detailed information (abstract, keywords, etc)

1B-3 (Time: 11:50 - 12:15)

Title	DI-SSD: Desymmetrized Interconnection Architecture and Dynamic Timing Calibration for Solid-State Drives
Author	Ren-Shuo Liu, *Jian-Hao Huang (National Tsing Hua Univ., Taiwan)
Page	pp. 34 - 39
Detailed information (abstract, keywords, etc)

Session 1C Advances in Bio-Chip and Bio-Data-Processing
Time: 11:00 - 12:15 Tuesday, January 23, 2018
Location: Room 402A
Chairs: Yanzhi Wang (Syracuse Univ., U.S.A.), Juinn-Dar Huang (National Chiao Tung Univ., Taiwan)

1C-1 (Time: 11:00 - 11:25)

Title	Sound Valve-Control for Programmable Microfluidic Devices
Author	*Andreas Grimmer, Berislav Klepic (Johannes Kepler Univ. Linz, Austria), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Robert Wille (Johannes Kepler Univ. Linz, Austria)
Page	pp. 40 - 45
Detailed information (abstract, keywords, etc)

1C-2 (Time: 11:25 - 11:50)

Title	Multi-Level Droplet Routing in Active-Matrix Based Digital-Microfluidic Biochips
Author	*Guan-Ruei Lu (National Chiao Tung Univ., Taiwan), Bhargab B. Bhattacharya (Indian Statistical Institute, India), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Page	pp. 46 - 51
Detailed information (abstract, keywords, etc)

1C-3 (Time: 11:50 - 12:15)

Title	MESGA: An MPSoC Based Embedded System Solution for Short Read Genome Alignment
Author	*Vikkitharan Gnanasambandapillai, Arash Bayat, Sri Parameswaran (Univ. of New South Wales, Australia)
Page	pp. 52 - 57
Detailed information (abstract, keywords, etc)

Session 1D Resource-Constrained Scheduling
Time: 11:00 - 12:15 Tuesday, January 23, 2018
Location: Room 402B
Chairs: Jingtong Hu (Univ. of Pittsburgh, U.S.A.), Yuan-Hao Chang (Academia Sinica, Taiwan)

1D-1 (Time: 11:00 - 11:25)

Title	Scheduling and Shaping of Complex Task Activations for Mixed-Criticality Systems
Author	Biao Hu (Beijing Univ. of Chemical Tech., China), *Kai Huang (Sun Yat-sen Univ., China)
Page	pp. 58 - 63
Detailed information (abstract, keywords, etc)

1D-2 (Time: 11:25 - 11:50)

Title	BUQS: Battery- and User-aware QoS Scaling for Interactive Mobile Devices
Author	*Wooseok Lee, Reena Panda (Univ. of Texas, Austin, U.S.A.), Dam Sunwoo, Jose Joao (ARM R&D, U.S.A.), Andreas Gerstlauer, Lizy K. John (Univ. of Texas, Austin, U.S.A.)
Page	pp. 64 - 69
Detailed information (abstract, keywords, etc)

1D-3 (Time: 11:50 - 12:15)

Title	Power Conversion Efficiency-Aware Mapping of Multithreaded Applications on Heterogeneous Architectures: A Comprehensive Parameter Tuning
Author	*Hossein Sayadi (George Mason Univ., U.S.A.), Divya Pathak, Ioannis Savidis (Drexel Univ., U.S.A.), Houman Homayoun (George Mason Univ., U.S.A.)
Page	pp. 70 - 75
Detailed information (abstract, keywords, etc)

Session 2A (SS-2) New Advances in Hardware Security
Time: 13:45 - 15:25 Tuesday, January 23, 2018
Location: Room 302
Organizer: Gang Qu (Univ. of Maryland, U.S.A.)

2A-1 (Time: 13:45 - 14:10)

Title	(Invited Paper) Effect of Aging on Linear and Nonlinear MUX PUFs by Statistical Modeling
Author	Anoop Koyily, S.V. Sandeep Avvaru, Chen Zhou, Chris H. Kim, *Keshab K. Parhi (Univ. of Minnesota, U.S.A.)
Page	pp. 76 - 83
Detailed information (abstract, keywords, etc)

2A-2 (Time: 14:10 - 14:35)

Title	(Invited Paper) ASAX: Automatic Security Assertion Extraction for Detecting Hardware Trojans
Author	*Chenguang Wang, Yici Cai, Qiang Zhou, Haoyi Wang (Tsinghua Univ., China)
Page	pp. 84 - 89
Detailed information (abstract, keywords, etc)

2A-3 (Time: 14:35 - 15:00)

Title	(Invited Paper) Polymorphic Gate based IC Watermarking Techniques
Author	*Tian Wang, Xiaoxin Cui, Dunshan Yu (Peking Univ., China), Omid Aramoon, Timothy Dunlap, Gang Qu (Univ. of Maryland, U.S.A.), Xiaole Cui (Peking Univ. Shenzhen Graduate School, China)
Page	pp. 90 - 96
Detailed information (abstract, keywords, etc)

2A-4 (Time: 15:00 - 15:25)

Title	(Invited Paper) A Machine Learning Attack Resistant Multi-PUF Design on FPGA
Author	Qingqing Ma (Nanjing Univ. of Aeronautics and Astronautics, China), Chongyan Gu, Neil Hanley (Queen's Univ. Belfast, U.K.), Chenghua Wang, *Weiqiang Liu (Nanjing Univ. of Aeronautics and Astronautics, China), Maire O'Neill (Queen's Univ. Belfast, U.K.)
Page	pp. 97 - 104
Detailed information (abstract, keywords, etc)

Session 2B Energy-Efficient CNN Accelerators
Time: 13:45 - 15:25 Tuesday, January 23, 2018
Location: Room 401
Chairs: Chun-Yi Lee (National Tsing Hua Univ., Taiwan), Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan)

2B-1 (Time: 13:45 - 14:10)

Title	Supporting Compressed-Sparse Activations and Weights on SIMD-like Accelerator for Sparse Convolutional Neural Networks
Author	*Chien-Yu Lin, Bo-Cheng Lai (National Chiao Tung Univ., Taiwan)
Page	pp. 105 - 110
Detailed information (abstract, keywords, etc)

2B-2 (Time: 14:10 - 14:35)

Title	IMCE: Energy-Efficient Bit-Wise In-Memory Convolution Engine for Deep Neural Network
Author	Shaahin Angizi, Zhezhi He, Farhana Parveen, *Deliang Fan (Univ. of Central Florida, U.S.A.)
Page	pp. 111 - 116
Detailed information (abstract, keywords, etc)

2B-3 (Time: 14:35 - 15:00)

Title	Training Low Bitwidth Convolutional Neural Network on RRAM
Author	*Yi Cai, Tianqi Tang, Lixue Xia, Ming Cheng, Zhenhua Zhu, Yu Wang, Huazhong Yang (Tsinghua Univ., China)
Page	pp. 117 - 122
Detailed information (abstract, keywords, etc)

2B-4 (Time: 15:00 - 15:25)

Title	A High-Throughput and Energy-Efficient RRAM-based Convolutional Neural Network using Data Encoding and Dynamic Quantization
Author	*Xizi Chen, Jingbo Jiang, Jingyang Zhu, Chi-Ying Tsui (Hong Kong Univ. of Science and Tech., China)
Page	pp. 123 - 128
Detailed information (abstract, keywords, etc)

Session 2C Networks on Chips and Beyond
Time: 13:45 - 15:25 Tuesday, January 23, 2018
Location: Room 402A
Chairs: Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany), John Kim (KAIST, Republic of Korea)

2C-1 (Time: 13:45 - 14:10)

Title	DRL-Cloud: Deep Reinforcement Learning-Based Resource Provisioning and Task Scheduling for Cloud Service Providers
Author	Mingxi Cheng (Duke Univ., U.S.A.), Ji Li, *Shahin Nazarian (Univ. of Sourthern California, U.S.A.)
Page	pp. 129 - 134
Detailed information (abstract, keywords, etc)

2C-2 (Time: 14:10 - 14:35)

Title	Pairing of Microring-based Silicon Photonic Transceivers for Tuning Power Optimization
Author	Rui Wu (Univ. of California, Santa Barbara, U.S.A.), M. Ashkan Seyedi (Hewlett Packard Labs, U.S.A.), *Yuyang Wang (Univ. of California, Santa Barbara, U.S.A.), Jared Hulme, Marco Fiorentino, Raymond G. Beausoleil (Hewlett Packard Labs, U.S.A.), Kwang-Ting Cheng (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 135 - 140
Detailed information (abstract, keywords, etc)

2C-3 (Time: 14:35 - 15:00)

Title	Neu-NoC: A High-efficient Interconnection Network for Accelerated Neuromorphic Systems
Author	Xiaoxiao Liu, Wei Wen (Univ. of Pittsburgh, U.S.A.), Xuehai Qian (Univ. of Southern California, U.S.A.), Hai Li, *Yiran Chen (Duke Univ., U.S.A.)
Page	pp. 141 - 146
Detailed information (abstract, keywords, etc)

2C-4 (Time: 15:00 - 15:25)

Title	A Lifetime-aware Mapping Algorithm to Extend MTTF of Networks-on-Chip
Author	*Letian Huang, Shuyu Chen, Qiong Wu (Univ. of Electronic Science and Tech. of China, China), Masoumeh Ebrahimi (Royal Inst. of Tech., Sweden), Junshi Wang, Shuyan Jiang, Qiang Li (Univ. of Electronic Science and Tech. of China, China)
Page	pp. 147 - 152
Detailed information (abstract, keywords, etc)

Session 2D Timing Exploration: Modeling, Analysis and Optimization
Time: 13:45 - 15:25 Tuesday, January 23, 2018
Location: Room 402B
Chairs: Ting-Chi Wang (National Tsing Hua Univ., Taiwan), Sheldon Tan (Univ. of California, Riverside, U.S.A.)

2D-1 (Time: 13:45 - 14:10)

Title	Layout-Dependent Aging Mitigation for Critical Path Timing
Author	Che-Lun Hsu (Univ. of Texas, Austin, U.S.A.), Shaofeng Guo (Peking Univ., China), Yibo Lin, Xiaoqing Xu, *Meng Li (Univ. of Texas, Austin, U.S.A.), Runsheng Wang, Ru Huang (Peking Univ., China), David Pan (Univ. of Texas, Austin, U.S.A.)
Page	pp. 153 - 158
Detailed information (abstract, keywords, etc)

2D-2 (Time: 14:10 - 14:35)

Title	MTTF-aware Design Methodology of Error Prediction Based Adaptively Voltage-scaled Circuits
Author	*Yutaka Masuda, Masanori Hashimoto (Osaka Univ., Japan)
Page	pp. 159 - 165
Detailed information (abstract, keywords, etc)

2D-3 (Time: 14:35 - 15:00)

Title	A Highly Compressed Timing Macro-modeling Algorithm for Hierarchical and Incremental Timing Analysis
Author	*Tin-Yin Lai, Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Page	pp. 166 - 171
Detailed information (abstract, keywords, etc)

2D-4 (Time: 15:00 - 15:25)

Title	FastPass: Fast Timing Path Search for Generalized Timing Exception Handling
Author	*Pei-Yu Lee (National Chiao Tung Univ., Taiwan), Iris Hui-Ru Jiang (National Taiwan Univ., Taiwan), Tung-Chieh Chen (Maxeda Technology, Taiwan)
Page	pp. 172 - 177
Detailed information (abstract, keywords, etc)

Session 3A Machine Learning Architecture Design and Its Applications
Time: 15:55 - 17:35 Tuesday, January 23, 2018
Location: Room 302
Chairs: Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Donghwa Shin (Yeungnam Univ., Republic of Korea)

3A-1 (Time: 15:55 - 16:20)

Title	ReGAN: A Pipelined ReRAM-Based Accelerator for Generative Adversarial Networks
Author	*Fan Chen, Linghao Song, Yiran Chen (Duke Univ., U.S.A.)
Page	pp. 178 - 183
Detailed information (abstract, keywords, etc)

3A-2 (Time: 16:20 - 16:45)

Title	Quad-Multiplier Packing Based on Customized Floating Point for Convolutional Neural Networks on FPGA
Author	*Zhifeng Zhang, Dajiang Zhou, Shihao Wang, Shinji Kimura (Waseda Univ., Japan)
Page	pp. 184 - 189
Detailed information (abstract, keywords, etc)

3A-3 (Time: 16:45 - 17:10)

Title	Sparse Ternary Connect: Convolutional Neural Networks Using Ternarized Weights with Enhanced Sparsity
Author	*Canran Jin, Heming Sun, Shinji Kimura (Waseda Univ., Japan)
Page	pp. 190 - 195
Detailed information (abstract, keywords, etc)

3A-4 (Time: 17:10 - 17:35)

Title	A Deep Reinforcement Learning Framework for Optimizing Fuel Economy of Hybrid Electric Vehicles
Author	Pu Zhao (Northeastern Univ., U.S.A.), *Yanzhi Wang (Syracuse Univ., U.S.A.), Naehyuck Chang (Korea Advanced Institute of Science and Engineering, Republic of Korea), Qi Zhu (Northwestern Univ., U.S.A.), Xue Lin (Northeastern Univ., U.S.A.)
Page	pp. 196 - 202
Detailed information (abstract, keywords, etc)

Session 3B Advanced Memory Architecture
Time: 15:55 - 17:35 Tuesday, January 23, 2018
Location: Room 401
Chairs: Hyung Gyu Lee (Daegu Univ., Republic of Korea), Hoeseok Yang (Ajou Univ., Republic of Korea)

3B-1 (Time: 15:55 - 16:20)

Title	Process Variation and Temperature Aware Adaptive Scrubbing for Retention Failures in STT-MRAM
Author	Nour Sayed, Sarath Mohanachandran Nair, Rajendra Bishnoi, *Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany)
Page	pp. 203 - 208
Detailed information (abstract, keywords, etc)

3B-2 (Time: 16:20 - 16:45)

Title	PIMCH: Cooperative Memory Prefetching in Processing-In-Memory Architecture
Author	*Sheng Xu, Ying Wang, Yinhe Han, Xiaowei Li (Chinese Academy of Sciences, China)
Page	pp. 209 - 214
Detailed information (abstract, keywords, etc)

3B-3 (Time: 16:45 - 17:10)

Title	CAMO: A Novel Cache Management Organization for GPGPUs
Author	*Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy (Indian Inst. of Tech., Bhubaneswar, India), Madhu Mutyam (Indian Inst. of Tech. Madras, India), Laxmi Narayan Bhuyan (Univ. of California, Riverside, U.S.A.)
Page	pp. 215 - 220
Detailed information (abstract, keywords, etc)

Best Paper Award
3B-4 (Time: 17:10 - 17:35)

Title	Process Variation Aware Data Management for Magnetic Skyrmions Racetrack Memory
Author	*Fan Chen (Duke Univ., U.S.A.), Zheng Li (Univ. of Pittsburgh, U.S.A.), Wang Kang, Weisheng Zhao (Beihang Univ., China), Hai Li, Yiran Chen (Duke Univ., U.S.A.)
Page	pp. 221 - 226
Detailed information (abstract, keywords, etc)

Session 3C Advanced Testing and Diagnosis Techniques
Time: 15:55 - 17:35 Tuesday, January 23, 2018
Location: Room 402A
Chairs: Jin-Fu Li (National Central Univ., Taiwan), Jing-Jia Liou (National Tsing Hua Univ., Taiwan)

3C-1 (Time: 15:55 - 16:20)

Title	Optimizing Dynamic Mapping Techniques for On-Line NoC Test
Author	Shuyan Jiang, *Qiong Wu, Shuyu Chen, Junshi Wang (Univ. of Electronic Science and Tech. of China, China), Masoumeh Ebrahimi (Royal Inst. of Tech., Sweden), Letian Huang, Qiang Li (Univ. of Electronic Science and Tech. of China, China)
Page	pp. 227 - 232
Detailed information (abstract, keywords, etc)

3C-2 (Time: 16:20 - 16:45)

Title	On Enabling Diagnosis for 1-Pin Test Fails in an Industrial Flow
Author	*Daniel Tille, Benedikt Gottinger, Ulrike Pfannkuchen (Infineon Technologies AG, Germany), Helmut Graeb, Ulf Schlichtmann (Tech. Univ. of Munich, Germany)
Page	pp. 233 - 238
Detailed information (abstract, keywords, etc)

3C-3 (Time: 16:45 - 17:10)

Title	Approximation-aware Testing for Approximate Circuits
Author	Arun Chandrasekharan, Stephan Eggersglüß, *Daniel Große, Rolf Drechsler (Univ. of Bremen, Germany)
Page	pp. 239 - 244
Detailed information (abstract, keywords, etc)

3C-4 (Time: 17:10 - 17:35)

Title	A Channel-Sharable Built-In Self-Test Scheme for Multi-Channel DRAMs
Author	*Kuan-Te Wu, Jin-Fu Li (National Central Univ., Taiwan), Chin-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou (ITRI, Taiwan)
Page	pp. 245 - 250
Detailed information (abstract, keywords, etc)

Session 3D Split Manufacturing, Logic Obfuscation and Camouflaging
Time: 15:55 - 17:35 Tuesday, January 23, 2018
Location: Room 402B
Chairs: Gang Qu (Univ. of Maryland, U.S.A.), Weiqiang Liu (Nanjing Univ. of Aeronautics and Astronautics, China)

3D-1 (Time: 15:55 - 16:20)

Title	Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing
Author	*Satwik Patnaik (New York Univ., U.S.A.), Johann Knechtel, Mohammed Ashraf, Ozgur Sinanoglu (New York Univ. Abu Dhabi, United Arab Emirates)
Page	pp. 251 - 258
Detailed information (abstract, keywords, etc)

3D-2 (Time: 16:20 - 16:45)

Title	A Conflict-Free Approach for Parallelizing SAT-Based De-Camouflaging Attacks
Author	*Xueyan Wang, Qiang Zhou, Yici Cai (Tsinghua Univ., China), Gang Qu (Univ. of Maryland, College Park, U.S.A.)
Page	pp. 259 - 264
Detailed information (abstract, keywords, etc)

3D-3 (Time: 16:45 - 17:10)

Title	A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion
Author	*Meng Li (Univ. of Texas, Austin, U.S.A.), Bei Yu (Chinese Univ. of Hong Kong, Hong Kong), Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Page	pp. 265 - 270
Detailed information (abstract, keywords, etc)

3D-4 (Time: 17:10 - 17:35)

Title	A Comparative Investigation of Approximate Attacks on Logic Encryptions
Author	Yuanqi Shen, Amin Rezaei, *Hai Zhou (Northwestern Univ., U.S.A.)
Page	pp. 271 - 276
Detailed information (abstract, keywords, etc)

Wednesday, January 24, 2018

Session 2K Keynote II
Time: 9:00 - 10:00 Wednesday, January 24, 2018
Location: Halla HALL
Chair: Youngsoo Shin (KAIST, Republic of Korea)

2K-1 (Time: 9:00 - 10:00)

Title	(Keynote Address) Quality, Schedule and Cost: Design Technology and the Last Semiconductor Scaling Levers
Author	Andrew B. Kahng (UCSD, U.S.A.)
Detailed information (abstract, keywords, etc)

Session 4A University Design Contest
Time: 10:30 - 12:10 Wednesday, January 24, 2018
Location: Room 302
Chairs: Minkyu Je (KAIST, Republic of Korea), Ikjoon Chang (Kyung Hee Univ., Republic of Korea)

Best Design Award
4A-1 (Time: 10:30 - 10:33)

Title	An Ultra-Low-Noise Differential Relaxation Oscillator based on a Swing-Boosting Scheme
Author	Junghyup Lee, *Arup George (Daegu Gyeongbuk Inst. of Science and Tech., Republic of Korea), Minkyu Je (KAIST, Republic of Korea)
Page	pp. 277 - 278
Detailed information (abstract, keywords, etc)

Best Design Award
4A-2 (Time: 10:33 - 10:36)

Title	A Nonvolatile Flip-Flop-Enabled Cryptographic Wireless Authentication Tag with Per-Query Key Update and Power-Glitch Attack Countermeasures
Author	Chiraag S. Juvekar (MIT, U.S.A.), Joyce Kwong (Texas Instruments, U.S.A.), *Hyung-Min Lee (Korea Univ., Republic of Korea), Anantha P. Chandrakasan (MIT, U.S.A.)
Page	pp. 279 - 280
Detailed information (abstract, keywords, etc)

Special Feature Award
4A-3 (Time: 10:36 - 10:39)

Title	A 42nJ/conversion On-Demand State-of-Charge Indicator for Miniature IoT Li-ion Batteries
Author	*Junwon Jeong (Korea Univ., Republic of Korea), Seokhyeon Jeong (Univ. of Michigan, U.S.A.), Chulwoo Kim (Korea Univ., Republic of Korea), Dennis Sylvester, David Blaauw (Univ. of Michigan, U.S.A.)
Page	pp. 281 - 282
Detailed information (abstract, keywords, etc)

Special Feature Award
4A-4 (Time: 10:39 - 10:42)

Title	A Supply Noise Insensitive PLL with a Rail-to-Rail Swing Ring Oscillator and a Wideband Noise Suppression Loop
Author	*Dongin Kim, SeongHwan Cho (KAIST, Republic of Korea)
Page	pp. 283 - 284
Detailed information (abstract, keywords, etc)

Special Feature Award
4A-5 (Time: 10:42 - 10:45)

Title	A Dual-Output SC Converter with Dynamic Power Allocation for Multi-Core Application Processors
Author	Junmin Jiang (Hong Kong Univ. of Science and Tech., Hong Kong), *Yan Lu (Univ. of Macau, Macau), Xun Liu, Wing-Hung Ki, Philip K. T. Mok (Hong Kong Univ. of Science and Tech., Hong Kong), Seng-Pan U, Rui P. Martins (Univ. of Macau, Macau)
Page	pp. 285 - 286
Detailed information (abstract, keywords, etc)

4A-6 (Time: 10:45 - 10:48)

Title	12Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling with 100% Data Payload and Spread Transition Scheme for 8K UHD Intra-Panel Interface
Author	Yeonho Lee, *Yoonjae Choi, Chulwoo Kim (Korea Univ., Republic of Korea)
Page	pp. 287 - 288
Detailed information (abstract, keywords, etc)

4A-7 (Time: 10:48 - 10:51)

Title	A Digital SC Converter with High Efficiency and Low Voltage Ripple
Author	Junmin Jiang, *Wing-Hung Ki (Hong Kong Univ. of Science and Tech., Hong Kong), Yan Lu (Univ. of Macau, Macau)
Page	pp. 289 - 290
Detailed information (abstract, keywords, etc)

4A-8 (Time: 10:51 - 10:54)

Title	A Reconfigurable SIMO System with 10-Output Dual-Bus DC-DC Converter using the Load Balancing Function in Group Allocator for Diversified Load Condition
Author	*Se-Un Shin, Sang-Hui Park, Gyu-Hyeong Cho (KAIST, Republic of Korea)
Page	pp. 291 - 292
Detailed information (abstract, keywords, etc)

4A-9 (Time: 10:54 - 10:57)

Title	Real-time Depth Map Processor for Offset Aperture based Single Camera System
Author	Hyeji Kim, Jinyeon Lim, *Yeongmin Lee, Woojin Yun, Young-Gyu Kim, Wonseok Choi, Asim Khan (KAIST, Republic of Korea), Muhammad Umar Karim Khan, Said Homidov (Center for Integrated Smart Sensors, Republic of Korea), Hyun Sang Park (Kongju National Univ., Republic of Korea), Chong-Min Kyung (KAIST, Republic of Korea)
Page	pp. 293 - 294
Detailed information (abstract, keywords, etc)

4A-10 (Time: 10:57 - 11:00)

Title	Edge Pursuit Comparator with Application in a 74.1dB SNDR, 20KS/s 15b SAR ADC
Author	*Minseob Shim (Korea Univ., Republic of Korea), Seokhyeon Jeong (Univ. of Michigan, U.S.A.), Paul Myers (Massachusetts Inst. of Tech., U.S.A.), Suyoung Bang (Intel Circuit Research Lab, U.S.A.), Junhua Shen (Analog Devices, U.S.A.), Chulwoo Kim (Korea Univ., Republic of Korea), Dennis Sylvester, David Blaauw, Wanyeong Jung (Univ. of Michigan, U.S.A.)
Page	pp. 295 - 296
Detailed information (abstract, keywords, etc)

4A-11 (Time: 11:00 - 11:03)

Title	A 300-μW Audio ΔΣ Modulator with 100.5-dB DR Using Dynamic Bias Inverter
Author	*Sangwoo Lee, Woojin Jo, Seungwoo Song, Youngcheol Chae (Yonsei Univ., Republic of Korea)
Page	pp. 297 - 298
Detailed information (abstract, keywords, etc)

4A-12 (Time: 11:03 - 11:06)

Title	An External-Capacitor-Less High PSR Low-Dropout Regulator Using an Adaptive Supply-Ripple Cancellation Technique to the Body-Gate
Author	*Younghyun Lim, Jeonghyun Lee, Suneui Park, Jaehyouk Choi (UNIST, Republic of Korea)
Page	pp. 299 - 300
Detailed information (abstract, keywords, etc)

4A-13 (Time: 11:06 - 11:09)

Title	A 230-260GHz Wideband Amplifier in 65nm CMOS Based on Dual-Peak G_max-core
Author	*Dae-Woong Park, Dzuhri Utomo (KAIST, Republic of Korea), Jong-Phil Hong (Chungbuk National Univ., Republic of Korea), Sang-Gug Lee (KAIST, Republic of Korea)
Page	pp. 301 - 302
Detailed information (abstract, keywords, etc)

4A-14 (Time: 11:09 - 11:12)

Title	Injection-Locked Frequency Multiplier with a Continuous Frequency-Tracking Loop for 5G Transceivers
Author	*Seyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi (Ulsan National Inst. of Science and Tech., Republic of Korea)
Page	pp. 303 - 304
Detailed information (abstract, keywords, etc)

4A-15 (Time: 11:12 - 11:15)

Title	A 6.9mW 120fps 28×50 Capacitive Touch Sensor for 1mm-φ Stylus Using Current-Driven ΔΣ ADCs
Author	*Hyunseok Hwang, Hyeyeon Lee, Youngcheol Chae (Yonsei Univ., Republic of Korea)
Page	pp. 305 - 306
Detailed information (abstract, keywords, etc)

4A-16 (Time: 11:15 - 11:18)

Title	A Switched-Loop-Filter PLL with Fast Phase-Error Correction Technique
Author	*Yongsun Lee, Taeho Seong, Seyeon Yoo, Jaehyouk Choi (UNIST, Republic of Korea)
Page	pp. 307 - 308
Detailed information (abstract, keywords, etc)

4A-17 (Time: 11:18 - 11:21)

Title	A 9.3 nW All-in-One Bandgap Voltage and Current Reference Circuit using Leakage-based PTAT Generation and DIBL Characteristic
Author	*Youngwoo Ji, Cheonhoo Jeon, Hyunwoo Son, Byungsub Kim, Hong-June Park, Jae-Yoon Sim (POSTECH, Republic of Korea)
Page	pp. 309 - 310
Detailed information (abstract, keywords, etc)

4A-18 (Time: 11:21 - 11:24)

Title	A 16.6-pJ/b 150-Mb/s Body-Channel Communication Transceiver with Decision Feedback Equalization Improving >200x Area Efficiency
Author	*Ji-Hoon Lee (KIST, Republic of Korea), Kwangmin Kim, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim (POSTECH, Republic of Korea)
Page	pp. 311 - 312
Detailed information (abstract, keywords, etc)

4A-19 (Time: 11:24 - 11:27)

Title	Low Power FSK Transceiver using ADPLL with Direct Modulation and Integrated SPDT for BLE Application
Author	*Dongsoo Lee, Sungjin Kim, Seongjin Oh, Gyusub Won, Thi kim nga Truong, Imran Ali, Hamed Abbasizadeh, Behnam Samadpoor Rikan, Kang-Yoon Lee (Sungkyunkwan Univ., Republic of Korea)
Page	pp. 313 - 314
Detailed information (abstract, keywords, etc)

4A-20 (Time: 11:27 - 11:30)

Title	A 2.22 Gbps High-Throughput NB-LDPC Decoder in 65nm CMOS with Aggressive Overlap Scheduling
Author	Injun Choi (Silicon Works, Republic of Korea), *Ji-Hoon Kim (Seoul National Univ. of Science and Tech., Republic of Korea)
Page	pp. 315 - 316
Detailed information (abstract, keywords, etc)

4A-21 (Time: 11:30 - 11:33)

Title	Design of Resource Sharing Reconfigurable ΔΣ SAR-ADC
Author	*Motomi Ishizuka, Kohei Yamada, Hiroki Ishikuro (Keio Univ., Japan)
Page	pp. 317 - 318
Detailed information (abstract, keywords, etc)

4A-22 (Time: 11:33 - 11:36)

Title	A 2.4GHz, -102dBm-Sensitivity, 25kb/s, 0.466mW Interference Resistant BFSK Multi-Channel Sliding-IF ULP Receiver
Author	*Hyun-Gi Seok, Oh-Yong Jung, Anjana Dissanayake, Sang-Gug Lee (KAIST, Republic of Korea)
Page	pp. 319 - 320
Detailed information (abstract, keywords, etc)

4A-23 (Time: 11:36 - 11:39)

Title	Highly Sensitive Fingerprint Readout IC for Glass-Covered Mutual Capacitive Fingerprint Sensor
Author	*Kyeongmin Park, Joohyeob Song, Franklin Bien (Ulsan National Inst. of Science and Tech., Republic of Korea)
Page	pp. 321 - 322
Detailed information (abstract, keywords, etc)

4A-24 (Time: 11:39 - 11:42)

Title	A 5.8 GHz DSRC Digitally Controlled CMOS RF-SoC Transceiver for China ETC
Author	Huimin Liu, Xiongfei Qu, Lingling Cao (Tianjin Univ. of Tech., China), Ruifeng Liu (RF Microelectronics, China), Yuanzhi Zhang (Southern Illinois Univ. Carbondale, U.S.A.), Meijuan Zhang, Xiaoqiang Li, Wenshen Wang (Tianjin Univ. of Tech., China), *Chao Lu (Southern Illinois Univ. Carbondale, U.S.A.)
Page	pp. 323 - 324
Detailed information (abstract, keywords, etc)

4A-25 (Time: 11:42 - 11:45)

Title	A Low-Power Wide Dynamic-Range Current Readout Circuit for Biosensors
Author	*Hyunwoo Son, Hwasuk Cho, Jahyun Koo, Youngwoo Ji, Byungsub Kim, Hong-June Park, Jae-Yoon Sim (POSTECH, Republic of Korea)
Page	pp. 325 - 326
Detailed information (abstract, keywords, etc)

4A-26 (Time: 11:45 - 11:48)

Title	An Efficient Fixed-point Arithmetic Processor Using a Hybrid CORDIC Algorithm
Author	*Hong-Thu Nguyen, Xuan-Thuan Nguyen, Cong-Kha Pham (Univ. of Electro-Communications, Japan)
Page	pp. 327 - 328
Detailed information (abstract, keywords, etc)

4A-27 (Time: 11:48 - 11:51)

Title	A 2.4pJ/bit, 6.37Gb/s SPC-enhanced BC-BCH Decoder in 65nm CMOS for NAND Flash Storage Systems
Author	*Jaehwan Jung, In-Cheol Park (KAIST, Republic of Korea), Youngjoo Lee (POSTECH, Republic of Korea)
Page	pp. 329 - 330
Detailed information (abstract, keywords, etc)

Session 4B System Architectures
Time: 10:30 - 12:10 Wednesday, January 24, 2018
Location: Room 401
Chairs: Sri Parameswaran (Univ. of New South Wales, Australia), Jing-Jia Liou (National Tsing Hua Univ., Taiwan)

4B-1 (Time: 10:30 - 10:55)

Title	Exploring Energy and Accuracy Tradeoff in Structure Simplification of Trained Deep Neural Networks
Author	*Boyu Zhang, Azadeh Davoodi, Yu-Hen Hu (Univ. of Wisconsin-Madison, U.S.A.)
Page	pp. 331 - 336
Detailed information (abstract, keywords, etc)

4B-2 (Time: 10:55 - 11:20)

Title	Low Latency Parallel Implementation of Traditionally-Called Stochastic Circuits using Deterministic Shuffling Networks
Author	*Zhiheng Wang, Soheil Mohajer, Kia Bazargan (Univ. of Minnesota, Twin Cities, U.S.A.)
Page	pp. 337 - 342
Detailed information (abstract, keywords, etc)

4B-3 (Time: 11:20 - 11:45)

Title	Optimizing FPGA-based Convolutional Neural Networks Accelerator for Image Super-Resolution
Author	*Jung-Woo Chang, Suk-Ju Kang (Sogang Univ., Republic of Korea)
Page	pp. 343 - 348
Detailed information (abstract, keywords, etc)

4B-4 (Time: 11:45 - 12:10)

Title	XORiM: A Case of In-Memory Bit-Comparator Implementation and Its Performance Implications
Author	*Kaiwei Zou, Ying Wang, Huawei Li, Xiaowei Li (Chinese Academy of Sciences, China)
Page	pp. 349 - 354
Detailed information (abstract, keywords, etc)

Session 4C Emerging Technologies for Energy Efficient Computing
Time: 10:30 - 12:10 Wednesday, January 24, 2018
Location: Room 402A
Chairs: Shigeru Yamashita (Ritsumeikan Univ., Japan), Wujie Wen (Florida International Univ., U.S.A.)

4C-1 (Time: 10:30 - 10:55)

Title	Logic Synthesis for Energy-Efficient Photonic Integrated Circuits
Author	Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, *David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Page	pp. 355 - 360
Detailed information (abstract, keywords, etc)

4C-2 (Time: 10:55 - 11:20)

Title	HieIM: Highly Flexible In-Memory Computing using STT MRAM
Author	Farhana Parveen, Zhezhi He, Shaahin Angizi, *Deliang Fan (Univ. of Central Florida, U.S.A.)
Page	pp. 361 - 366
Detailed information (abstract, keywords, etc)

4C-3 (Time: 11:20 - 11:45)

Title	Performance Analysis on Structure of Racetrack Memory
Author	*Hongbin Zhang (Tsinghua Univ., China), Chao Zhang (Peking Univ., China), Qingda Hu (Tsinghua Univ., China), Chengmo Yang (Univ. of Delaware, U.S.A.), Jiwu Shu (Tsinghua Univ., China)
Page	pp. 367 - 374
Detailed information (abstract, keywords, etc)

4C-4 (Time: 11:45 - 12:10)

Title	Modeling of Biaxial Magnetic Tunneling Junction for Multi-level Cell STT-RAM Realization
Author	Enes Eken, Ismail Bayram (Univ. of Pittsburgh, U.S.A.), Hai (Helen) Li, *Yiran Chen (Duke Univ., U.S.A.)
Page	pp. 375 - 380
Detailed information (abstract, keywords, etc)

Session 4D Design for Manufacturability and Reliability
Time: 10:30 - 12:10 Wednesday, January 24, 2018
Location: Room 402B
Chair: Masanori Hashimoto (Osaka Univ., Japan)

4D-1 (Time: 10:30 - 10:55)

Title	Automatic Insertion of Airgap with Design Rule Constraints
Author	*Daijoon Hyun, Youngsoo Shin (KAIST, Republic of Korea)
Page	pp. 381 - 386
Detailed information (abstract, keywords, etc)

4D-2 (Time: 10:55 - 11:20)

Title	On Coloring Rectangular and Diagonal Grid Graphs for Multiple Patterning Lithography
Author	Daifeng Guo (Univ. of Illinois, Urbana-Champaign, U.S.A.), Hongbo Zhang (Facebook, U.S.A.), *Martin D.F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Page	pp. 387 - 392
Detailed information (abstract, keywords, etc)

4D-3 (Time: 11:20 - 11:45)

Title	Lifetime-aware Design Methodology for Dynamic Partially Reconfigurable Systems
Author	*Siva Satyendra Sahoo, Tuan D. A. Nguyen, Bharadwaj Veeravalli (National Univ. of Singapore, Singapore), Akash Kumar (Tech. Univ. Dresden, Germany)
Page	pp. 393 - 398
Detailed information (abstract, keywords, etc)

4D-4 (Time: 11:45 - 12:10)

Title	Electromigration-Lifetime Constrained Power Grid Optimization Considering Multi-Segment Interconnect Wires
Author	Han Zhou, Yijing Sun, Zeyu Sun, Hengyang Zhao, *Sheldon X.-D. Tan (Univ. of California, Riverside, U.S.A.)
Page	pp. 399 - 404
Detailed information (abstract, keywords, etc)

Session 5A (IS) Machine/Deep Learning for Semiconductor Design, EDA Technologies, and Application
Time: 13:40 - 15:45 Wednesday, January 24, 2018
Location: Room 302
Organizer: Kyu Myung Choi (Seoul National Univ., Republic of Korea)

5A-1 (Time: 13:40 - 14:05)

Title	(Invited Paper) New Directions for Learning-Based IC Design Tools and Methodologies
Author	*Andrew B. Kahng (Univ. of California, San Diego, U.S.A.)
Page	pp. 405 - 410
Detailed information (abstract, keywords, etc)

5A-2 (Time: 14:05 - 14:30)

Title	(Invited Paper) Machine Learning and Systems for Building the Next Generation of EDA tools
Author	*Manish Pandey (Synopsys, U.S.A.)
Page	pp. 411 - 415
Detailed information (abstract, keywords, etc)

5A-3 (Time: 14:30 - 14:55)

Title	(Invited Paper) Machine Learning based Generic Violation Waiver System with Application on Electromigration Sign-off
Author	*Norman Chang, Ajay Baranwal, Hao Zhuang, Ming-Chih Shih, Rahul Rajan, Yaowei Jia, Hui-Lun Liao, Ying-Shiun Li (ANSYS, U.S.A.), Ting Ku, Rex Lin (Nvidia, U.S.A.)
Page	pp. 416 - 421
Detailed information (abstract, keywords, etc)

5A-4 (Time: 14:55 - 15:20)

Title	(Invited Paper) Machine Learning for Engineering
Author	*Jeff Dyck (Solido Design Automation, U.S.A.)
Page	pp. 422 - 427
Detailed information (abstract, keywords, etc)

5A-5 (Time: 15:20 - 15:45)

Title	(Invited Paper) Large-scale Short-term Urban Taxi Demand Forecasting Using Deep Learning
Author	Siyu Liao (City Univ. of New York, U.S.A.), Liutong Zhou, Xuan Di (Columbia Univ., U.S.A.), Bo Yuan (City Univ. of New York, U.S.A.), *Jinjun Xiong (IBM, U.S.A.)
Page	pp. 428 - 433
Detailed information (abstract, keywords, etc)

Session 5B System Design Methodologies
Time: 13:40 - 15:45 Wednesday, January 24, 2018
Location: Room 401
Chairs: Naehyuck Chang (KAIST, Republic of Korea), Akash Kumar (Tech. Univ. Dresden, Germany)

5B-1 (Time: 13:40 - 14:05)

Title	Utilizing Quad-Trees for Efficient Design Space Exploration with Partial Assignment Evaluation
Author	*Kai Neubauer (Univ. of Rostock, Germany), Philipp Wanko, Torsten Schaub (Univ. of Potsdam, Germany), Christian Haubelt (Univ. of Rostock, Germany)
Page	pp. 434 - 439
Detailed information (abstract, keywords, etc)

5B-2 (Time: 14:05 - 14:30)

Title	SCBench: A Benchmark Design Suite for SystemC Verification and Validation
Author	*Bin Lin, Fei Xie (Portland State Univ., U.S.A.)
Page	pp. 440 - 445
Detailed information (abstract, keywords, etc)

5B-3 (Time: 14:30 - 14:55)

Title	MemFlow: Memory-Driven Data Scheduling with Datapath Co-design in Accelerators for Large-Scale Inference Applications
Author	*Qi Nie, Sharad Malik (Princeton Univ., U.S.A.)
Page	pp. 446 - 451
Detailed information (abstract, keywords, etc)

5B-4 (Time: 14:55 - 15:20)

Title	A Mapping Approach between IR and Binary CFGs Dealing with Aggressive Compiler Optimizations for Performance Estimation
Author	*Omayma Matoussi, Frédéric Pétrot (Tima Laboratory, Grenoble INP, France)
Page	pp. 452 - 457
Detailed information (abstract, keywords, etc)

5B-5 (Time: 15:20 - 15:45)

Title	System Level Performance Analysis and Optimization for the Adaptive Clocking based Multi-Core Processor
Author	*Byung Su Kim (Samsung Electronics, Republic of Korea), Joon-Sung Yang (Sungkyunkwan Univ., Republic of Korea)
Page	pp. 458 - 463
Detailed information (abstract, keywords, etc)

Session 5C Synthesis, Routing and Timing
Time: 13:40 - 15:45 Wednesday, January 24, 2018
Location: Room 402A
Chairs: Jason C. Verley (Sandia National Laboratory, U.S.A.), Chien-Nan (Jimmy) Liu (National Central Univ., Taiwan)

Best Paper Candidate
5C-1 (Time: 13:40 - 14:05)

Title	Detecting Non-Functional Circuit Activity in SoC Designs
Author	*Dustin Peterson, Yannick Boekle, Oliver Bringmann (Univ. of Tübingen, Germany)
Page	pp. 464 - 469
Detailed information (abstract, keywords, etc)

5C-2 (Time: 14:05 - 14:30)

Title	Multi-Level Timing Simulation on GPUs
Author	*Eric Schneider, Michael A. Kochte, Hans-Joachim Wunderlich (Univ. of Stuttgart, Germany)
Page	pp. 470 - 475
Detailed information (abstract, keywords, etc)

5C-3 (Time: 14:30 - 14:55)

Title	An Optimal Gate Design for the Synthesis of Ternary Logic Circuits
Author	*Sunmean Kim, Taeho Lim, Seokhyeong Kang (Ulsan National Inst. of Science and Tech., Republic of Korea)
Page	pp. 476 - 481
Detailed information (abstract, keywords, etc)

5C-4 (Time: 14:55 - 15:20)

Title	Performance-Preserved Analog Routing Methodology via Wire Load Reduction
Author	*Hao-Yu Chi, Hwa-Yi Tseng, Chien-Nan Jimmy Liu (National Central Univ., Taiwan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan)
Page	pp. 482 - 487
Detailed information (abstract, keywords, etc)

5C-5 (Time: 15:20 - 15:45)

Title	Static Timing Analysis for Ring Oscillators
Author	*David M. Moore (Univ. of Michigan, U.S.A.), Jeffrey A. Fredenburg, Muhammad Faisal (Movellus, U.S.A.), David D. Wentzloff (Univ. of Michigan, U.S.A.)
Page	pp. 488 - 493
Detailed information (abstract, keywords, etc)

Session 5D Advanced Placement and Routing Techniques
Time: 13:40 - 15:45 Wednesday, January 24, 2018
Location: Room 402B
Chairs: Yasuhiro Takashima (Univ. of Kitakyushu, Japan), Ting-Chi Wang (National Tsing Hua Univ., Taiwan)

5D-1 (Time: 13:40 - 14:05)

Title	OCV Guided Clock Tree Topology Reconstruction
Author	Necati Uysal, *Rickard Ewetz (Univ. of Central Florida, U.S.A.)
Page	pp. 494 - 499
Detailed information (abstract, keywords, etc)

5D-2 (Time: 14:05 - 14:30)

Title	Cohesive Techniques for Cell Layout Optimization Supporting 2D Metal-1 Routing Completion
Author	*Kyeongrok Jo, Seyong Ahn, Taewhan Kim, Kyumyung Choi (Seoul National Univ., Republic of Korea)
Page	pp. 500 - 506
Detailed information (abstract, keywords, etc)

5D-3 (Time: 14:30 - 14:55)

Title	Clustering of Flip-Flops for Useful-Skew Clock Tree Synthesis
Author	*Chuan Yean Tan (Purdue Univ., U.S.A.), Rickard Ewetz (Univ. of Central Florida, U.S.A.), Cheng-Kok Koh (Purdue Univ., U.S.A.)
Page	pp. 507 - 512
Detailed information (abstract, keywords, etc)

5D-4 (Time: 14:55 - 15:20)

Title	Optimal Die Placement for Interposer-Based 3D ICs
Author	*Sergii Osmolovskyi (Dresden Univ. of Tech., Germany), Johann Knechtel (New York Univ. Abu Dhabi, United Arab Emirates), Igor L. Markov (Univ. of Michigan, U.S.A.), Jens Lienig (Dresden Univ. of Tech., Germany)
Page	pp. 513 - 520
Detailed information (abstract, keywords, etc)

5D-5 (Time: 15:20 - 15:45)

Title	Flip-Chip Routing with IO Planning Considering Practical Pad Assignment Constraints
Author	*Tao-Chun Yu, Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan)
Page	pp. 521 - 526
Detailed information (abstract, keywords, etc)

Session 6A (SS-3) Training Deep Neural Networks: Algorithms and Architectures
Time: 16:15 - 17:30 Wednesday, January 24, 2018
Location: Room 302
Organizer: Kiyoung Choi (Seoul National Univ., Republic of Korea)

6A-1 (Time: 16:15 - 16:40)

Title	(Invited Paper) Accelerator-centric Deep Learning Systems for Enhanced Scalability, Energy-Efficiency, and Programmability
Author	*Minsoo Rhu (POSTECH, Republic of Korea)
Page	pp. 527 - 533
Detailed information (abstract, keywords, etc)

6A-2 (Time: 16:40 - 17:05)

Title	(Invited Paper) Running Sparse and Low-Precision Neural Network: When Algorithm Meets Hardware
Author	Bing Li, Wei Wen, Jiachen Mao (Duke Univ., U.S.A.), Sicheng Li (Hewlett Packard Labs, U.S.A.), *Yiran Chen, Hai(Helen) Li (Duke Univ., U.S.A.)
Page	pp. 534 - 539
Detailed information (abstract, keywords, etc)

6A-3 (Time: 17:05 - 17:30)

Title	(Invited Paper) Architectures and Algorithms for User Customization of CNNs
Author	Barend Harris, Mansureh S. Moghaddam, Duseok Kang, Inpyo Bae, Euiseok Kim, Hyemi Min (Seoul National Univ., Republic of Korea), Hansu Cho, Sukjin Kim (Samsung Electronics, Republic of Korea), *Bernhard Egger, Soonhoi Ha, Kiyoung Choi (Seoul National Univ., Republic of Korea)
Page	pp. 540 - 547
Detailed information (abstract, keywords, etc)

Session 6B Emerging Memory Management Techniques
Time: 16:15 - 17:30 Wednesday, January 24, 2018
Location: Room 401
Chairs: Minsoo Rhu (POSTECH, Republic of Korea), Pi-Cheng Hsiu (Academia Sinica, Taiwan)

6B-1 (Time: 16:15 - 16:40)

Title	Rethinking Self-balancing Binary Search Tree over Phase Change Memory with Write Asymmetry
Author	*Chieh-Fu Chang (Academia Sinica, Taiwan), Che-Wei Chang (Chang Gung Univ., Taiwan), Yuan-Hao Chang (Academia Sinica, Taiwan), Ming-Chang Yang (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 548 - 553
Detailed information (abstract, keywords, etc)

6B-2 (Time: 16:40 - 17:05)

Title	Energy, Latency, and Lifetime Improvements in MLC NVM with Enhanced WOM Code
Author	*Huizhang Luo, Liang Shi, Qiao Li (Chongqing Univ., China), Chun Jason Xue (City Univ. of Hong Kong, Hong Kong), Edwin H.-M. Sha (Chongqing Univ., China)
Page	pp. 554 - 559
Detailed information (abstract, keywords, etc)

6B-3 (Time: 17:05 - 17:30)

Title	Scheduling Multi-Rate Real-Time Applications on Clustered Many-Core Architectures with Memory Constraints
Author	*Matthias Becker, Saad Mubeen (Mälardalen Univ., Sweden), Dakshina Dasari (Robert Bosch GmbH, Germany), Moris Behnam, Thomas Nolte (Mälardalen Univ., Sweden)
Page	pp. 560 - 567
Detailed information (abstract, keywords, etc)

Session 6C Intelligent System Designs with Neuromorphic and Stochastic Technologies
Time: 16:15 - 17:30 Wednesday, January 24, 2018
Location: Room 402A
Chairs: Deliang Fan (Univ. of Central Florida, U.S.A.), Bing Li (Duke Univ., U.S.A.)

6C-1 (Time: 16:15 - 16:40)

Title	PT-Spike: A Precise-Time-Dependent Single Spike Neuromorphic Architecture with Efficient Supervised Learning
Author	Tao Liu (Florida International Univ., U.S.A.), Lei Jiang (Indiana Univ., U.S.A.), Yier Jin (Univ. of Florida, U.S.A.), Gang Quan, *Wujie Wen (Florida International Univ., U.S.A.)
Page	pp. 568 - 573
Detailed information (abstract, keywords, etc)

6C-2 (Time: 16:40 - 17:05)

Title	Fully Parallel RRAM Synaptic Array for Implementing Binary Neural Network with (+1, -1) Weights and (+1, 0) Neurons
Author	Xiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, *Shimeng Yu (Arizona State Univ., U.S.A.)
Page	pp. 574 - 579
Detailed information (abstract, keywords, etc)

6C-3 (Time: 17:05 - 17:30)

Title	Spintronics based Stochastic Computing for Efficient Bayesian Inference System
Author	Xiaotao Jia, *Jianlei Yang, Zhaohao Wang (Beihang Univ., China), Yiran Chen, Hai (Helen) Li (Duke Univ., U.S.A.), Weisheng Zhao (Beihang Univ., China)
Page	pp. 580 - 585
Detailed information (abstract, keywords, etc)

Session 6D New Flavors of Logic and Arithmetic Synthesis
Time: 16:15 - 17:30 Wednesday, January 24, 2018
Location: Room 402B
Chairs: Shouyi Yin (Tsinghua Univ., China), Jaeyong Chung (Incheon National Univ., Republic of Korea)

6D-1 (Time: 16:15 - 16:40)

Title	SAT-Based Area Recovery in Structural Technology Mapping
Author	*Bruno Schmitt (EPFL, Switzerland), Alan Mishchenko, Robert Brayton (UC Berkeley, U.S.A.)
Page	pp. 586 - 591
Detailed information (abstract, keywords, etc)

6D-2 (Time: 16:40 - 17:05)

Title	A Two-Step Search Engine for Large Scale Boolean Matching under NP3 Equivalence
Author	*Chak-Wa Pui, Peishan Tu, Haocheng Li, Gengjie Chen, Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 592 - 598
Detailed information (abstract, keywords, etc)

6D-3 (Time: 17:05 - 17:30)

Title	Low-Cost Hardware Architectures for Mersenne Modulo Functional Units
Author	Keith Campbell, Chen-Hsuan Lin, *Deming Chen (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Page	pp. 599 - 604
Detailed information (abstract, keywords, etc)

Thursday, January 25, 2018

Session 3K Keynote III
Time: 8:30 - 10:00 Thursday, January 25, 2018
Location: Halla HALL
Chair: Youngsoo Shin (KAIST, Republic of Korea)

3K-1 (Time: 8:30 - 9:15)

Title	(Keynote Address) CAE challenge on High Capacity/High Bandwidth Memory Design
Author	Woojong Han (SK Hynix, Republic of Korea)
Detailed information (abstract, keywords, etc)

3K-2 (Time: 9:15 - 10:00)

Title	(Keynote Address) TeraByte/s Bandwidth 2.5D HBM (High-bandwidth Memory Module) Designs for Deep Learning Artificial Intelligent Servers
Author	Joungho Kim (KAIST, Republic of Korea)
Detailed information (abstract, keywords, etc)

Session 7A Multiplier Design: From Accurate to Approximate
Time: 10:30 - 11:45 Thursday, January 25, 2018
Location: Room 302
Chairs: Kazuyoshi Takagi (Kyoto Univ., Japan), Youngjoo Lee (POSTECH)

7A-1 (Time: 10:30 - 10:55)

Title	A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design
Author	*Tongxin Yang, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ., Japan)
Page	pp. 605 - 610
Detailed information (abstract, keywords, etc)

7A-2 (Time: 10:55 - 11:20)

Title	Exploration of Approximate Multipliers Design Space using Carry Propagation Free Compressors
Author	Sina Boroumand (Univ. of Tehran, Iran), Hadi P. Afshar (Qualcomm Research, U.S.A.), *Philip Brisk (Univ. of California, Riverside, U.S.A.), Siamak Mohammadi (Univ. of Tehran, Iran)
Page	pp. 611 - 616
Detailed information (abstract, keywords, etc)

7A-3 (Time: 11:20 - 11:45)

Title	Low-power Implementation of Mitchell’s Approximate Logarithmic Multiplication for Convolutional Neural Networks
Author	*Min Soo Kim (Univ. of California, Irvine, U.S.A.), Alberto Antonio Del Barrio, Román Hermida (Univ. Complutense de Madrid, Spain), Nader Bagherzadeh (Univ. of California, Irvine, U.S.A.)
Page	pp. 617 - 622
Detailed information (abstract, keywords, etc)

Session 7B (SS-4) Reliability and Aging-Aware Designs for sub-10nm ICs
Time: 10:30 - 11:45 Thursday, January 25, 2018
Location: Room 401
Organizer: Sheldon Tan (UC Riverside, U.S.A.)

7B-1 (Time: 10:30 - 10:55)

Title	(Invited Paper) Accelerating Electromigration Aging for Fast Failure Detection for Nanometer ICs
Author	Zeyu Sun, Sheriff Sadiqbatcha, Hengyang Zhao, *Sheldon X.-D. Tan (Univ. of California, Riverside, U.S.A.)
Page	pp. 623 - 630
Detailed information (abstract, keywords, etc)

7B-2 (Time: 10:55 - 11:20)

Title	(Invited Paper) Efficient Worst-case Timing Analysis of Critical-path Delay under Workload-dependent Aging Degradation
Author	*Shumpei Morita, Song Bian (Kyoto Univ., Japan), Michihiro Shintani (NAIST, Japan), Masayuki Hiromoto, Takashi Sato (Kyoto Univ., Japan)
Page	pp. 631 - 636
Detailed information (abstract, keywords, etc)

7B-3 (Time: 11:20 - 11:45)

Title	(Invited Paper) Balancing Resiliency and Energy Efficiency of Functional Units in Ultra-low Power Systems
Author	Mohammad Saber Golanbari, Anteneh Gebregiorgis, Elyas Moradi, Saman Kiamehr, *Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany)
Page	pp. 637 - 644
Detailed information (abstract, keywords, etc)

Session 7C (SS-5) Design Automation and Methodology for Flexible Electronics
Time: 10:30 - 11:45 Thursday, January 25, 2018
Location: Room 402A
Organizers: Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany), Jim Huang (Hewlett Packard Labs)

7C-1 (Time: 10:30 - 10:55)

Title	(Invited Paper) Mechanical Strain and Temperature Aware Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array
Author	*Wenyu Sun, Yuxuan Huang, Qinghang Zhao, Fei Qiao (Tsinghua Univ., China), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Xiaojun Guo (Shanghai Jiao Tong Univ., China), Huazhong Yang, Yongpan Liu (Tsinghua Univ., China)
Page	pp. 645 - 650
Detailed information (abstract, keywords, etc)

7C-2 (Time: 10:55 - 11:20)

Title	(Invited Paper) Process Design Kit for Flexible Hybrid Electronics
Author	*Leilai Shao (UCSB, U.S.A.), Tsung-Ching Huang (Hewlett Packard Labs, U.S.A.), Ting Lei, Zhenan Bao (Stanford Univ., U.S.A.), Raymond Beausoleil (Hewlett Packard Labs, U.S.A.), Kwang-Ting Cheng (Hong-Kong Univ. of Science and Tech., China)
Page	pp. 651 - 657
Detailed information (abstract, keywords, etc)

7C-3 (Time: 11:20 - 11:45)

Title	(Invited Paper) From Silicon to Printed Electronics: A Coherent Modeling and Design Flow Approach Based on Printed Electrolyte Gated FETs
Author	Gabriel Cadilha Marques, Farhan Rasheed, Jasmin Aghassi-Hagmann, *Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany)
Page	pp. 658 - 663
Detailed information (abstract, keywords, etc)

Session 7D Novel Synthesis Techniques for Quantum Circuits
Time: 10:30 - 11:45 Thursday, January 25, 2018
Location: Room 402B
Chairs: Kyu-Myung Choi (Seoul National Univ., Republic of Korea), Sangdo Park (Samsung Electronics, Republic of Korea)

7D-1 (Time: 10:30 - 10:55)

Title	A Best-Fit Mapping Algorithm to Facilitate ESOP-Decomposition in Clifford+T Quantum Network Synthesis
Author	*Giulia Meuli, Mathias Soeken (EPFL, Switzerland), Martin Roetteler, Nathan Wiebe (Microsoft Research, U.S.A.), Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 664 - 669
Detailed information (abstract, keywords, etc)

7D-2 (Time: 10:55 - 11:20)

Title	Exploiting Coding Techniques for Logic Synthesis of Reversible Circuits
Author	*Alwin Zulehner, Robert Wille (Johannes Kepler Univ. Linz, Austria)
Page	pp. 670 - 675
Detailed information (abstract, keywords, etc)

7D-3 (Time: 11:20 - 11:45)

Title	Functional Decomposition Using Majority
Author	*Zhufei Chu (Ningbo Univ., China), Mathias Soeken (EPFL, Switzerland), Yinshui Xia (Ningbo Univ., China), Giovanni De Micheli (EPFL, Switzerland)
Page	pp. 676 - 681
Detailed information (abstract, keywords, etc)

Session 8A Energy Efficient System Design
Time: 13:15 - 14:30 Thursday, January 25, 2018
Location: Room 302
Chairs: Jae-Joon Kim (POSTECH, Republic of Korea), Jaeyong Chung (Incheon National Univ., Republic of Korea)

8A-1 (Time: 13:15 - 13:40)

Title	CANNA: Neural Network Acceleration using Conﬁgurable Approximation on GPGPU
Author	Mohsen Imani, Max Masich, *Daniel Peroni, Pushen Wang, Tajana Rosing (Univ. of California, San Diego, U.S.A.)
Page	pp. 682 - 689
Detailed information (abstract, keywords, etc)

8A-2 (Time: 13:40 - 14:05)

Title	Task Assignment and Scheduling in MPSoC under Process Variation: A Stochastic Approach
Author	*Behnam Khodabandeloo, Ahmad Khonsari (Univ. of Tehran/Institute for Research in Fundamental Sciences, Iran), Alireza Majidi (Texas A&M Univ., U.S.A.), Mohammad Hassan Hajiesmaili (Univ. of Tehran/Institute for Research in Fundamental Sciences, Iran)
Page	pp. 690 - 695
Detailed information (abstract, keywords, etc)

8A-3 (Time: 14:05 - 14:30)

Title	DarkMem: Fine-Grained Power Management of Local Memories for Accelerators in Embedded Systems
Author	*Christian Pilato (Univ. della Svizzera italiana (USI), Switzerland), Luca P. Carloni (Columbia Univ., U.S.A.)
Page	pp. 696 - 701
Detailed information (abstract, keywords, etc)

Session 9A Hardware Security Primitive Design and Implementation
Time: 15:00 - 16:15 Thursday, January 25, 2018
Location: Room 302
Chairs: Wujie Wen (Florida International Univ., U.S.A.), Taewhan Kim (Seoul National Univ., Republic of Korea)

9A-1 (Time: 15:00 - 15:25)

Title	CryptoBlaze: A Partially Homomorphic Processor with Multiple Instructions and Non-Deterministic Encryption Support
Author	*Florencia Irena, Daniel Murphy, Sri Parameswaran (Univ. of New South Wales, Australia)
Page	pp. 702 - 708
Detailed information (abstract, keywords, etc)

9A-2 (Time: 15:25 - 15:50)

Title	PMU-Trojan: On Exploiting Power Management Side Channel for Information Leakage
Author	*Md Nazmul Islam, Sandip Kundu (Univ. of Massachusetts Amherst, U.S.A.)
Page	pp. 709 - 714
Detailed information (abstract, keywords, etc)

9A-3 (Time: 15:50 - 16:15)

Title	A Low-overhead PUF based on Parallel Scan Design
Author	*Wenxuan Wang, Aijiao Cui (Harbin Inst. of Tech. Shenzhen Graduate School, China), Gang Qu (Univ. of Maryland, U.S.A.), Huawei Li (Chinese Academy of Sciences, China)
Page	pp. 715 - 720
Detailed information (abstract, keywords, etc)

Session 10A Deep Learning and Architectural Security
Time: 16:45 - 18:00 Thursday, January 25, 2018
Location: Room 302
Chairs: Taewhan Kim (Seoul National Univ., Republic of Korea), Ji-Hoon Kim (Seoul National Univ. of Science and Tech., Republic of Korea)

Best Paper Candidate
10A-1 (Time: 16:45 - 17:10)

Title	Security Analysis and Enhancement of Model Compressed Deep Learning Systems under Adversarial Attacks
Author	Qi Liu, Tao Liu, Zihao Liu (Florida International Univ., U.S.A.), Yanzhi Wang (Syracuse Univ., U.S.A.), Yier Jin (Univ. of Florida, U.S.A.), *Wujie Wen (Florida International Univ., U.S.A.)
Page	pp. 721 - 726
Detailed information (abstract, keywords, etc)

10A-2 (Time: 17:10 - 17:35)

Title	HLIFT: A High-level Information Flow Tracking Method for Detecting Hardware Trojans
Author	*Chenguang Wang, Yici Cai, Qiang Zhou (Tsinghua Univ., China)
Page	pp. 727 - 732
Detailed information (abstract, keywords, etc)

10A-3 (Time: 17:35 - 18:00)

Title	System-on-Chip Security Architecture and CAD Framework for Hardware Patch
Author	*Atul Prasad Deb Nath (Univ. of Florida, U.S.A.), Sandip Ray (NXP Semiconductors, U.S.A.), Abhishek Basak (Intel, U.S.A.), Swarup Bhunia (Univ. of Florida, U.S.A.)
Page	pp. 733 - 738
Detailed information (abstract, keywords, etc)

The 23rd Asia and South Pacific Design Automation Conference Technical Program

Session Schedule

List of papers

The 23rd Asia and South Pacific Design Automation Conference
Technical Program