The 21st Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract

Author Index: HERE

Session Schedule

Tuesday, January 26, 2016

TF4303	TF4203	TF4304	TF4204
1K (TF Theatre) Opening & Keynote I 8:30 - 10:00
1S University Design Contest 10:20 - 12:00	1A The Optimization of Memory Architecture and Management 10:20 - 12:00	1B Secure Embedded Systems & IoT 10:20 - 12:00	1C Design for Directed Self-Assembly 10:20 - 12:00
2S (Special Session) Designing with Spintronics: Recent Developments and Upcoming Challenges 13:50 - 15:30	2A Advances in Verification 13:50 - 15:30	2B System Simulation and Testing 13:50 - 15:30	2C Advanced Issues in Floorplanning and Placement 13:50 - 15:30
3S (Special Session) High-Level Synthesis – Now, the Future, and the "Dark Secrets" 15:50 - 17:30	3A Robust Timing Analysis and Optimization 15:50 - 17:30	3B Low Power in Deep Sub-Micro: From Architecture to Physical Design 15:50 - 17:30	3C Emerging Devices for Energy Efficient Computing 15:50 - 17:30

Wednesday, January 27, 2016

TF4303	TF4203	TF4304	TF4204
2K (TF Theatre) Keynote II 9:00 - 10:00
4S (Special Session) Design Challenges for Energy-Efficient IoT Edge Devices 10:20 - 12:00	4A Taking Advantages of Uncertainty in System Optimization 10:20 - 12:00	4B Security and Reliability in Emerging Devices 10:20 - 12:00	4C Routing 10:20 - 12:00
5S (Special Session) Cross-Layer Resilience: Snapshots from the Frontier of Design 13:50 - 15:55	5A (Special Session) Design Automation of Energy-Efficient Smart Buildings and Smart Cars 13:50 - 15:55	5B Advanced Embedded Software Techniques: Sensing, Computation, and Storage 13:50 - 15:55	5C Advances in Logic Synthesis 13:50 - 15:55

Thursday, January 28, 2016

TF4303	TF4203	TF4304	TF4204
3K (TF Theatre) Keynote III 8:30 - 10:00
6S (Special Session) Cyber-Physical Systems and Security 10:20 - 12:00	6A Testing, Modeling and Optimization Techniques for Analog Circuits 10:20 - 12:00	6B Energy-Efficient & Customized Computing 10:20 - 12:00	6C Design Methodologies for Microfluidic Biochips 10:20 - 12:00
7S (Special Session) New Frontiers of Physical Design 13:50 - 15:30	7A System-Level Design for Energy-Efficiency and Reliability 13:50 - 15:30	7B Design for Trustworthy IC 13:50 - 15:30	7C Design for Reliability 13:50 - 15:30
8S (Special Session) Reliability, Adaptability and Flexibility in Timing 15:50 - 17:30	8A Emerging Networks-on-Chip Designs 15:50 - 17:30	8B Test and Debug 15:50 - 17:30	8C Emerging Devices and Systems for Cyber-Physical Applications 15:50 - 17:30

List of papers

Remark: The presenter of each paper is marked with "*".

Tuesday, January 26, 2016

Session 1K Opening & Keynote I
Time: 8:30 - 10:00 Tuesday, January 26, 2016
Location: TF Theatre
Chair: Rui Martins (Univ. of Macau, Macau)

1K-1 (Time: 9:00 - 10:00)

Title	(Keynote Address) The Next Decade
Author	*Alessandro Cremonesi (STMicroelectronics, Italy)
Detailed information (abstract, keywords, etc)

Session 1S University Design Contest
Time: 10:20 - 12:00 Tuesday, January 26, 2016
Location: TF4303
Chairs: Man-Kay Law (Univ. of Macau, Macau), Yan Lu (Univ. of Macau, Macau)

1S-1 (Time: 10:20 - 10:28)

Title	An Automatic Place-and-Routed Two-Stage Fractional-N Injection-locked PLL Using Soft Injection
Author	*Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 1 - 2
Detailed information (abstract, keywords, etc)

1S-2 (Time: 10:28 - 10:36)

Title	Time-Domain I/Q-LOFT Compensator Using a Simple Envelope Detector for a Sub-GHz IEEE 802.11af WLAN Transmitter
Author	*Chak-Fong Cheang, Ka-Fai Un, Pui-In Mak, Rui Paulo da Silva Martins (Univ. of Macau, Macau)
Page	pp. 3 - 4
Detailed information (abstract, keywords, etc)

1S-3 (Time: 10:36 - 10:44)

Title	A Noise Reduction Technique for Divider-Less Fractional-N Frequency Synthesizer using Phase-Interpolation Technique
Author	*Aravind Tharayil Narayanan, Makihiko Katsuragi, Kengo Nakata, Yuki Terashima, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan)
Page	pp. 5 - 6
Detailed information (abstract, keywords, etc)

1S-4 (Time: 10:44 - 10:52)

Title	A 2.2 uW 15b Incremental Delta-Sigma ADC with Output-Driven Input Segmentation
Author	*Bo Wang (Hong Kong Univ. of Science and Tech., Hong Kong), Man-Kay Law (Macau Univ., Macau), Saqib Mohamad (Hong Kong Univ. of Science and Tech., Hong Kong), Amine Bermak (Hamad Bin Khalifa Univ., Qatar)
Page	pp. 7 - 8
Detailed information (abstract, keywords, etc)

1S-5 (Time: 10:52 - 11:00)

Title	A 200-MHz 4-Phase Fully Integrated Voltage Regulator With Local Ground Sensing Dual Loop ZDS Hysteretic Control Using 6.5nH Package Bondwire Inductors on 65nm Bulk CMOS
Author	Min Kyu Song, Joseph Sankman, Jayeol Lee, *Dongsheng Ma (Univ. of Texas, Dallas, U.S.A.)
Page	pp. 9 - 10
Detailed information (abstract, keywords, etc)

1S-6 (Time: 11:00 - 11:08)

Title	An AC Powered Converter-Free LED Driver with Low Flicker
Author	*Yuan Gao, Lisong Li, Philip K.T. Mok (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 11 - 12
Detailed information (abstract, keywords, etc)

1S-7 (Time: 11:08 - 11:16)

Title	A Variable-Voltage Low-Power Technique for Digital Circuit System
Author	*An-Tai Xiao, Yung-Siang Miao (National Chiao Tung Univ., Taiwan), Ching-Hwa Cheng (Feng Chia Univ., Taiwan), Jiun-In Guo (National Chiao Tung Univ., Taiwan)
Page	pp. 13 - 14
Detailed information (abstract, keywords, etc)

1S-8 (Time: 11:16 - 11:24)

Title	Sub-threshold VLSI Logic Family Exploiting Unbalanced Pull-up/down Network, Logical Effort and Inverse-Narrow-Width Techniques
Author	*Ming-Zhong Li, Chio-In Ieong, Man-Kay Law, Pui-In Mak, Mang-I Vai, Sio-Hang Pun, Rui P. Martins (Univ. of Macau, Macau)
Page	pp. 15 - 16
Detailed information (abstract, keywords, etc)

1S-9 (Time: 11:24 - 11:32)

Title	A Testable and Debuggable Dual-Core System with Thermal-Aware Dynamic Voltage and Frequency Scaling
Author	Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, *Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin (National Cheng Kung Univ., Taiwan)
Page	pp. 17 - 18
Detailed information (abstract, keywords, etc)

1S-10 (Time: 11:32 - 11:40)

Title	Rapid Prototyping of Multi-Mode QC-LDPC Decoder for 802.11n/ac Standard
Author	*Qing Lu, Bruce C. W. Sham, Francis C. M. Lau (Hong Kong Polytechnic Univ., Hong Kong)
Page	pp. 19 - 20
Detailed information (abstract, keywords, etc)

1S-11 (Time: 11:40 - 11:48)

Title	Sub-µW QRS Detection Processor Using Quadratic Spline Wavelet Transform and Maxima Modulus Pair Recognition for Power-Efficient Wireless Arrhythmia Monitoring
Author	*Chio-In Ieong, Pui-In Mak, Mang-I Vai, Rui P. Martins (Univ. of Macau, Macau)
Page	pp. 21 - 22
Detailed information (abstract, keywords, etc)

1S-12 (Time: 11:48 - 11:56)

Title	Design of an Energy-Autonomous, Disposable, Supply-Sensing Biosensor Using Bio Fuel Cell and 0.23-V 0.25-µm Zero-V_th All-Digital CMOS Supply-Controlled Ring Oscillator with Inductive Transmitter
Author	*Kiichi Niitsu, Atsuki Kobayashi (Nagoya Univ., Japan), Yudai Ogawa, Matsuhiko Nishizawa (Tohoku Univ., Japan), Kazuo Nakazato (Nagoya Univ., Japan)
Page	pp. 23 - 24
Detailed information (abstract, keywords, etc)

Session 1A The Optimization of Memory Architecture and Management
Time: 10:20 - 12:00 Tuesday, January 26, 2016
Location: TF4203
Chairs: Yun Liang (Peking Univ., China, China), Swathi Gurumani (Advanced Digital Sciences Center, Singapore (UIUC-ASTAR center), Singapore)

1A-1 (Time: 10:20 - 10:45)

Title	Performance-centric Register File Design for GPUs using Racetrack Memory
Author	*Shuo Wang, Yun Liang, Chao Zhang, Xiaolong Xie, Guangyu Sun (Peking Univ., China), Yongpan Liu, Yu Wang (Tsinghua Univ., China), Xiuhong Li (Peking Univ., China)
Page	pp. 25 - 30
Detailed information (abstract, keywords, etc)

1A-2 (Time: 10:45 - 11:10)

Title	Improving Read Performance of STT-MRAM based Main Memories through Smash Read and Flexible Read
Author	Lei Jiang (Advanced Micro Devices, U.S.A.), Wujie Wen (Florida International Univ., U.S.A.), *Danghui Wang (Northwestern Polytechnical Univ., China), Lide Duan (Univ. of Texas, San Antonio, U.S.A.)
Page	pp. 31 - 36
Detailed information (abstract, keywords, etc)

1A-3 (Time: 11:10 - 11:35)

Title	STLAC: A Spatial and Temporal Locality-Aware Cache and Network-on-Chip Codesign for Tiled Many-core Systems
Author	*Mingyu Wang, Zhaolin Li (Tsinghua Univ., China)
Page	pp. 37 - 42
Detailed information (abstract, keywords, etc)

1A-4 (Time: 11:35 - 12:00)

Title	A Lightweight OpenMP4 Run-time for Embedded Systems
Author	Roberto E. Vargas, Sara Royuela, *Maria A. Serrano, Xavi Martorell, Eduardo Quiñones (Barcelona Supercomputing Center, Spain)
Page	pp. 43 - 49
Detailed information (abstract, keywords, etc)

Session 1B Secure Embedded Systems & IoT
Time: 10:20 - 12:00 Tuesday, January 26, 2016
Location: TF4304
Chairs: Qiaoyan Yu (Univ. of New Hampshire, U.S.A.), Swaroop Ghosh (Univ. of South Florida, U.S.A.)

1B-1 (Time: 10:20 - 10:45)

Title	Improving Tag Generation for Memory Data Authentication in Embedded Processor Systems
Author	Tao Liu, *Hui Guo, Sri Parameswaran (Univ. of New South Wales, Australia), X. Sharon Hu (Univ. of Notre Dame, U.S.A.)
Page	pp. 50 - 55
Detailed information (abstract, keywords, etc)

1B-2 (Time: 10:45 - 11:10)

Title	JTAG-Based Robust PCB Authentication for Protection Against Counterfeiting Attacks
Author	Andrew Hennessy, Yu Zheng (Case Western Reserve Univ., U.S.A.), *Swarup Bhunia (Univ. of Florida, U.S.A.)
Page	pp. 56 - 61
Detailed information (abstract, keywords, etc)

1B-3 (Time: 11:10 - 11:35)

Title	Maximizing Level of Confidence for Non-Equidistant Checkpointing
Author	*Dimitar Nikolov, Erik Larsson (Lund Univ., Sweden)
Page	pp. 62 - 68
Detailed information (abstract, keywords, etc)

1B-4 (Time: 11:35 - 12:00)

Title	A Mutual Auditing Framework to Protect IoT against Hardware Trojans
Author	Chen Liu, Patrick Cronin, *Chengmo Yang (Univ. of Delaware, U.S.A.)
Page	pp. 69 - 74
Detailed information (abstract, keywords, etc)

Session 1C Design for Directed Self-Assembly
Time: 10:20 - 12:00 Tuesday, January 26, 2016
Location: TF4204
Chairs: Bei Yu (Chinese Univ. of Hong Kong, Hong Kong), Tetsuaki Matsunawa (Toshiba, Japan)

1C-1 (Time: 10:20 - 10:45)

Title	Simultaneous Template Optimization and Mask Assignment for DSA with Multiple Patterning
Author	*Jian Kuang, Junjie Ye, Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong)
Page	pp. 75 - 82
Detailed information (abstract, keywords, etc)

1C-2 (Time: 10:45 - 11:10)

Title	Mask Optimization for Directed Self-Assembly Lithography: Inverse DSA and Inverse Lithography
Author	*Seongbo Shim, Youngsoo Shin (KAIST, Republic of Korea)
Page	pp. 83 - 88
Detailed information (abstract, keywords, etc)

1C-3 (Time: 11:10 - 11:35)

Title	Cut Redistribution with Directed Self-Assembly Templates for Advanced 1-D Gridded Layouts
Author	*Zhi-Wen Lin, Yao-Wen Chang (National Taiwan Univ., Taiwan)
Page	pp. 89 - 94
Detailed information (abstract, keywords, etc)

1C-4 (Time: 11:35 - 12:00)

Title	Contact Layer Decomposition To Enable DSA With Multi-patterning Technique For Standard Cell Based Layout
Author	Zigang Xiao, Chun-Xun Lin, *Martin D.F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Hongbo Zhang (Synopsys, U.S.A.)
Page	pp. 95 - 102
Detailed information (abstract, keywords, etc)

Session 2S (Special Session) Designing with Spintronics: Recent Developments and Upcoming Challenges
Time: 13:50 - 15:30 Tuesday, January 26, 2016
Location: TF4303
Organizer/Chair: Sachin S. Sapatnekar (Univ. of Minnesota, U.S.A.)

2S-1 (Time: 13:50 - 14:20)

Title	(Invited Paper) Logic and Memory Design using Spin-based Circuits
Author	*Zhaoxin Liang, Meghna Mankalale, Brandon Del Bel, Sachin S. Sapatnekar (Univ. of Minnesota, U.S.A.)
Page	pp. 103 - 108
Detailed information (abstract, keywords, etc)

2S-2 (Time: 14:20 - 14:50)

Title	(Invited Paper) Architecture Design with STT-RAM: Opportunities and Challenges
Author	Ping Chi, Shuangchen Li, Yuanqing Cheng (Univ. of California, Santa Barbara, U.S.A.), Yu Lu, Seung H. Kang (Qualcomm Incorporated, U.S.A.), *Yuan Xie (Univ. of California, Santa Barbara, U.S.A.)
Page	pp. 109 - 114
Detailed information (abstract, keywords, etc)

2S-3 (Time: 14:50 - 15:20)

Title	(Invited Paper) Prospects of Efficient Neural Computing with Arrays of Magneto-metallic Neurons and Synapses
Author	Abhronil Sengupta, Karthik Yogendra, Deliang Fan, *Kaushik Roy (Purdue Univ., U.S.A.)
Page	pp. 115 - 120
Detailed information (abstract, keywords, etc)

Session 2A Advances in Verification
Time: 13:50 - 15:30 Tuesday, January 26, 2016
Location: TF4203
Chairs: Jason C. Verley (Sandia National Labs, U.S.A.), Zuochang Ye (Tsinghua Univ., China)

2A-1 (Time: 13:50 - 14:15)

Title	Automatic Abstraction Refinement of TR for PDR
Author	Kuan Fan, *Ming-Jen Yang, Chung-Yang (Ric) Huang (National Taiwan Univ., Taiwan)
Page	pp. 121 - 126
Detailed information (abstract, keywords, etc)

2A-2 (Time: 14:15 - 14:40)

Title	A Complete Approach to Unreachable State Diagnosability via Property Directed Reachability
Author	*Ryan Berryhill, Andreas Veneris (Univ. of Toronto, Canada)
Page	pp. 127 - 132
Detailed information (abstract, keywords, etc)

2A-3 (Time: 14:40 - 15:05)

Title	Formally Analyzing Fault Tolerance in Datapath Designs using Equivalence Checking
Author	Payman Behnam (Univ. of Tehran, Iran), Bijan Alizadeh (Univ. of Tehran, and IPM, Iran), Sajjad Taheri (Univ. of Tehran, Iran), *Masahiro Fujita (Univ. of Tokyo, Japan)
Page	pp. 133 - 138
Detailed information (abstract, keywords, etc)

2A-4 (Time: 15:05 - 15:30)

Title	Coupling Reverse Engineering and SAT to Tackle NP-Complete Arithmetic Circuitry Verification in ~O(# of gates)
Author	*Yi Diao, Xing Wei (Easy-Logic Technology, Hong Kong), Tak.Kei Lam (Chinese Univ. of Hong Kong, Hong Kong), Yu.Liang Wu (Easy-Logic Technology, Hong Kong)
Page	pp. 139 - 146
Detailed information (abstract, keywords, etc)

Session 2B System Simulation and Testing
Time: 13:50 - 15:30 Tuesday, January 26, 2016
Location: TF4304
Chairs: Liang Shi (Chongqing Univ., China), Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong)

2B-1 (Time: 13:50 - 14:15)

Title	NVPsim： A Simulator for Architecture Explorations of Nonvolatile Processors
Author	Yizi Gu, *Yongpan Liu, Yiqun Wang, Hehe Li, Huazhong Yang (Tsinghua Univ., China)
Page	pp. 147 - 152
Detailed information (abstract, keywords, etc)

2B-2 (Time: 14:15 - 14:40)

Title	MCSSim: A Memory Channel Storage Simulator
Author	*Renhai Chen, Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Chia-Lin Yang (National Taiwan Univ., Taiwan), Tao Li (Univ. of Florida, U.S.A.)
Page	pp. 153 - 158
Detailed information (abstract, keywords, etc)

2B-3 (Time: 14:40 - 15:05)

Title	Trace-Based Context-Sensitive Timing Simulation Considering Execution Path Variations
Author	*Sebastian Ottlik, Jan Micha Borrmann, Sadik Asbach, Alexander Viehl (FZI Research Center for Information Technology, Germany), Wolfgang Rosenstiel, Oliver Bringmann (Univ. of Tübingen, Germany)
Page	pp. 159 - 165
Detailed information (abstract, keywords, etc)

2B-4 (Time: 15:05 - 15:30)

Title	Generating High Coverage Tests for SystemC Designs Using Symbolic Execution
Author	*Bin Lin, Zhenkun Yang, Kai Cong, Fei Xie (Portland State Univ., U.S.A.)
Page	pp. 166 - 171
Detailed information (abstract, keywords, etc)

Session 2C Advanced Issues in Floorplanning and Placement
Time: 13:50 - 15:30 Tuesday, January 26, 2016
Location: TF4204
Chairs: Sheqin Dong (Tsinghua Univ., China), Yukihide Kohira (Univ. of Aizu, Japan)

2C-1 (Time: 13:50 - 14:15)

Title	Circular-Contour-Based Obstacle-Aware Macro Placement
Author	*Chien-Hsiung Chiou, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang (National Taiwan Univ., Taiwan)
Page	pp. 172 - 177
Detailed information (abstract, keywords, etc)

2C-2 (Time: 14:15 - 14:40)

Title	Learning-Based Prediction of Embedded Memory Timing Failures During Initial Floorplan Design
Author	Wei-Ting J. Chan (UC San Diego, U.S.A.), Kun Young Chung (Samsung Electronics, Republic of Korea), Andrew B. Kahng (UC San Diego, U.S.A.), Nancy D. MacDonald (ClariPhy Communications, U.S.A.), *Siddhartha Nath (UC San Diego, U.S.A.)
Page	pp. 178 - 185
Detailed information (abstract, keywords, etc)

2C-3 (Time: 14:40 - 15:05)

Title	Stitch Aware Detailed Placement for Multiple E-Beam Lithography
Author	Yibo Lin (Univ. of Texas, Austin, U.S.A.), *Bei Yu (Chinese Univ. of Hong Kong, Hong Kong), Yi Zou (Univ. of Texas, Austin, U.S.A.), Zhuo Li, Charles J. Alpert (Cadence Design Systems, U.S.A.), David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Page	pp. 186 - 191
Detailed information (abstract, keywords, etc)

2C-4 (Time: 15:05 - 15:30)

Title	Minimum Implant Area-Aware Placement and Threshold Voltage Refinement
Author	Seong-I Lei, *Wai Kei Mak (National Tsing Hua Univ., Taiwan), Chris Chu (Iowa State Univ., U.S.A.)
Page	pp. 192 - 197
Detailed information (abstract, keywords, etc)

Session 3S (Special Session) High-Level Synthesis – Now, the Future, and the "Dark Secrets"
Time: 15:50 - 17:30 Tuesday, January 26, 2016
Location: TF4303
Organizer: Deming Chen (UIUC, U.S.A.), Chair: Eric Yun Liang (Peking Univ., China)

3S-1 (Time: 15:50 - 16:15)

Title	(Invited Paper) Design and Verification Using High-Level Synthesis
Author	*Andres Takach (Mentor Graphics, U.S.A.)
Page	pp. 198 - 203
Detailed information (abstract, keywords, etc)

3S-2 (Time: 16:15 - 16:40)

Title	(Invited Paper) High-Level Synthesis of Accelerators in Embedded Scalable Platforms
Author	Paolo Mantovani, Giuseppe Di Guglielmo, *Luca P. Carloni (Columbia Univ., U.S.A.)
Page	pp. 204 - 211
Detailed information (abstract, keywords, etc)

3S-3 (Time: 16:40 - 17:05)

Title	(Invited Paper) High Quality IP Design using High-Level Synthesis Design Flow
Author	*Qiang Zhu (Cadence Design Systems, Japan), Masato Tatsuoka (Socionext, Japan)
Page	pp. 212 - 217
Detailed information (abstract, keywords, etc)

3S-4 (Time: 17:05 - 17:30)

Title	(Invited Paper) Designing High-Quality Hardware on a Development Effort Budget: A Study of the Current State of High-Level Synthesis
Author	Zelei Sun, Keith Campbell, Wei Zuo (UIUC, U.S.A.), Kyle Rupnow, Swathi Gurumani (ADSC, Singapore), Frederic Doucet (Qualcomm, U.S.A.), *Deming Chen (UIUC, U.S.A.)
Page	pp. 218 - 225
Detailed information (abstract, keywords, etc)

Session 3A Robust Timing Analysis and Optimization
Time: 15:50 - 17:30 Tuesday, January 26, 2016
Location: TF4203
Chairs: Ngai Wong (Univ. of Hong Kong, China), Hao Yu (Nanyang Technological Univ., Singapore)

3A-1 (Time: 15:50 - 16:15)

Title	Clock Buffer Polarity Assignment Utilizing Useful Clock Skews for Power Noise Reduction
Author	*Deokjin Joo, Taewhan Kim (Seoul National Univ., Republic of Korea)
Page	pp. 226 - 231
Detailed information (abstract, keywords, etc)

3A-2 (Time: 16:15 - 16:40)

Title	Buffer Insertion to Remove Hold Violations at Multiple Process Corners
Author	*Inhak Han, Daijoon Hyun, Youngsoo Shin (KAIST, Republic of Korea)
Page	pp. 232 - 237
Detailed information (abstract, keywords, etc)

3A-3 (Time: 16:40 - 17:05)

Title	Speed Binning With High-Quality Structural Patterns From Functional Timing Analysis (FTA)
Author	*Louis Y.-Z. Lin, Charles H.-P. Wen (National Chiao Tung Univ., Taiwan)
Page	pp. 238 - 243
Detailed information (abstract, keywords, etc)

3A-4 (Time: 17:05 - 17:30)

Title	Electromigration Recovery Modeling and Analysis under Time-Dependent Current and Temperature Stressing
Author	Xin Huang (Univ. of California, Riverside, U.S.A.), Valeriy Sukharev (Mentor Graphics, U.S.A.), Taeyoung Kim (Univ. of California, Riverside, U.S.A.), Haibao Chen (Shanghai Jiao Tong Univ., China), *Sheldon X.-D. Tan (Univ. of California, Riverside, U.S.A.)
Page	pp. 244 - 249
Detailed information (abstract, keywords, etc)

Session 3B Low Power in Deep Sub-Micro: From Architecture to Physical Design
Time: 15:50 - 17:30 Tuesday, January 26, 2016
Location: TF4304
Chairs: Takashi Sato (Kyoto Univ., Japan), Pingqiang Zhou (ShanghaiTech Univ., China)

3B-1 (Time: 15:50 - 16:15)

Title	A Novel Low-Cost Dynamic Logic Reconfigurable Structure Strategy for Low Power Optimization
Author	*Yu-Guang Chen, Wan-Yu Wen, Yun-Ting Wang, You-Luen Lee, Shih-Chieh Chang (National Tsing Hua Univ., Taiwan)
Page	pp. 250 - 255
Detailed information (abstract, keywords, etc)

3B-2 (Time: 16:15 - 16:40)

Title	An Energy-Efficient Random Number Generator for Stochastic Circuits
Author	*Kyounghoon Kim (Seoul National Univ., Republic of Korea), Jongeun Lee (UNIST, Republic of Korea), Kiyoung Choi (Seoul National Univ., Republic of Korea)
Page	pp. 256 - 261
Detailed information (abstract, keywords, etc)

3B-3 (Time: 16:40 - 17:05)

Title	Design of an All-Digital Temperature Sensor in 28 nm CMOS Using Temperature-Sensitive Delay Cells and Adaptive-1P Calibration for Error Reduction
Author	Shang-Yi Li, *Pei-Yuan Chou, Jinn-Shyan Wang (Chung-Cheng Univ., Taiwan)
Page	pp. 262 - 267
Detailed information (abstract, keywords, etc)

3B-4 (Time: 17:05 - 17:30)

Title	Design and Allocation of Loosely Coupled Multi-bit Flip-flops for Power Reduction in Post-Placement Optimization
Author	*Hyoungseok Moon, Taewhan Kim (Seoul National Univ., Republic of Korea)
Page	pp. 268 - 273
Detailed information (abstract, keywords, etc)

Session 3C Emerging Devices for Energy Efficient Computing
Time: 15:50 - 17:30 Tuesday, January 26, 2016
Location: TF4204
Chairs: Danghui Wang (Northwestern Polytechnical Univ., China), Jingtong Hu (Oklahoma State Univ., U.S.A.)

3C-1 (Time: 15:50 - 16:15)

Title	Thermal Optimization for Memristor-Based Hybrid Neuromorphic Computing Systems
Author	Chi-Ruo Wu (National Cheng Kung Univ., Taiwan), Wei Wen (Univ. of Pittsburgh, U.S.A.), *Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Yiran Chen (Univ. of Pittsburgh, U.S.A.)
Page	pp. 274 - 279
Detailed information (abstract, keywords, etc)

3C-2 (Time: 16:15 - 16:40)

Title	An Energy-efficient Matrix Multiplication Accelerator by Distributed In-memory Computing on Binary RRAM Crossbar
Author	*Leibin Ni, Yuhao Wang, Hao Yu (Nanyang Technological Univ., Singapore), Wei Yang, Chuliang Weng, Junfeng Zhao (Huawei Technologies, China)
Page	pp. 280 - 285
Detailed information (abstract, keywords, etc)

3C-3 (Time: 16:40 - 17:05)

Title	A Racetrack Memory Based In-memory Booth Multiplier for Cryptography Application
Author	*Tao Luo (Nanyang Technological Univ., Singapore), Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong), Bingsheng He, Douglas Maskell (Nanyang Technological Univ., Singapore)
Page	pp. 286 - 291
Detailed information (abstract, keywords, etc)

3C-4 (Time: 17:05 - 17:30)

Title	Look-ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits
Author	*Robert Wille (Johannes Kepler Univ. Linz, Austria), Oliver Keszocze (DFKI GmbH, Germany), Marcel Walter, Patrick Rohrs (Univ. of Bremen, Germany), Anupam Chattopadhyay (Nanyang Technological Univ., Singapore), Rolf Drechsler (Univ. of Bremen, Germany)
Page	pp. 292 - 297
Detailed information (abstract, keywords, etc)

Wednesday, January 27, 2016

Session 2K Keynote II
Time: 9:00 - 10:00 Wednesday, January 27, 2016
Location: TF Theatre
Chair: Pui-In Mak (Univ. of Macau, Macau)

2K-1 (Time: 9:00 - 10:00)

Title	(Keynote Address) Systems of Systems - The Next Frontier of Semiconductor
Author	*Qi Wang (Cadence Design Systems, U.S.A.)
Detailed information (abstract, keywords, etc)

Session 4S (Special Session) Design Challenges for Energy-Efficient IoT Edge Devices
Time: 10:20 - 12:00 Wednesday, January 27, 2016
Location: TF4303
Organizers/Chairs: Saibal Mukhopadhyay (Georgia Tech, U.S.A.), Vijay Raghunathan (Purdue Univ., U.S.A.)

4S-1 (Time: 10:20 - 10:45)

Title	(Invited Paper) Energy-Efficient System Design for IoT Devices
Author	Hrishikesh Jayakumar, Arnab Raha, Younghyun Kim, Soubhagya Sutar, Woo Suk Lee, *Vijay Raghunathan (Purdue Univ., U.S.A.)
Page	pp. 298 - 301
Detailed information (abstract, keywords, etc)

4S-2 (Time: 10:45 - 11:10)

Title	(Invited Paper) Energy Delivery for Self-Powered IoT Devices
Author	Khondker Z. Ahmed, Monodeep Kar, *Saibal Mukhopadhyay (Georgia Tech, U.S.A.)
Page	pp. 302 - 307
Detailed information (abstract, keywords, etc)

4S-3 (Time: 11:10 - 11:35)

Title	(Invited Paper) Efficient Embedded Learning for IoT Devices
Author	Swagath Venkataramani, Kaushik Roy, *Anand Raghunathan (Purdue Univ., U.S.A.)
Page	pp. 308 - 311
Detailed information (abstract, keywords, etc)

4S-4 (Time: 11:35 - 12:00)

Title	(Invited Paper) Computing with Coupled Spin Torque Nano Oscillators
Author	Karthik Yogendra (Purdue Univ., U.S.A.), Deliang Fan (Univerisity of Central Florida, U.S.A.), Yong Shim, Minsuk Koo, *Kaushik Roy (Purdue Univ., U.S.A.)
Page	pp. 312 - 317
Detailed information (abstract, keywords, etc)

Session 4A Taking Advantages of Uncertainty in System Optimization
Time: 10:20 - 12:00 Wednesday, January 27, 2016
Location: TF4203
Chairs: Ing-Jer Huang (National Sun Yat-sen Univ., Taiwan), Chun Jason Xue (City Univ. of Hong Kong, Hong Kong)

4A-1 (Time: 10:20 - 10:45)

Title	ApproxMap: On Task Allocation and Scheduling for Resilient Applications
Author	*Juan Yi (Chongqing Univ., China), Qian Zhang, Ye Tian, Ting Wang (Chinese Univ. of Hong Kong, China), Weichen Liu, Edwin H.-M. Sha (Chongqing Univ., China), Qiang Xu (Chinese Univ. of Hong Kong, China)
Page	pp. 318 - 323
Detailed information (abstract, keywords, etc)

4A-2 (Time: 10:45 - 11:10)

Title	Energy Optimization of Stochastic Applications with Statistical Guarantees of Deadline and Reliability
Author	*Xiong Pan, Wei Jiang (Univ. of Electronic Science and Tech. of China, China), Ke Jiang (Linköping Univ., Sweden), Liang Wen, Qi Dong (Univ. of Electronic Science and Tech. of China, China)
Page	pp. 324 - 329
Detailed information (abstract, keywords, etc)

4A-3 (Time: 11:10 - 11:35)

Title	SMoSi: A Framework for the Derivation of Sleep Mode Traces from RTL Simulations
Author	*Dustin Peterson, Oliver Bringmann (Univ. of Tübingen, Germany)
Page	pp. 330 - 335
Detailed information (abstract, keywords, etc)

4A-4 (Time: 11:35 - 12:00)

Title	Optimization of Behavioral IPs in Multi-Processor System-on-Chips
Author	Yidi Liu, *Benjamin Carrion Schafer (Hong Kong Polytechnic Univ., Hong Kong)
Page	pp. 336 - 341
Detailed information (abstract, keywords, etc)

Session 4B Security and Reliability in Emerging Devices
Time: 10:20 - 12:00 Wednesday, January 27, 2016
Location: TF4304
Chairs: Yier Jin (Univ. of Central Florida, U.S.A.), Swaroop Ghosh (Univ. of South Florida, U.S.A.)

4B-1 (Time: 10:20 - 10:45)

Title	A Novel PUF based on Cell Error Rate Distribution of STT-RAM
Author	*Xian Zhang, Guangyu Sun (Peking Univ., China), Yaojun Zhang, Yiran Chen, Hai Li (Univ. of Pittsburgh, U.S.A.), Wujie Wen (Florida International Univ., U.S.A.), Jia Di (Univ. of Arkansas, U.S.A.)
Page	pp. 342 - 347
Detailed information (abstract, keywords, etc)

4B-2 (Time: 10:45 - 11:10)

Title	Data Privacy in Non-Volatile Cache: Challenges, Attack Models and Solutions
Author	Nitin Rathi, *Swaroop Ghosh, Anirudh Iyengar (Univ. of South Florida, U.S.A.), Helia Naeimi (Intel Labs, U.S.A.)
Page	pp. 348 - 353
Detailed information (abstract, keywords, etc)

4B-3 (Time: 11:10 - 11:35)

Title	Pin Tumbler Lock: A Shift based Encryption Mechanism for Racetrack Memory
Author	*Hongbin Zhang (Tsinghua Univ., China), Chao Zhang, Xian Zhang, Guangyu Sun (Peking Univ., China), Jiwu Shu (Tsinghua Univ., China)
Page	pp. 354 - 359
Detailed information (abstract, keywords, etc)

4B-4 (Time: 11:35 - 12:00)

Title	Routing Path Reuse Maximization for Efficient NV-FPGA Reconfiguration
Author	Yuan Xue, Patrick Cronin, *Chengmo Yang (Univ. of Delaware, U.S.A.), Jingtong Hu (Oklahoma State Univ., U.S.A.)
Page	pp. 360 - 365
Detailed information (abstract, keywords, etc)

Session 4C Routing
Time: 10:20 - 12:00 Wednesday, January 27, 2016
Location: TF4204
Chairs: Iris Hui-Ru Jiang (National Chiao Tung Univ., Taiwan), Yao-Wen Chang (National Taiwan Univ., Taiwan)

4C-1 (Time: 10:20 - 10:45)

Title	MCMM Clock Tree Optimization based on Slack Redistribution Using a Reduced Slack Graph
Author	*Rickard Ewetz, Cheng-Kok Koh (Purdue Univ., U.S.A.)
Page	pp. 366 - 371
Detailed information (abstract, keywords, etc)

4C-2 (Time: 10:45 - 11:10)

Title	Dynamic Planning of Local Congestion from Varying-Size Vias for Global Routing Layer Assignment
Author	Daohang Shi, Edward Tashjian, *Azadeh Davoodi (Univ. of Wisconsin-Madison, U.S.A.)
Page	pp. 372 - 377
Detailed information (abstract, keywords, etc)

4C-3 (Time: 11:10 - 11:35)

Title	Negotiation-Based Track Assignment Considering Local Nets
Author	*Man-Pan Wong (National Tsing Hua Univ., Taiwan), Wen-Hao Liu (Cadence Design Systems, U.S.A.), Ting-Chi Wang (National Tsing Hua Univ., Taiwan)
Page	pp. 378 - 383
Detailed information (abstract, keywords, etc)

4C-4 (Time: 11:35 - 12:00)

Title	Ordered Escape Routing for Grid Pin Array Based on Min-cost Multi-commodity Flow
Author	*Fengxian Jiao, Sheqin Dong (Tsinghua Univ., China)
Page	pp. 384 - 389
Detailed information (abstract, keywords, etc)

Session 5S (Special Session) Cross-Layer Resilience: Snapshots from the Frontier of Design
Time: 13:50 - 15:55 Wednesday, January 27, 2016
Location: TF4303
Organizer: Ulf Schlichtmann (TUM, Germany), Chair: Jörg Henkel (KIT, Germany)

5S-1 (Time: 13:50 - 14:15)

Title	(Invited Paper) Efficient Reliability Management in SoCs – An Approximate DRAM Perspective
Author	Matthias Jung, Deepak M. Mathew, Christian Weis, *Norbert Wehn (Univ. of Kaiserslautern, Germany)
Page	pp. 390 - 394
Detailed information (abstract, keywords, etc)

5S-2 (Time: 14:15 - 14:40)

Title	(Invited Paper) Cross-layer Virtual/Physical Sensing and Actuation for Resilient Heterogeneous Many-core SoCs
Author	*Santanu Sarma, Tiago Mück, Majid Shoushtari, Abbas BanaiyanMofrad, Nikil Dutt (UC Irvine, U.S.A.)
Page	pp. 395 - 402
Detailed information (abstract, keywords, etc)

5S-3 (Time: 14:40 - 15:05)

Title	(Invited Paper) On-chip Monitoring and Compensation Scheme with Fine-grain Body Biasing for Robust and Energy-Efficient Operations
Author	A.K.M. Mahfuzul Islam (Univ. of Tokyo, Japan), *Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 403 - 409
Detailed information (abstract, keywords, etc)

5S-4 (Time: 15:05 - 15:30)

Title	(Invited Paper) Embedded Software Reliability Testing by Unit-Level Fault Injection
Author	Petra R. Maier, Daniel Mueller-Gritschneder, Ulf Schlichtmann (TU Munich, Germany), *Veit B. Kleeberger (Infineon Technologies, Germany)
Page	pp. 410 - 416
Detailed information (abstract, keywords, etc)

Session 5A (Special Session) Design Automation of Energy-Efficient Smart Buildings and Smart Cars
Time: 13:50 - 15:55 Wednesday, January 27, 2016
Location: TF4203
Organizer: Naehyuck Chang (KAIST, Republic of Korea), Chair: Tohru Ishihara (Kyoto Univ., Japan)

5A-1 (Time: 13:50 - 14:15)

Title	(Invited Paper) Thermal Modeling for Energy-Efficient Smart Building With Advanced Overfitting Mitigation Technique
Author	Wandi Liu, Hai Wang (Univ. of Electronic Science and Tech. of China, China), Hengyang Zhao, Shujuan Wang (Univ. of California, Riverside, U.S.A.), Haibao Chen, Yuzhuo Fu (Shanghai Jiaotong Univ., China), Jian Ma (Univ. of Electronic Science and Tech. of China, China), Xin Li (Carnegie Mellon Univ., U.S.A.), *Sheldon X.-D. Tan (Univ. of California, Riverside, U.S.A.)
Page	pp. 417 - 422
Detailed information (abstract, keywords, etc)

5A-2 (Time: 14:15 - 14:40)

Title	(Invited Paper) Modeling, Analysis, and Optimization of Electric Vehicle HVAC Systems
Author	*Mohammad Abdullah Al Faruque, Korosh Vatanparvar (UC Irvine, U.S.A.)
Page	pp. 423 - 428
Detailed information (abstract, keywords, etc)

5A-3 (Time: 14:40 - 15:05)

Title	(Invited Paper) Distributed Reconfigurable Battery System Management Architectures
Author	*Sebastian Steinhorst (TUM CREATE, Singapore), Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Samarjit Chakraborty (TU Munich, Germany), Matthias Kauer (TUM CREATE, Singapore), Shuai Li (Hong Kong Polytechnic Univ., Hong Kong), Martin Lukasiewycz, Swaminathan Narayanaswamy (TUM CREATE, Singapore), Muhammad Usman Rafique, Qixin Wang (Hong Kong Polytechnic Univ., Hong Kong)
Page	pp. 429 - 434
Detailed information (abstract, keywords, etc)

5A-4 (Time: 15:05 - 15:30)

Title	(Invited Paper) Minimum-Energy Driving Speed Profiles for Low-Speed Electric Vehicles
Author	Donkyu Baek, Joonki Hong, *Naehyuck Chang (KAIST, Republic of Korea)
Page	p. 435
Detailed information (abstract, keywords, etc)

Session 5B Advanced Embedded Software Techniques: Sensing, Computation, and Storage
Time: 13:50 - 15:55 Wednesday, January 27, 2016
Location: TF4304
Chairs: Zili Shao (Hong Kong Polytechnic Univ., China), Duo Liu (Chongqing Univ., China)

5B-1 (Time: 13:50 - 14:15)

Title	Multi-version Checkpointing for Flash File Systems
Author	*Shih-Chun Chou (National Taiwan Univ., Taiwan), Yuan-Hao Chang, Yuan-Hung Kuan (Academia Sinica, Taiwan), Po-Chun Huang (Yuan Ze Univ., Taiwan), Che-Wei Tsao (National Taiwan Univ., Taiwan)
Page	pp. 436 - 443
Detailed information (abstract, keywords, etc)

5B-2 (Time: 14:15 - 14:40)

Title	Relay-based Key Management to Support Secure Deletion for Resource-Constrained Flash-Memory Storage Devices
Author	Wei-Lin Wang (National Tsing Hua Univ., Taiwan), Yuan-Hao Chang (Academia Sinica, Taiwan), *Po-Chun Huang (Yuan Ze Univ., Taiwan), Chia-Heng Tu (Smart Network System Institute, Institute for Information Industry, Taiwan), Hsin-Wen Wei (Tamkang Univ., Taiwan), Wei-Kuan Shih (National Tsing Hua Univ., Taiwan)
Page	pp. 444 - 449
Detailed information (abstract, keywords, etc)

5B-3 (Time: 14:40 - 15:05)

Title	Peak-to-average Pumping Efficiency Improvement for Charge Pump in Phase Change Memories
Author	Huizhang Luo (Chongqing Univ., China), Jingtong Hu (Oklahoma State Univ., U.S.A.), *Liang Shi (Chongqing Univ., China), Chun Jason Xue (City Univ. of Hong Kong, Hong Kong), Qingfeng Zhuge (Chongqing Univ., China)
Page	pp. 450 - 455
Detailed information (abstract, keywords, etc)

5B-4 (Time: 15:05 - 15:30)

Title	Exploiting Parallelism of Imperfect Nested Loops with Sibling Inner Loops on Coarse-Grained Reconfigurable Architectures
Author	*Xinhan Lin, Shouyi Yin, Leibo Liu, Shaojun Wei (Tsinghua Univ., China)
Page	pp. 456 - 461
Detailed information (abstract, keywords, etc)

5B-5 (Time: 15:30 - 15:55)

Title	SlowMo – Enhancing Mobile Gesture-Based Authentication Schemes via Sampling Rate Optimization
Author	*Kent W. Nixon, Xiang Chen, Zhi-Hong Mao, Yiran Chen (Univ. of Pittsburgh, U.S.A.)
Page	pp. 462 - 467
Detailed information (abstract, keywords, etc)

Session 5C Advances in Logic Synthesis
Time: 13:50 - 15:55 Wednesday, January 27, 2016
Location: TF4204
Chairs: Benjamin Carrion Schafer (Hong Kong Polytechnic Univ., Hong Kong), Kai-Chiang Wu (National Chiao Tung Univ., Taiwan)

5C-1 (Time: 13:50 - 14:15)

Title	Lattice-Based Boolean Diagrams: Canonical, Order-Independent Graphical Representations of Boolean Functions
Author	Ahmed Nassar, *Fadi J. Kurdahi (Univ. of California, Irvine, U.S.A.)
Page	pp. 468 - 473
Detailed information (abstract, keywords, etc)

5C-2 (Time: 14:15 - 14:40)

Title	BDD Minimization for Approximate Computing
Author	*Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler (Univ. of Bremen, Germany)
Page	pp. 474 - 479
Detailed information (abstract, keywords, etc)

5C-3 (Time: 14:40 - 15:05)

Title	MajorSat: A SAT Solver to Majority Logic
Author	Yu-Min Chou (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (Yuan Ze Univ., Taiwan), Chun-Yao Wang, *Ching-Yi Huang (National Tsing Hua Univ., Taiwan)
Page	pp. 480 - 485
Detailed information (abstract, keywords, etc)

5C-4 (Time: 15:05 - 15:30)

Title	Fast Synthesis of Threshold Logic Networks with Optimization
Author	*Yung-Chih Chen, Runyi Wang, Yan-Ping Chang (Yuan Ze Univ., Taiwan)
Page	pp. 486 - 491
Detailed information (abstract, keywords, etc)

5C-5 (Time: 15:30 - 15:55)

Title	Polysynchronous Stochastic Circuits
Author	*M. Hassan Najafi, David J. Lilja, Marc Riedel, Kia Bazargan (Univ. of Minnesota, U.S.A.)
Page	pp. 492 - 498
Detailed information (abstract, keywords, etc)

Thursday, January 28, 2016

Session 3K Keynote III
Time: 8:30 - 10:00 Thursday, January 28, 2016
Location: TF Theatre
Chair: David Pan (Univ. of Texas, Austin, U.S.A.)

3K-1 (Time: 8:30 - 9:00)

Title	(Keynote Address) Majority-based Synthesis for Nanotechnologies
Author	Luca Amaru, Pierre-Emmanuel Gaillardon, *Giovanni De Micheli (Integrated Systems Laboratory, EPFL, Switzerland)
Page	pp. 499 - 502
Detailed information (abstract, keywords, etc)

3K-2 (Time: 9:00 - 9:30)

Title	(Keynote Address) A Scalable Communication-Aware Compilation Flow for Programmable Accelerators
Author	*Jason Cong, Hui Huang, Mohammad Ali Ghodrat (UCLA, U.S.A.)
Page	pp. 503 - 510
Detailed information (abstract, keywords, etc)

3K-3 (Time: 9:30 - 10:00)

Title	(Keynote Address) Software and System Co-optimization in the era of Heterogeneous Computing
Author	*Michael Gschwind (IBM, U.S.A.)
Detailed information (abstract, keywords, etc)

Session 6S (Special Session) Cyber-Physical Systems and Security
Time: 10:20 - 12:00 Thursday, January 28, 2016
Location: TF4303
Organizer/Chair: Jeyavijayan Rajendran (Univ. of Texas, Dallas, U.S.A.), Farinaz Koushanfar (Rice Univ., U.S.A.)

6S-1 (Time: 10:20 - 10:45)

Title	(Invited Paper) Enabling Multi-Layer Cyber-Security Assessment of Industrial Control Systems through Hardware-in-the-Loop Testbeds
Author	Anastasis Keliris, Charalambos Konstantinou, Nektarios Georgios Tsoutsos (New York Univ., U.S.A.), Raghad Baiad, *Michail Maniatakos (New York Univ. Abu Dhabi, United Arab Emirates)
Page	pp. 511 - 518
Detailed information (abstract, keywords, etc)

6S-2 (Time: 10:45 - 11:10)

Title	(Invited Paper) Security Analysis on Consumer and Industrial IoT Devices
Author	Jacob Wurm, Khoa Hoang, Orlando Arias (Univ. of Central Florida, U.S.A.), Ahmad-Reza Sadeghi (TU Darmstadt, Germany), *Yier Jin (Univ. of Central Florida, U.S.A.)
Page	pp. 519 - 524
Detailed information (abstract, keywords, etc)

6S-3 (Time: 11:10 - 11:35)

Title	(Invited Paper) Covert Channels Using Mobile Device’s Magnetic Field Sensors
Author	Nikolay Matyunin (Tech. Univ. Darmstadt, Germany), *Jakub Szefer (Yale Univ., U.S.A.), Sebastian Biedermann, Stefan Katzenbeisser (Tech. Univ. Darmstadt, Germany)
Page	pp. 525 - 532
Detailed information (abstract, keywords, etc)

6S-4 (Time: 11:35 - 12:00)

Title	(Invited Paper) Multi-valued Arbiters for Quality Enhancement of PUF Responses on FPGA Implementation
Author	*Siarhei S. Zalivaka (Nanyang Technological Univ., Singapore), Alexander V. Puchkov, Vladimir P. Klybik, Alexander A. Ivaniuk (Belarusian State Univ. of Informatics and Radioelectronics, Belarus), Chip-Hong Chang (Nanyang Technological Univ., Singapore)
Page	pp. 533 - 538
Detailed information (abstract, keywords, etc)

Session 6A Testing, Modeling and Optimization Techniques for Analog Circuits
Time: 10:20 - 12:00 Thursday, January 28, 2016
Location: TF4203
Chairs: Sheldon Tan (Univ. of California, Riverside, U.S.A.), Mark Po-Hung LIN (National Chung Cheng Univ., Taiwan)

6A-1 (Time: 10:20 - 10:45)

Title	Every Test Makes a Difference: Compressing Analog Tests to Decrease Production Costs
Author	Seyed Nematollah Ahmadyan (Univ. of Illinois, Urbana-Champaign, U.S.A.), Suriyaprakash Natarajan (Intel, U.S.A.), *Shobha Vasudevan (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Page	pp. 539 - 544
Detailed information (abstract, keywords, etc)

6A-2 (Time: 10:45 - 11:10)

Title	Re-thinking Polynomial Optimization: Efficient Programming of Reconfigurable Radio Frequency (RF) Systems by Convexification
Author	Fa Wang, Shihui Yin, Minhee Jun, *Xin Li, Tamal Mukherjee, Rohit Negi, Larry Pileggi (Carnegie Mellon Univ., U.S.A.)
Page	pp. 545 - 550
Detailed information (abstract, keywords, etc)

6A-3 (Time: 11:10 - 11:35)

Title	An Efficient Trajectory-based Algorithm for Model Order Reduction of Nonlinear Systems via Localized Projection and Global Interpolation
Author	Chenjie Yang, *Fan Yang, Xuan Zeng (Fudan Univ., China), Dian Zhou (Univ. of Texas, Dallas, China)
Page	pp. 551 - 556
Detailed information (abstract, keywords, etc)

6A-4 (Time: 11:35 - 12:00)

Title	STORM: A Nonlinear Model Order Reduction Method via Symmetric Tensor Decomposition
Author	Jian Deng, Haotian Liu, Kim Batselier, Yu-Kwong Kwok, *Ngai Wong (Univ. of Hong Kong, Hong Kong)
Page	pp. 557 - 562
Detailed information (abstract, keywords, etc)

Session 6B Energy-Efficient & Customized Computing
Time: 10:20 - 12:00 Thursday, January 28, 2016
Location: TF4304
Chairs: Weichen Liu (Chongqing Univ., China), Yaoyao Ye (Shanghai Jiao Tong Univ., China)

6B-1 (Time: 10:20 - 10:45)

Title	Footfall – GPS Polling Scheduler for Power Saving on Wearable Devices
Author	*Kent W. Nixon, Xiang Chen, Yiran Chen (Univ. of Pittsburgh, U.S.A.)
Page	pp. 563 - 568
Detailed information (abstract, keywords, etc)

6B-2 (Time: 10:45 - 11:10)

Title	CP-FPGA: Computation Data-Aware Software/Hardware Co-design for Nonvolatile FPGAs based on Checkpointing Techniques
Author	*Zhe Yuan, Yongpan Liu, Hehe Li, Huazhong Yang (Tsinghua Univ., China)
Page	pp. 569 - 574
Detailed information (abstract, keywords, etc)

6B-3 (Time: 11:10 - 11:35)

Title	Design Space Exploration of FPGA-Based Deep Convolutional Neural Networks
Author	Mohammad Motamedi, *Philipp Gysel, Venkatesh Akella, Soheil Ghiasi (Univ. of California, Davis, U.S.A.)
Page	pp. 575 - 580
Detailed information (abstract, keywords, etc)

6B-4 (Time: 11:35 - 12:00)

Title	LRADNN: High-Throughput and Energy-Efficient Deep Neural Network Accelerator using Low Rank Approximation
Author	*Jingyang Zhu (Hong Kong Univ. of Science and Tech., Hong Kong), Zhiliang Qian (Shanghai Jiao Tong Univ., China), Chi-Ying Tsui (Hong Kong Univ. of Science and Tech., Hong Kong)
Page	pp. 581 - 586
Detailed information (abstract, keywords, etc)

Session 6C Design Methodologies for Microfluidic Biochips
Time: 10:20 - 12:00 Thursday, January 28, 2016
Location: TF4204
Chairs: Hailong Yao (Tsinghua Univ., China), Tohru Ishihara (Kyoto Univ., Japan)

6C-1 (Time: 10:20 - 10:45)

Title	Sequence-Pair-Based Placement and Routing for Flow-Based Microfluidic Biochips
Author	*Qin Wang, Yizhong Ru, Hailong Yao (Tsinghua Univ., China), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Yici Cai (Tsinghua Univ., China)
Page	pp. 587 - 592
Detailed information (abstract, keywords, etc)

6C-2 (Time: 10:45 - 11:10)

Title	Congestion- and Timing-Driven Droplet Routing for Pin-Constrained Paper-Based Microfluidic Biochips
Author	*Jain-De Li, Sying-Jyan Wang (National Chung Hsing Univ., Taiwan), Katherine Shu-Min Li (National Sun Yat-sen Univ., Taiwan), Tsung-Yi Ho (National Tsing Hua Univ., Taiwan)
Page	pp. 593 - 598
Detailed information (abstract, keywords, etc)

6C-3 (Time: 11:10 - 11:35)

Title	Chain-Based Pin Count Minimization for General-Purpose Digital Microfluidic Biochips
Author	*Yung-Chun Lei, Chen-Shing Hsu, Juinn-Dar Huang (National Chiao Tung Univ., Taiwan), Jing-Yang Jou (National Central Univ., Taiwan)
Page	pp. 599 - 604
Detailed information (abstract, keywords, etc)

6C-4 (Time: 11:35 - 12:00)

Title	A Routability-Driven Flow Routing Algorithm for Programmable Microfluidic Devices
Author	Yi-Siang Su (National Taiwan Univ., Taiwan), *Tsung-Yi Ho (National Tsing Hua Univ., Taiwan), Der-Tsai Lee (National Taiwan Univ., Taiwan)
Page	pp. 605 - 610
Detailed information (abstract, keywords, etc)

Session 7S (Special Session) New Frontiers of Physical Design
Time: 13:50 - 15:30 Thursday, January 28, 2016
Location: TF4303
Organizer: Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong), Chair: Bei Yu (Chinese Univ. of Hong Kong, Hong Kong)

7S-1 (Time: 13:50 - 14:20)

Title	(Invited Paper) Advanced Multi-Patterning and Hybrid Lithography Techniques
Author	*Fedor G. Pikus, Andres Torres (Mentor Graphics, U.S.A.)
Page	pp. 611 - 616
Detailed information (abstract, keywords, etc)

7S-2 (Time: 14:20 - 14:50)

Title	(Invited Paper) Recent Research Development and New Challenges in Analog Layout Synthesis
Author	*Mark Po-Hung Lin (National Chung Cheng Univ., Taiwan), Yao-Wen Chang (National Taiwan Univ., Taiwan), Chih-Ming Hung (MediaTek, Taiwan)
Page	pp. 617 - 622
Detailed information (abstract, keywords, etc)

7S-3 (Time: 14:50 - 15:20)

Title	(Invited Paper) To Detect, Locate, and Mask Hardware Trojans in Digital Circuits by Reverse Engineering and Functional ECO
Author	*Xing Wei, Yi Diao, Yu-Liang Wu (Easy-Logic Technology, Hong Kong)
Page	pp. 623 - 630
Detailed information (abstract, keywords, etc)

Session 7A System-Level Design for Energy-Efficiency and Reliability
Time: 13:50 - 15:30 Thursday, January 28, 2016
Location: TF4203
Chairs: Guihai Yan (Chinese Academy of Sciences, China), Donghwa Shin (Yeungnam Univ., Republic of Korea)

7A-1 (Time: 13:50 - 14:15)

Title	Aging-aware High-level Physical Planning for Reconfigurable Systems
Author	Zana Ghaderi, *Eli Bozorgzadeh (Univ. of California, Irvine, U.S.A.)
Page	pp. 631 - 636
Detailed information (abstract, keywords, etc)

7A-2 (Time: 14:15 - 14:40)

Title	Hardware Reliability Margining for the Dark Silicon Era
Author	Liangzhen Lai, *Puneet Gupta (UCLA, U.S.A.)
Page	pp. 637 - 642
Detailed information (abstract, keywords, etc)

7A-3 (Time: 14:40 - 15:05)

Title	ACR: Enabling Computation Reuse for Approximate Computing
Author	*Xin He, Guihai Yan, Yinhe Han, Xiaowei Li (Chinese Academy of Sciences, China)
Page	pp. 643 - 648
Detailed information (abstract, keywords, etc)

7A-4 (Time: 15:05 - 15:30)

Title	Work hard, sleep well - Avoid irreversible IC wearout with proactive rejuvenation
Author	*Xinfei Guo, Mircea R. Stan (Univ. of Virginia, U.S.A.)
Page	pp. 649 - 654
Detailed information (abstract, keywords, etc)

Session 7B Design for Trustworthy IC
Time: 13:50 - 15:30 Thursday, January 28, 2016
Location: TF4304
Chairs: Yu Wang (Tsinghua Univ., China), Jeyavijayan Rajendran (Univ. of Texas, Dallas, U.S.A.)

7B-1 (Time: 13:50 - 14:15)

Title	Netlist Reverse Engineering for High-Level Functionality Reconstruction
Author	*Travis Meade, Shaojie Zhang, Yier Jin (Univ. of Central Florida, U.S.A.)
Page	pp. 655 - 660
Detailed information (abstract, keywords, etc)

7B-2 (Time: 14:15 - 14:40)

Title	Assessing CPA Resistance of AES with Different Fault Tolerance Mechanisms
Author	Hoda Pahlevanzadeh, Jaya Dofe, *Qiaoyan Yu (Univ. of New Hampshire, U.S.A.)
Page	pp. 661 - 666
Detailed information (abstract, keywords, etc)

7B-3 (Time: 14:40 - 15:05)

Title	SPARTA: A Scheduling Policy for Thwarting Differential Power Analysis Attacks
Author	*Ke Jiang, Petru Eles, Zebo Peng, Sudipta Chattopadhyay (Linköping Univ., Sweden), Lejla Batina (Radboud Univ., Netherlands)
Page	pp. 667 - 672
Detailed information (abstract, keywords, etc)

7B-4 (Time: 15:05 - 15:30)

Title	Analysis and Vulnerability Exploration of Current Secure Scan Designs
Author	Yanhui Luo, *Aijiao Cui (Harbin Inst. of Tech. Shenzhen Graduate School, China), Huawei Li (Chinese Academy of Sciences, China), Gang Qu (Univ. of Maryland College Park, U.S.A.)
Page	pp. 673 - 678
Detailed information (abstract, keywords, etc)

Session 7C Design for Reliability
Time: 13:50 - 15:30 Thursday, January 28, 2016
Location: TF4204
Chairs: Martin Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), Evangeline F.Y. Young (Chinese Univ. of Hong Kong, Hong Kong)

7C-1 (Time: 13:50 - 14:15)

Title	Laplacian Eigenmaps and Bayesian Clustering Based Layout Pattern Sampling and Its Applications to Hotspot Detection and OPC
Author	*Tetsuaki Matsunawa (Toshiba, Japan), Bei Yu (Chinese Univ. of Hong Kong, Hong Kong), David Z. Pan (Univ. of Texas, Austin, U.S.A.)
Page	pp. 679 - 684
Detailed information (abstract, keywords, etc)

7C-2 (Time: 14:15 - 14:40)

Title	Balancing Lifetime and Soft-Error Reliability to Improve System Availability
Author	*Junlong Zhou (Univ. of Notre Dame, East China Normal Univ., U.S.A.), X. Sharon Hu, Yue Ma (Univ. of Notre Dame, U.S.A.), Tongquan Wei (East China Normal Univ., China)
Page	pp. 685 - 690
Detailed information (abstract, keywords, etc)

7C-3 (Time: 14:40 - 15:05)

Title	A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region
Author	*Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ., Japan)
Page	pp. 691 - 696
Detailed information (abstract, keywords, etc)

7C-4 (Time: 15:05 - 15:30)

Title	Delay Uncertainty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products
Author	Samyoung Bang (Samsung Electronics, Republic of Korea), Kwangsoo Han, Andrew B. Kahng, *Mulong Luo (Univ. of California, San Diego, U.S.A.)
Page	pp. 697 - 704
Detailed information (abstract, keywords, etc)

Session 8S (Special Session) Reliability, Adaptability and Flexibility in Timing
Time: 15:50 - 17:30 Thursday, January 28, 2016
Location: TF4303
Organizer: Bing Li (Tech. Univ. München, Germany), Chair: Hidetoshi Onodera (Kyoto Univ., Japan)

8S-1 (Time: 15:50 - 17:30)

Title	(Invited Paper) Reliability, Adaptability and Flexibility in Timing: Buy a Life Insurance for Your Circuits
Author	*Ulf Schlichtmann (TU Munich, Germany), Masanori Hashimoto (Osaka Univ., Japan), Iris Hui-Ru Jiang (National Chiao Tung Univ., Taiwan), Bing Li (TU Munich, Germany)
Page	pp. 705 - 711
Detailed information (abstract, keywords, etc)

Session 8A Emerging Networks-on-Chip Designs
Time: 15:50 - 17:30 Thursday, January 28, 2016
Location: TF4203
Chairs: Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany), Chun-Yi Lee (National Tsing Hua Univ., Taiwan)

8A-1 (Time: 15:50 - 16:15)

Title	A High Performance Reliable NoC Router
Author	*Lu Wang, Sheng Ma, Zhiying Wang (National Univ. of Defense Tech., China)
Page	pp. 712 - 718
Detailed information (abstract, keywords, etc)

8A-2 (Time: 16:15 - 16:40)

Title	Dynamic Admission Control for Real-Time Networks-On-Chips
Author	*Adam Kostrzewa, Selma Saidi, Leonardo Ecco, Rolf Ernst (TU Braunschweig, Germany)
Page	pp. 719 - 724
Detailed information (abstract, keywords, etc)

8A-3 (Time: 16:40 - 17:05)

Title	FoToNoC: A Hierarchical Management Strategy Based on Folded Torus-Like Network-on-Chip for Dark Silicon Many-Core Systems
Author	*Lei Yang, Weichen Liu, Weiwen Jiang, Mengquan Li, Juan Yi, Edwin Hsing-Mean Sha (Chongqing Univ., China)
Page	pp. 725 - 730
Detailed information (abstract, keywords, etc)

8A-4 (Time: 17:05 - 17:30)

Title	Analytical ThruChip Inductive Coupling Channel Design Optimization
Author	*Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda (Keio Univ., Japan)
Page	pp. 731 - 736
Detailed information (abstract, keywords, etc)

Session 8B Test and Debug
Time: 15:50 - 17:30 Thursday, January 28, 2016
Location: TF4304
Chair: Shi-Yu Huang (National Tsing Hua Univ., Taiwan)

8B-1 (Time: 15:50 - 16:15)

Title	Extending Trace History Through Tapered Summaries in Post-silicon Validation
Author	*Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi (Indian Inst. of Tech. Delhi, India), Deepak Chauhan, Sharad Kumar (Freescale Semiconductors India Pvt, India)
Page	pp. 737 - 742
Detailed information (abstract, keywords, etc)

8B-2 (Time: 16:15 - 16:40)

Title	Novel Applications of Deep Learning Hidden Features for Adaptive Testing
Author	*Bingjun Xiao (Univ. of California, Los Angeles, U.S.A.), Jinjun Xiong (IBM Research, U.S.A.), Yiyu Shi (Univ. of Notre Dame, U.S.A.)
Page	pp. 743 - 748
Detailed information (abstract, keywords, etc)

8B-3 (Time: 16:40 - 17:05)

Title	Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns
Author	*Dominik Erb, Karsten Scheibler (Univ. of Freiburg, Germany), Michael A. Kochte (Univ. of Stuttgart, Germany), Matthias Sauer (Univ. of Freiburg, Germany), Hans-Joachim Wunderlich (Univ. of Stuttgart, Germany), Bernd Becker (Univ. of Freiburg, Germany)
Page	pp. 749 - 754
Detailed information (abstract, keywords, etc)

8B-4 (Time: 17:05 - 17:30)

Title	Test and Diagnosis Pattern Generation for Dynamic Bridging Faults and Transition Delay Faults
Author	*Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee (National Cheng Kung Univ., Taiwan)
Page	pp. 755 - 760
Detailed information (abstract, keywords, etc)

Session 8C Emerging Devices and Systems for Cyber-Physical Applications
Time: 15:50 - 17:30 Thursday, January 28, 2016
Location: TF4204
Chairs: Chengmo Yang (Univ. of Delaware, U.S.A.), Duo Liu (Chongqing Univ., China)

8C-1 (Time: 15:50 - 16:15)

Title	Flexible Transition Metel Dichalcogenide Field-Effect Transistors: A Circuit-Level Simulation Study of Delay and Power under Bending, Process Variation, and Scaling
Author	Ying-Yu Chen (Univ. of Illinois, Urbana-Champaign, U.S.A.), *Morteza Gholipour (Babol Univ. of Tech., Iran), Deming Chen (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Page	pp. 761 - 768
Detailed information (abstract, keywords, etc)

8C-2 (Time: 16:15 - 16:40)

Title	Non-Volatile Non-Shadow Flip-Flop using Spin Orbit Torque for Efficient Normally-off Computing
Author	*Rajendra Bishnoi, Fabian Oboril, Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany)
Page	pp. 769 - 774
Detailed information (abstract, keywords, etc)

8C-3 (Time: 16:40 - 17:05)

Title	Optimal Co-Scheduling of HVAC Control and Battery Management for Energy-Efficient Buildings Considering State-of-Health Degradation
Author	*Tiansong Cui, Shuang Chen (Univ. of Southern California, U.S.A.), Yanzhi Wang (Syracuse Univ., U.S.A.), Qi Zhu (Univ. of California, Riverside, U.S.A.), Shahin Nazarian, Massoud Pedram (Univ. of Southern California, U.S.A.)
Page	pp. 775 - 780
Detailed information (abstract, keywords, etc)

8C-4 (Time: 17:05 - 17:30)

Title	Accurate Remaining Range Estimation for Electric Vehicles
Author	*Joonki Hong, Sangjun Park, Naehyuck Chang (KAIST, Republic of Korea)
Page	pp. 781 - 786
Detailed information (abstract, keywords, etc)

The 21st Asia and South Pacific Design Automation Conference Technical Program

Session Schedule

List of papers

The 21st Asia and South Pacific Design Automation Conference
Technical Program