| Title | Extending Trace History Through Tapered Summaries in Post-silicon Validation |
| Author | *Sandeep Chandran, Preeti Ranjan Panda, Smruti R. Sarangi (Indian Institute of Technology Delhi, India), Deepak Chauhan, Sharad Kumar (Freescale Semiconductors India Pvt Ltd, India) |
| Page | pp. 737 - 742 |
| Keyword | Post-silicon Validation Methodology, Online filtering, Tapered Summaries |
| Abstract | On-chip trace buffers are increasingly being used for at-speed debug during post-silicon validation. However, the activity history captured by these buffers is small due to their limited size. We propose a novel scheme that extends the captured trace history (by upto 162%) by using a portion of the trace buffer to also store summaries of trace messages. We describe an Overlapped architecture that uses reduced number of ports to capture tapered summaries. We demonstrate the usefulness of the proposed methodology for debugging various classes of bugs encountered during post-silicon validation. |
| Title | Novel Applications of Deep Learning Hidden Features for Adaptive Testing |
| Author | *Bingjun Xiao (University of California, Los Angeles, U.S.A.), Jinjun Xiong (IBM Research, U.S.A.), Yiyu Shi (University of Notre Dame, U.S.A.) |
| Page | pp. 743 - 748 |
| Keyword | Adaptive testing, DNN, Big data |
| Abstract | Adaptive test of integrated circuits (IC) promises to increase
the quality and yield of products with reduced manufacturing
test cost compared to traditional static test flows. Based on recent progress on machine learning, this
paper proposes a novel deep learning based method for adaptive
test. In this paper, we start from a trained
deep neuron network (DNN) with a much higher accuracy than
the conventional test flow for the pass and fail prediction. We
further develop two novel applications by leveraging the features
learned from DNN: one to enable partial testing, i.e., make
decisions on pass and fail without finishing the entire test flow,
and two to enable dynamic test ordering, i.e., changing the
sequence of tests adaptively. Experiment results show significant
improvement on the accuracy and effectiveness of our proposed
method. |
| Title | Mixed 01X-RSL-Encoding for Fast and Accurate ATPG with Unknowns |
| Author | *Dominik Erb, Karsten Scheibler (University of Freiburg, Germany), Michael A. Kochte (University of Stuttgart, Germany), Matthias Sauer (University of Freiburg, Germany), Hans-Joachim Wunderlich (University of Stuttgart, Germany), Bernd Becker (University of Freiburg, Germany) |
| Page | pp. 749 - 754 |
| Keyword | Unknown values, test generation, Restricted symbolic logic, SAT, stuck-at faults |
| Abstract | Unknown (X) values in a design introduce pessimism
in conventional test generation algorithms which results in a loss of
fault coverage. This pessimism is reduced by a more accurate modeling
and analysis. Unfortunately, accurate analysis techniques highly
increase runtime and limit scalability. One promising technique to
prevent high runtimes while still providing high accuracy is the use
of restricted symbolic logic (RSL). However, also pure RSL-based
algorithms reach their limits as soon as millon gate circuits need to
be processed.
In this paper, we propose new ATPG techniques to overcome such
limitations. An efficient hybrid encoding combines the accuracy of
RSL-based modeling with the compactness of conventional threevalued
encoding. A low-cost two-valued SAT-based untestability
check is able to classify most untestable faults with low runtime. An
incremental and event-based accurate fault simulator is introduced
to reduce fault simulation effort.
The experiments demonstrate the effectiveness of the proposed
techniques. Over 97% of the faults are accurately classified. Both
the number of aborts and the total runtime are significantly reduced
compared to the state-of-the-art pure RSL-based algorithm. For
circuits up to a million gates, the fault coverage could be increased
considerably compared to a state-of-the-art commercial tool with
very competitive runtimes. |
| Title | Test and Diagnosis Pattern Generation for Dynamic Bridging Faults and Transition Delay Faults |
| Author | *Cheng-Hung Wu, Saint James Lee, Kuen-Jong Lee (National Cheng Kung Univ., Taiwan) |
| Page | pp. 755 - 760 |
| Keyword | Fault diagnosis, transition fault, dynamic bridging fault, diagnosis pattern generation, test compaction |
| Abstract | A dynamic bridging fault (DBF) induces a transition delay on a circuit node and hence has similar effects as a transition delay fault (TDF). However the causes of these two types of faults are quite different: a DBF is due to the bridging effects between two circuit nodes, while a TDF is due to a node itself or the logic connected to the node. Thus in addition to detecting these two types of faults, it is also important to distinguish them such that the exact sources of defects can be identified during the yield ramping process. In this paper we present an efficient test and diagnosis pattern generation procedure to detect DBFs and TDFs as well as to distinguish them. We first analyze the dominance relation between a DBF and its corresponding TDF. A novel circuit model called the inverse DBF (IDBF) model is then developed which can transform the problem of distinguishing a pair of a DBF and a TDF into the problem of detecting the inverse DBF. The pattern generation process can then be done by using an ATPG tool for dynamic bridging faults. We believe this is the first work to distinguish TDFs and DBFs. A complete procedure to generate both test and diagnosis patterns to detect all testable TDFs and DBFs in addition to distinguishing them is then presented. In this flow all TDFs and DBFs as well as all fault pairs between the two types of faults can be modeled in a single circuit and dealt with in a few ATPG runs. Thus the pattern generation process is quite efficient and very compact pattern sets can be obtained by utilizing the test pattern compaction feature of the ATPG tool. Experimental results on ISCAS89 benchmarks show that our procedure can detect all detectable TDFs and DBFs and up to 99.96% diagnosis resolution for these faults is achieved. |