| Title | A High Performance Reliable NoC Router |
| Author | *Lu Wang, Sheng Ma, Zhiying Wang (College of Computer, National University of Defense Technology, China) |
| Page | pp. 712 - 718 |
| Keyword | Reliability, Network-on-chip, High performance, Router design |
| Abstract | Aggressive scaling of CMOS process technology allows the fabrication of highly integrated chips, and enables the design of multiprocessors system-on-chip connected by the network- on-chip (NoC). However, it brings about widespread reliability challenges.
Aiming to tackle the permanent faults on the router components, we propose a high performance, high reliability and low cost router design based on a generic 2-stage router. Four fault tolerant strategies are added in our reliable router. We exploit a double routing strategy for the routing computation(RC) failure, a default winner strategy for the virtual channel allocation (VA), a runtime arbiter selection strategy for the switch allocation (SA) failure and a double bypass bus strategy for the crossbar failure. Different from previous reliable routers, our design leverages the feature of pipeline optimization and routing algorithm to maintain the performance in fault tolerance especially under heavy network loads. Besides, our proposed router provides higher reliability with lower hardware consumption than previous reliable router designs. |
| Title | Dynamic Admission Control for Real-Time Networks-On-Chips |
| Author | *Adam Kostrzewa, Selma Saidi, Leonardo Ecco, Rolf Ernst (TU Braunschweig, Germany) |
| Page | pp. 719 - 724 |
| Keyword | real-time, safety, overlay network |
| Abstract | Networks-on-Chip (NoCs) for real-time
systems require solutions for safe and predictable
sharing of network resources. In this work, we present
a mechanism for a global and dynamic admission con-
trol in NoCs designed for real-time systems. It in-
troduces an overlay network to synchronize transmis-
sions using arbitration units called Resource Managers
(RMs), which allows a global and work-conserving
scheduling. We present a formal worst-case timing
analysis for the proposed mechanism and demonstrate
that this solution not only exposes higher performance
in simulation but, even more importantly, consistently
reaches smaller formally guaranteed worst-case laten-
cies than TDM for realistic levels of system’s utiliza-
tion. Our mechanism does not require modification of
routers and therefore can be used together with any
architecture utilizing non-blocking routers. |
| Title | FoToNoC: A Hierarchical Management Strategy Based on Folded Torus-Like Network-on-Chip for Dark Silicon Many-Core Systems |
| Author | *Lei Yang, Weichen Liu, Weiwen Jiang, Mengquan Li, Juan Yi, Edwin Hsing-Mean Sha (Chongqing University, China) |
| Page | pp. 725 - 730 |
| Keyword | Dark silicon, System performance, Network-on-Chip, Temperature |
| Abstract | In this dark silicon era, techniques have been developed to selectively activate nonadjacent cores in physical locations to maintain the safe temperature and allowable power budget on a many-core chip. This will result in unexpected increase in the communication overhead due to longer average distance between active cores in a typical mesh-based Network-on-Chip (NoC), and in turn reduce the system performance and energy efficiency. In this paper, we present FoToNoC, a Folded Torus-like NoC, and a hierarchical management strategy on top of it, to address this tradeoff problem for heterogeneous many-core systems. Optimizations of chip temperature, inter-core communication, application performance, and system energy consumption are well isolated in FoToNoC, and addressed in different design phases and aspects. A cluster-based hierarchical strategy is proposed to manage the system adaptively in several different control levels. Compared with mesh-based systems on a set of synthetic and real benchmarks, FoToNoC can achieve on average 39.4% performance improvement when similar temperature conditions are maintained, and the proposed strategy can further reduce the total energy consumption by up to 42.0%. |
| Title | Analytical ThruChip Inductive Coupling Channel Design Optimization |
| Author | *Li-Chung Hsu, Junichiro Kadomoto, So Hasegawa, Atsutake Kosuge, Yasuhiro Take, Tadahiro Kuroda (Keio University, Japan) |
| Page | pp. 731 - 736 |
| Keyword | TCI, 3-D IC, ThruChip, Inductive Coupling |
| Abstract | ThruChip interface (TCI) is an emerg- ing 3-D integrated circuit stacking technology. TCI utilizes on-chip inductor to build vertical communi- cation channel in near field distance and has been proved to stand comparison with through-silicon-via (TSV) in data rate, power, and reliability. Moreover, it is also cost-effective in manufacturing due to its wireless nature. In this paper, an analytical method is proposed to find near-optimal TCI inductive cou- pling channel solution. The experiment results show an average 16.8% transmitting current reduction and shrink design time from days to a few minutes. |