| Title | Laplacian Eigenmaps and Bayesian Clustering Based Layout Pattern Sampling and Its Applications to Hotspot Detection and OPC |
| Author | *Tetsuaki Matsunawa (Toshiba Corp., Japan), Bei Yu (Chinese University of Hong Kong, Hong Kong), David Z. Pan (University of Texas at Austin, U.S.A.) |
| Page | pp. 679 - 684 |
| Keyword | Pattern Sampling, Clustering, OPC, Hotspot Detection |
| Abstract | Effective layout pattern sampling is a fundamental component for lithography process optimization, hotspot detection, and model calibration.
Existing pattern sampling algorithms rely on either vector quantization or heuristic approaches.
However, it is difficult to manage these methods due to the heavy demands of prior knowledges, such as high-dimensional layout features and manually tuned hypothetical model parameters.
In this paper we present a self-contained layout pattern sampling framework, where no manual parameter tuning is needed.
To handle high dimensionality and diverse layout feature types, we propose a nonlinear dimensionality reduction technique with kernel parameter optimization.
Furthermore, we develop a Bayesian model based clustering, through which automatic sampling is realized without arbitrary setting of model parameters.
The effectiveness of our framework is verified through a sampling benchmark suite and two applications, lithography hotspot detection and optical proximity correction. |
| Title | Balancing Lifetime and Soft-Error Reliability to Improve System Availability |
| Author | *Junlong Zhou (University of Notre Dame, East China Normal University, U.S.A.), X. Sharon Hu, Yue Ma (University of Notre Dame, U.S.A.), Tongquan Wei (East China Normal University, China) |
| Page | pp. 685 - 690 |
| Keyword | Lifetime, Soft-Error, Reliability, Availability, MTTF |
| Abstract | CMOS scaling has greatly increased concerns for lifetime reliability due to permanent faults and soft-error reliability due to transient faults. Most existing works only focus on one of the two reliability concerns, but often times techniques used to increase one type of reliability may adversely impact the other type. A few efforts do consider both types of reliability together and use two different metrics to quantify the two types of reliability. However, for many systems, the concern of the user is to maximize system availability by improving the mean time to failure (MTTF), regardless of whether the failure is caused by permanent faults or transient faults. Addressing this concern requires a uniform metric to measure the effect due to both types of faults. In this paper, we derive a novel analytical expression for calculating the MTTF due to transient faults. Using this new formula and an existing method to evaluate system MTTF, we formulate and solve the problem of maximizing system availability with consideration of permanent faults, transient faults, and throughput constraint. Extensive simulations of synthetic task sets and benchmarks based on real-world applications were performed to validate our algorithm. |
| Title | A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region |
| Author | *Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto University, Japan) |
| Page | pp. 691 - 696 |
| Keyword | Cross-coupled inverter, Yield, Stability, Analytical Model, Sub-threshold Voltage |
| Abstract | A cross-coupled inverter which is an essential element of on-chip memory subsystems plays an important role in synchronous LSI circuits.
In this paper, an analytical stability model for a cross-coupled inverter operating in a sub-threshold voltage region is proposed.
The proposed model analytically shows that the minimum operating voltage of the cross-coupled inverter distributes normally in a high-sigma region if the distribution of the threshold voltage is Gaussian.
The minimum supply voltage at which the yield of the cross-coupled inverter becomes a specific value can be accurately derived by a simple calculation using the model. Monte-Carlo simulation assuming a commercial 28nm process technology demonstrates the accuracy and the validity of the proposed model.
Based on the model, this paper shows strategies for variation tolerant memory design. |
| Title | Delay Uncertainty and Signal Criticality Driven Routing Channel Optimization for Advanced DRAM Products |
| Author | Samyoung Bang (Samsung Electronics, Republic of Korea), Kwangsoo Han, Andrew B. Kahng, *Mulong Luo (University of California at San Diego, U.S.A.) |
| Page | pp. 697 - 704 |
| Keyword | interconnection, crosstalk, DRAM, timing |
| Abstract | Crosstalk-induced delay change is a critical challenge
to physical design of long interconnect channels in DRAM products
at the 2x and 1x technology nodes. Due to severe cost challenges
in a high-volume, commodity market, layout resources including
channel width, buffers, and number of metal routing layers are
extremely scarce. We describe a new channel optimizer that reduces
crosstalk-induced delay uncertainty, weighted by signal criticality and aware of signal activity correlations (e.g., to reduce delay uncertainty by mutual shielding). Instead of the typical signal net permutation strategy, we apply (pessimistic) timing-driven swizzling to minimize the delay uncertainty cost function. Contributions of this work include (1) an accurate and efficient analytical crosstalk delay calculator, (2) scalability up to hundreds of signals and tracks in the routing channel through use of greedy and decomposition strategies as well as a pair-swapping heuristic, and (3) experimental studies that demonstrate up to 24% reduction of the worstcase
criticality-weighted delay uncertainty (or, 34ps of absolute
delay uncertainty reduction) compared with the typical signal
permutation approach. |