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The 21st Asia and South Pacific Design Automation Conference

Session 7B  Design for Trustworthy IC
Time: 13:50 - 15:30 Thursday, January 28, 2016
Location: TF4304
Chairs: Yu Wang (Tsinghua Univ., China), Jeyavijayan Rajendran (Univ. of Texas, Dallas, U.S.A.)

7B-1 (Time: 13:50 - 14:15)
TitleNetlist Reverse Engineering for High-Level Functionality Reconstruction
Author*Travis Meade, Shaojie Zhang, Yier Jin (Univ. of Central Florida, U.S.A.)
Pagepp. 655 - 660
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7B-2 (Time: 14:15 - 14:40)
TitleAssessing CPA Resistance of AES with Different Fault Tolerance Mechanisms
AuthorHoda Pahlevanzadeh, Jaya Dofe, *Qiaoyan Yu (Univ. of New Hampshire, U.S.A.)
Pagepp. 661 - 666
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7B-3 (Time: 14:40 - 15:05)
TitleSPARTA: A Scheduling Policy for Thwarting Differential Power Analysis Attacks
Author*Ke Jiang, Petru Eles, Zebo Peng, Sudipta Chattopadhyay (Linköping Univ., Sweden), Lejla Batina (Radboud Univ., Netherlands)
Pagepp. 667 - 672
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7B-4 (Time: 15:05 - 15:30)
TitleAnalysis and Vulnerability Exploration of Current Secure Scan Designs
AuthorYanhui Luo, *Aijiao Cui (Harbin Inst. of Tech. Shenzhen Graduate School, China), Huawei Li (Chinese Academy of Sciences, China), Gang Qu (Univ. of Maryland College Park, U.S.A.)
Pagepp. 673 - 678
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