| Title | Aging-aware High-level Physical Planning for Reconfigurable Systems |
| Author | Zana Ghaderi, *Eli Bozorgzadeh (University of California, Irvine, U.S.A.) |
| Page | pp. 631 - 636 |
| Keyword | Aging mitigation, Reconfigurable systems, Physical planning, Performance degradation, Aging analysis |
| Abstract | Due to advanced silicon technology, reconfigurable system-on-chip devices such as FPGAs are increasingly becoming sensitive to aging effects. This paper presents a high-level physical planning with reconfiguration strategy in order to mitigate the aging-induced delay degradation in FPGA resources. The proposed solution is an offline framework composed of an aging-aware floorplanner coupled with a proactive aging-aware reconfiguration policy which generates checkpoints aperiodically for runtime reconfiguration. We consider BTI and HCI aging mechanisms and consider the BTI-based aging recovery during idle periods using aging history map. The experiments demonstrate that sequence of configurations generated by this scheme provides average aging-rate reduction on FPGA resources and application performance by 53.2% and 17.5%, respectively. |
| Title | Hardware Reliability Margining for the Dark Silicon Era |
| Author | Liangzhen Lai, *Puneet Gupta (UCLA, U.S.A.) |
| Page | pp. 637 - 642 |
| Keyword | dark silicon, reliability, margining |
| Abstract | Hardware reliability margin should be derived from the worst-case aging scenario, which typically occurs when the circuits are operating at peak performance state with the highest operating voltage and frequency. However, as integrated circuits enter the ``dark silicon'' era, it is impossible to power up all circuits throughout the entire lifetime. Reliability margining in absence of architecture-level power/thermal constraints can be overly pessimistic. In this work, we propose a margining scheme that employs the power/thermal contexts and system management policies to derive the actual worst-case workload pattern for different reliability phenomena. Our experiment results show that at 60% dark ratio, conventional margining approach can overestimate the aging degradation due to EM and BTI by up to 3-7X and 18% respectively. Our margining method is able to eliminate these over-pessimism and results in about 20% delay margin and 40%-60% metal width margin reduction. |
| Title | ACR: Enabling Computation Reuse for Approximate Computing |
| Author | *Xin He (Chinese Academy of Sciences, China), Guihai Yan, Yinhe Han, Xiaowei Li (Institute of Computing Technology, Chinese Academy of Sciences, China) |
| Page | pp. 643 - 648 |
| Keyword | Approximate computing, Computation reuse |
| Abstract | Approximate computing, which trades off computation quality (e.g, accuracy) and computation efforts, has becoming a promising technique to improve performance for many mission-non-critical and error-tolerant applications. The computations in such applications usually exhibit superior value locality, i.e, computations performed by a function or code region are very likely to reproduce ``similar'' results. Reusing the similar results can bypass redundant computations, as long as ``exact'' results are not mandatory. However, conventional computation reuse techniques are less effective in approximate computing paradigm. The input values of two computation instances have to be identical to reuse one for another, hence ``exact'' in nature. We propose ACR, an approximate computation reuse framework, to enable computation reuse for approximate computing. ACR relaxes the exact matching in inputs to some extent regulated by ``similarity'' quantification, thereby shifting the exact computation reuse paradigm to its approximate counterpart. We furthermore propose an input significance-aware similarity quantification scheme through statistical approaches. Experimental result shows ACR could effectively exploit the potential of computation reuse for approximate computing and reduce 47.6\% computations on average for a set of approximate applications. |
| Title | Work hard, sleep well - Avoid irreversible IC wearout with proactive rejuvenation |
| Author | *Xinfei Guo, Mircea R. Stan (University of Virginia, U.S.A.) |
| Page | pp. 649 - 654 |
| Keyword | irreversible wearout, boundary, sleep-when-getting-tired, negative turbo boost |
| Abstract | Various wearout mechanisms have both a reversible and an irreversible (permanent) part, with some, like BTI and EM having a significant reversible part, while others, like HCI, being mostly irreversible. In this paper we make two contributions. First, we show that the boundary between the reversible and irreversible parts of wearout is not fixed, with the irreversible part becoming at least partially reversible under the right conditions of active accelerated recovery and stress/recovery scheduling. Second, we show that there are certain stress/recovery schedules that can (almost) completely eliminate irreversible wearout, thus allowing significant reductions in necessary design margins. The experiments were done on commercial FPGAs fabricated in a 40nm technology. To fully repair and avoid the irreversible wearout, we propose a biology-inspired sleep-when-getting-tired strategy. The strategy can achieve >60x design margin reduction and ~9% average performance improvement within a 10-year lifetime constraint compared to the no-recovery case. Potential system level implementations (a negative “turbo-boost” like strategy) in multicore and NoC systems are also presented. |