| Title | (Invited Paper) Efficient Reliability Management in SoCs – An Approximate DRAM Perspective |
| Author | Matthias Jung, Deepak M. Mathew, Christian Weis, *Norbert Wehn (University of Kaiserslautern, Germany) |
| Page | pp. 390 - 394 |
| Keyword | Approximate, DRAM, Reliability, Refresh, Memory |
| Abstract | In today's computing systems Dynamic Random Access Memories (DRAMs) have a large influence on performance and contribute significantly to the total power consumption. Thus, recent research activities bring the idea of approximate DRAM into focus to save power and improve performance by lowering the refresh rate or disabling refresh completely. Hence, fast and accurate models are required for a thoroughly exploration of approximate DRAM for error resilient applications. In this paper we present a holistic simulation environment for investigations on approximate DRAM and show the impact on error resilient applications. |
| Title | (Invited Paper) Cross-layer Virtual/Physical Sensing and Actuation for Resilient Heterogeneous Many-core SoCs |
| Author | *Santanu Sarma, Tiago Mück, Majid Shoushtari, Abbas BanaiyanMofrad, Nikil Dutt (UC Irvine, U.S.A.) |
| Page | pp. 395 - 402 |
| Keyword | cross-layer, virtual sensor, SoC, CPSoC, MPSoC |
| Abstract | We introduce the concepts of cross-layer virtual/physical sensing and actuation to achieve resiliency for the emerging class of heterogeneous many-core Systems-on-Chip (SoCs). Using the CyberPhysical System-on-Chip (CPSoC) concept as an exemplar sensor-rich many-core heterogeneous computing platform, we illustrate how to intrinsically couple on-chip and cross-layer physical and virtual sensing and actuation applied across different layers of the hardware/software system stack to adaptively achieve desired objectives and Quality-of-Service (QoS). We present two sample use cases that exemplify the cross-layer virtual/physical sensing and actuation approach. First, we present SmartBalance, a cross-layer sensing-driven Linux load balancer for energy efficient task execution on heterogeneous MPSoCs. Second, we present “Partially Forgetful Memories”, a software/hardware approach that achieves dynamic memory guard-banding for memory resilience and its application for approximate computing. |
| Title | (Invited Paper) On-chip Monitoring and Compensation Scheme with Fine-grain Body Biasing for Robust and Energy-Efficient Operations |
| Author | A.K.M. Mahfuzul Islam (University of Tokyo, Japan), *Hidetoshi Onodera (Kyoto University, Japan) |
| Page | pp. 403 - 409 |
| Keyword | Energy Optimization, Compensation, Monitor, Body Biasing, Scaling |
| Abstract | Aggressive technology scaling and strong demand for lowering supply voltage impose a serious challenge in achieving robust and energy-efficient circuit operation. This paper first overviews on device-circuit interactions to enable cross-layer resiliency, and energy optimization. We show that the ability to monitor and control device and circuit characteristics not only in- crease energy-efficiency by more than 20% but also relax the severe design constraints, which were required because of the uncertainties of variability. We then demonstrate two proof-of-concept circuits in a 65 nm process to show variability resiliency and energy optimization with local body biasing. |
| Title | (Invited Paper) Embedded Software Reliability Testing by Unit-Level Fault Injection |
| Author | Petra R. Maier, Daniel Mueller-Gritschneder, Ulf Schlichtmann (TU Munich, Germany), *Veit B. Kleeberger (Infineon Technologies, Germany) |
| Page | pp. 410 - 416 |
| Keyword | Reliability, Embedded Software, ISO 26262 |
| Abstract | Decreasing device sizes in integrated circuits lead to increasing vulnerability of hardware to errors resulting from radiation, crosstalk or power-supply disturbances. Especially in the automotive domain many tasks of electronics are safety relevant, so that solid error detection and correction is imperative. However, completely safe hardware is too expensive for the cost sensitive automotive market. Hence, software safety mechanisms must deal with errors originating from hardware to ensure safe system behavior. To verify safe system behavior under the influence of hardware errors, fault injection is currently done at integration level, but software redesign at this design stage should be avoided due to high costs. To early detect code vulnerable to hardware errors, we propose fault injection at unit level. Thanks to short simulation scenarios and good parallelization capability, even exhaustive fault injection is possible for multiple representative workloads. Using the results from the fault-injection campaigns, the software designer is able to consider reliability during the implementation phase and avoid costly redesigns. |