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The 21st Asia and South Pacific Design Automation Conference

Session 5C  Advances in Logic Synthesis
Time: 13:50 - 15:55 Wednesday, January 27, 2016
Location: TF4204
Chairs: Benjamin Carrion Schafer (Hong Kong Polytechnic Univ., Hong Kong), Kai-Chiang Wu (National Chiao Tung Univ., Taiwan)

5C-1 (Time: 13:50 - 14:15)
TitleLattice-Based Boolean Diagrams: Canonical, Order-Independent Graphical Representations of Boolean Functions
AuthorAhmed Nassar, *Fadi J. Kurdahi (Univ. of California, Irvine, U.S.A.)
Pagepp. 468 - 473
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5C-2 (Time: 14:15 - 14:40)
TitleBDD Minimization for Approximate Computing
Author*Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler (Univ. of Bremen, Germany)
Pagepp. 474 - 479
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5C-3 (Time: 14:40 - 15:05)
TitleMajorSat: A SAT Solver to Majority Logic
AuthorYu-Min Chou (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (Yuan Ze Univ., Taiwan), Chun-Yao Wang, *Ching-Yi Huang (National Tsing Hua Univ., Taiwan)
Pagepp. 480 - 485
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5C-4 (Time: 15:05 - 15:30)
TitleFast Synthesis of Threshold Logic Networks with Optimization
Author*Yung-Chih Chen, Runyi Wang, Yan-Ping Chang (Yuan Ze Univ., Taiwan)
Pagepp. 486 - 491
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5C-5 (Time: 15:30 - 15:55)
TitlePolysynchronous Stochastic Circuits
Author*M. Hassan Najafi, David J. Lilja, Marc Riedel, Kia Bazargan (Univ. of Minnesota, U.S.A.)
Pagepp. 492 - 498
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