Title | Dynamic Planning of Local Congestion from Varying-Size Vias for Global Routing Layer Assignment |
Author | Daohang Shi, Edward Tashjian, *Azadeh Davoodi (University of Wisconsin-Madison, U.S.A.) |
Page | pp. 372 - 377 |
Keyword | global routing, layer assignment, local congestion, detailed routing, via modeling |
Abstract | This work is the first to present global routing models for
capturing the impact of local congestion caused by varying-size vias.
The models are then incorporated to dynamically drive a proposed layer
assignment algorithm. This is also the first work to actually evaluate
the impact of global routing solutions using a commercial detailed router. In our experiments we report fewer number of DRC violations by only changing the layer assignment at global routing, and detailed route using the Olympus-SoC of Mentor Graphics. |
Title | Negotiation-Based Track Assignment Considering Local Nets |
Author | *Man-Pan Wong (National Tsing Hua University, Taiwan), Wen-Hao Liu (Cadence Design Systems Inc., U.S.A.), Ting-Chi Wang (National Tsing Hua University, Taiwan) |
Page | pp. 378 - 383 |
Keyword | Routability, congestion, track assignment |
Abstract | Routability has become a very challenging issue in a modern VLSI design flow. Many works use global routing to estimate the routability in early design stages. However, global routing cannot accurately capture local congestion, so it is hard to detect the detailed routability issue. To more accurately estimate the detailed-routing routability, this paper presents a track-assignment-based routability estimator. In this work, wire segments called iroutes are extracted from a global routing result, and then the proposed negotiation-based algorithm assigns these iroutes to proper tracks and minimizes the overlaps between the iroutes. Based on the assignment result, we can judge which regions may have critical routability issues by seeing where more overlaps reside. |
Title | Ordered Escape Routing for Grid Pin Array Based on Min-cost Multi-commodity Flow |
Author | *Fengxian Jiao, Sheqin Dong (Tsinghua University, China) |
Page | pp. 384 - 389 |
Keyword | PCB Routing, Ordered Escape Routing, Min-cost Multi-commodity flow |
Abstract | Ordered Escape routing is a critical issue in high-speed PCB routing. In this paper, for the first time, a Min-cost Multi-commodity Flow (MMCF) approach is proposed to solve the ordered escape routing. The characteristic of grid pin array is analyzed and then a basic network model is used to convert ordered escape routing to MMCF model. To satisfy the constraints of ordered escape routing, three novel transformations, such as non-crossing transformation, ordering transformation and capacity transformation, are used to convert the basic network model to the final correct MMCF model. Experimental results show that our method achieves 100% routability for all the test cases. The method can get both a feasible solution and an optimal solution. Compared to published approaches, our method improves in both wire length and CPU time remarkably. |