| Title | A Novel PUF based on Cell Error Rate Distribution of STT-RAM |
| Author | *Xian Zhang, Guangyu Sun (Peking University, China), Yaojun Zhang, Yiran Chen, Hai Li (University of Pittsburgh, U.S.A.), Wujie Wen (Florida International University, U.S.A.), Jia Di (University of Arkansas, U.S.A.) |
| Page | pp. 342 - 347 |
| Keyword | PUF, STTRAM, Spintronic |
| Abstract | Physical Unclonable Functions (PUFs) have been widely proposed as security primitives to provide device iden- tification and authentication. Recently, PUFs based on Non- volatile Memory (NVM) are widely proposed since the promise of NVMs’ wide application. In addition, NVM-based PUFs are considered to be more immune to invasive attack and simulation attack than CMOS-based PUFs. However, the existing NVM- based PUF either shows the unreliability under environmental variations or need extra modifications to the IC manufacturing process. In this work, we propose err-PUF, a novel PUF design based on the cell error rate distribution of STT-RAM. Instead of using the distribution directly, we generate a stable finger- print based on a novel concept called Error-rate Differential Pair (EDP) without modifications to the read/write circuits. Comprehensive results demonstrate that err-PUF can achieve sufficient reliability under environmental variations, which can significantly impact the cell error rates. Moreover, compared with existing approaches, err-PUF has a higher speed and lower power consumption with negligible overhead. |
| Title | Data Privacy in Non-Volatile Cache: Challenges, Attack Models and Solutions |
| Author | Nitin Rathi, *Swaroop Ghosh, Anirudh Iyengar (University of South Florida, U.S.A.), Helia Naeimi (Intel Labs, U.S.A.) |
| Page | pp. 348 - 353 |
| Keyword | Nonvolatile cache memory, Data Privacy, Attack model, Architecture |
| Abstract | Non-volatile memories (NVMs) have drawn significant attention due to complete elimination of bitcell leakage. Among the NVMs, Spin-Transfer-Torque RAM (STTRAM) is considered to be a strong candidate for last level cache (LLC). Although promising STTRAM LLC brings new security challenges that were absent in conventional volatile memories such as Static RAM (SRAM). The root cause is persistent data and the fundamental dependency of the memory technology on ambient parameters such as magnetic field and temperature that can be exploited to compromise the data. We provide a qualitative analysis of the data privacy issues in the emerging nonvolatile cache. We also propose new attack models to compromise the sensitive data in LLC. The encryption technique used to secure the data in main memory and hard disk may not be useful for LLC due to latency overhead. We propose two low-overhead techniques to ensure data privacy in LLC- (a) implementing semi nonvolatile memory (SNVM); and, (b) data erasure at power OFF. Erasing could be energy intensive and may require dedicated battery to work under power failure attacks. To address this concern we reuse the energy stored in power rail after power OFF to erase the bits using a canary circuit to track MTJ write time. The simulation results show 0.6% IPC loss and 1.2% energy overhead during normal operation due to added circuitry. |
| Title | Pin Tumbler Lock: A Shift based Encryption Mechanism for Racetrack Memory |
| Author | *Hongbin Zhang (Tsinghua University, China), Chao Zhang, Xian Zhang, Guangyu Sun (Peking University, China), Jiwu Shu (Tsinghua University, China) |
| Page | pp. 354 - 359 |
| Keyword | Racetrack Memory, Encryption, NVM |
| Abstract | As various non-volatile memory (NVM) technologies have been adopted in different levels of memory hierarchy, the security issue of protecting information retained in NVM after power-off has become a new challenge, which results in extensive research on data encryption for NVM. Previous encryption approaches, however, have some limitations, such as high design complexity and non-trivial timing and energy overhead. Recently, an emerging NVM called racetrack memory (RM) has been widely investigated because of its advantages of ultra-high storage density
and fast read/write speed. Besides these well-known advantages, we observe that the tape-like structure of RM cell and its unique shift operation can also be leveraged to facilitate NVM data encryption. Base on this observation, we propose an efficient shift based mechanism, named Pin Tumbler Lock (PTL), which completes encryption and decryption by shifting racetracks in several nanoseconds. Experimental results demonstrate that our design can achieve the same security strength of AES-128 with 3.1% performance overhead and 3.7% energy overhead and 1.56% storage cost and 1.6% area cost. |
| Title | Routing Path Reuse Maximization for Efficient NV-FPGA Reconfiguration |
| Author | Yuan Xue, Patrick Cronin, *Chengmo Yang (University of Delaware, U.S.A.), Jingtong Hu (Oklahoma State University, U.S.A.) |
| Page | pp. 360 - 365 |
| Keyword | NVM-based FPGA, reuse-aware routing, switch-box reconfiguration |
| Abstract | Non-volatile memory-based FPGAs (NV-FPGAs) are expecting to replace traditional SRAM-based FPGAs to achieve higher scalability and lower power consumption. Yet the slow write performance of NVMs challenges FPGA (re)configuration speed and overhead. To efficiently configure switch boxes, this paper proposes a routing path reuse technique. Technical contributions include a mathematical reconfiguration cost model of routing resources, a reuse-aware routing scheme, as well as the incorporation of the proposed scheme into standard VTR CAD tool. |