| Title | ApproxMap: On Task Allocation and Scheduling for Resilient Applications |
| Author | *Juan Yi (Chongqing University, China), Qian Zhang, Ye Tian, Ting Wang (The Chinese University of Hong Kong, China), Weichen Liu, Edwin H.-M. Sha (Chongqing University, China), Qiang Xu (The Chinese University of Hong Kong, China) |
| Page | pp. 318 - 323 |
| Keyword | multiprocessors, resilient application, scheduling, energy efficiency |
| Abstract | Many emerging applications are inherently error-resilient and hence do not require exact computation. In this paper, we consider the task allocation and scheduling problem for mapping such applications to voltage-scalable multiprocessor systems. The proposed solution, namely ApproxMap, judiciously determines the mapping and execution sequence of resilient tasks to minimize the energy consumption of the application while meeting their target quality requirements and timing constraints. To be specific, ApproxMap generates energy-efficient yet flexible task schedule at design-time, and conducts lightweight online adjustment according to runtime dynamics for further energye-fficiency improvement. Experimental results on various task graphs demonstrate the efficacy of ApproxMap. |
| Title | Energy Optimization of Stochastic Applications with Statistical Guarantees of Deadline and Reliability |
| Author | *Xiong Pan, Wei Jiang (University of Electronic Science and Technology of China, China), Ke Jiang (Linköping University, Sweden), Liang Wen, Qi Dong (University of Electronic Science and Technology of China, China) |
| Page | pp. 324 - 329 |
| Keyword | Energy, Reliability, Soft Real-time, Stochastic task, System-level design |
| Abstract | In this paper, we target on energy-efficient design of soft real-time and reliable applications on uniprocessor embedded systems. We consider soft real-time tasks with stochastic execution times with given distribution. Instead of guaranteeing hard real-time constraint, the application may be finished after their deadlines with a certain probability. We utilize Dynamic Voltage and Frequency Scaling (DVFS) to save energy, and also take into account of the impact of DVFS on reliability. Our objective is to minimize the expected energy consumption of the system subject to statistical reliability and deadline constraints. Due to the huge complexity of solving the problem exactly, we develop a fast bi-search approach based on dynamic programming, which can find the near-optimal solution with energy cost at most (1+β) times of the optimal energy and has polynomial time complexity. Extensive experiments and a real-life application were conducted to evaluate the efficiency of the proposed techniques. |
| Title | Optimization of Behavioral IPs in Multi-Processor System-on-Chips |
| Author | Yidi Liu, *Benjamin Carrion Schafer (the Hong Kong Polytechnic University, Hong Kong) |
| Page | pp. 336 - 341 |
| Keyword | high level synthesis, multi-processor SoC, behavioral IP, MPSoC |
| Abstract | This work shows that behavioral IPs (BIPs) are often over-designed when used in heterogeneous Multi-Processor SoCs (MPSoCs) mainly because they are designed and optimized separately. When inserted in the MPSoC, these IPs often have to wait for data from the master and also access to the bus to return the results. Behavioral IPs have the advantage over traditional RTL-based IPs that they can be re-synthesized with different constraints, which allows the generation of micro-architectures with unique area vs. performance trade-off. This work leverages this and introduces a method to automatically identify the workload of each behavioral IP mapped as a slave on an MPSoC system and re-synthesizes it to maximize its efficiency, i.e. reduce its area and minimize its idle time, without affecting the overall performance. We show the area can be reduced by up to 26.1% compared to the fastest implementation without any performance degradation and on average by 13.21%. Compared to an exhaustive search our method is only on average 5% worse while on average 16x faster. |