| Title | (Keynote Address) Majority-based Synthesis for Nanotechnologies |
| Author | Luca Amaru, Pierre-Emmanuel Gaillardon, *Giovanni De Micheli (Integrated Systems Laboratory, EPFL, Switzerland) |
| Page | pp. 499 - 502 |
| Keyword | Logic Synthesis, Majority Logic, Nanotechnology |
| Abstract | We study the logic synthesis of emerging nanotech- nologies whose elementary devices abstraction is a majority voter. We argue that synthesis tools, natively supporting the majority logic abstraction, are the technology enablers. This is because they allow designers to validate majority-based nanotechnologies on large-scale benchmarks. We describe models and data- structures for logic design with majority-based nanotechnologies and we show results of applying new synthesis algorithms and tools. We conclude that new logic synthesis methods are required to achieve a fair assessment on emerging nanotechnologies. |
| Title | (Keynote Address) A Scalable Communication-Aware Compilation Flow for Programmable Accelerators |
| Author | *Jason Cong, Hui Huang, Mohammad Ali Ghodrat (UCLA, U.S.A.) |
| Page | pp. 503 - 510 |
| Keyword | Keynote |
| Abstract | Programmable accelerators (PA) are receiving increased attention in domain-specific architecture designs to provide more general support for customization. In a PA-rich system, computational kernels are compiled into predefined PA templates and dynamically mapped to real PAs at runtime. This imposes a demanding challenge on the compiler side – that is, how to generate high-quality PA mapping code. Another important concern is the communication cost among PAs: if not handled properly at compile time, data transfers among tens or hundreds of accelerators in a PA-rich system will limit the overall performance gain. In this paper we present an efficient PA compilation flow, which is scalable for mapping large computation kernels into PA-rich architectures. Communication overhead is modeled and optimized in the proposed flow to reduce runtime data transfers among accelerators. Experimental results show that for 12 computation-intensive standard benchmarks, the proposed approach significantly improves compilation calability, mapping quality and overall communication cost compared to state-of-art PA compilation approaches. We also evaluate the proposed flow on a recently developed PA-rich platform [1]; the final performance gain is improved by 49.5% on average. |
| Title | (Keynote Address) Software and System Co-optimization in the era of Heterogeneous Computing |
| Author | *Michael Gschwind (IBM Thomas J Watson Research Center, U.S.A.) |
| Keyword | Keynote |
| Abstract | Escalating costs of semiconductor technology and its lagging performance relative to historic trends is motivating acceleration and specialization as more impactful means to increase system value. Targeted specialization is being increasingly pursued as an important way to achieve dramatic improvements in workload acceleration. This requires a broad understanding of workloads, system structures, and algorithms to determine what to accelerate / specialize, and how, i.e., via SW?; via HW?; or via SW+HW? which presents many choices, necessitating co-optimization of SW and HW. In this talk, we will focus on an application driven approach to software and system co-optimization, based on inventing new software algorithms, that have strong affinity to hardware acceleration. A High Level design methodology that is needed to enable targeted specialization in hardware will also be described. |