| Title | Speed Binning With High-Quality Structural Patterns From Functional Timing Analysis (FTA) |
| Author | *Louis Y.-Z. Lin, Charles H.-P. Wen (Dept. of Elec. Comp. Engr., National Chiao Tung University, Taiwan) |
| Page | pp. 238 - 243 |
| Keyword | speed-binning, FTA |
| Abstract | The operating speed of a chip decides its price in the nanometer era. Thus, design companies require highquality speed binning to maximize their profits. The way they usually rely on is legacy (i.e. structural) tests for speed binning since functional tests are too expensive to derive. Besides legacy and functional tests, recent studies tried to apply the notion of delay testing for deriving speed-binning patterns; nevertheless, all of them could not determine the number of patterns in the meanwhile of taking process variation into consideration. Therefore, in this paper, we propose speed-binning pattern generation (SBPG) method to deterministically generate a high-quality pattern set for speed binning. This SPBG mainly consists of two core techniques: (1) empirical variation sampling (EVS) and (2) functional timing analysis (FTA), which efficiently derives few high-quality patterns from a small number of learning samples. Finally, in experimental results, SBPG achieves a satisfactory accuracy (> 99% on average) for five benchmark circuits under various conditions of process variation, and is shown to be an efficient solution for speed binning. |
| Title | Electromigration Recovery Modeling and Analysis under Time-Dependent Current and Temperature Stressing |
| Author | Xin Huang (University of California, Riverside, U.S.A.), Valeriy Sukharev (Mentor Graphics Corporation, U.S.A.), Taeyoung Kim (University of California, Riverside, U.S.A.), Haibao Chen (Shanghai Jiao Tong University, China), *Sheldon X.-D. Tan (University of California, Riverside, U.S.A.) |
| Page | pp. 244 - 249 |
| Keyword | EM, reliability, recovery, analytical model |
| Abstract | Electromigration (EM) has been considered to be the major reliability issue for current and future VLSI technologies. Current EM reliability analysis is overloaded by over-conservative and simplified EM models. Particularly the transient recovery effect in the EM-induced stress evolution kinetics has never been treated properly in all the existing analytical EM models. In this article, we propose a new physics-based dynamic compact EM model, which for the first time, can accurately predict the transient hydrostatic stress recovery effect in a confined metal wire. The new dynamic EM model is based on the direct analytical solution of one-dimensional Korhonen’s equation with load driven by any unipolar or bipolar current waveforms under varying temperature. We show that the EM recovery effect can be quite significant even under unidirectional current loads. This healing process is sensitive to temperature, and higher temperatures lead to faster and more complete recovery. Such effect can be further exploited to significantly extend the lifetime of the interconnect wires if the chip current or power can be properly regulated and managed. As a result, the new dynamic EM model can be incorporated with existing dynamic thermal/power/reliability management and optimization approaches, devoted to reliability-aware optimization at multiple system levels (chip/server/rack/data centers). Presented results show that the proposed EM model agrees very well with the numerical analysis results under any time-varying current density and temperature profiles. |