| Title | Circular-Contour-Based Obstacle-Aware Macro Placement |
| Author | *Chien-Hsiung Chiou, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang (National Taiwan University, Taiwan) |
| Page | pp. 172 - 177 |
| Keyword | VLSI, Physical Design, Macro Placement, Obstacle |
| Abstract | We present an obstacle-aware macro placement algorithm which locates macros to simultaneously optimize wirelength and routability. We propose a circular contour to characterize the region formed by all obstacles. With the circular contour, we can effectively avoid the overlap between movable macros and obstacles, and simultaneously optimize the shape and area of the region for standard-cell placement.
Experimental results show that our algorithm can achieve the best quality, compared to manual designs provided by industry and leading academic mixed-size placers. |
| Title | Learning-Based Prediction of Embedded Memory Timing Failures During Initial Floorplan Design |
| Author | Wei-Ting J. Chan (UC San Diego, U.S.A.), Kun Young Chung (Samsung Electronics Co. Ltd., Republic of Korea), Andrew B. Kahng (UC San Diego, U.S.A.), Nancy D. MacDonald (ClariPhy Communications, U.S.A.), *Siddhartha Nath (UC San Diego, U.S.A.) |
| Page | pp. 178 - 185 |
| Keyword | Floorplan, multiphysics, machine learning, Boosting, timing |
| Abstract | Embedded memories are critical in SoC designs as they pose challenges in timing-correctness in advanced technology nodes. We propose a learning-based methodology to perform early prediction of timing failure risk given only the netlist, timing constraints and floorplan context.
We save long runtimes of P&R tools with early prediction. Our methodology identifies which memories are at “risk”, and provides guidance for floorplan changes to reduce predicted “risk”. We can predict slack to within 200ps with only floorplan information. |
| Title | Stitch Aware Detailed Placement for Multiple E-Beam Lithography |
| Author | Yibo Lin (University of Texas at Austin, U.S.A.), *Bei Yu (Chinese University of Hong Kong, Hong Kong), Yi Zou (University of Texas at Austin, U.S.A.), Zhuo Li, Charles J. Alpert (Cadence Design Systems, Inc., U.S.A.), David Z. Pan (University of Texas at Austin, U.S.A.) |
| Page | pp. 186 - 191 |
| Keyword | Multiple Electron Beam Lithography, Stitch Error, Detailed Placement, Dynamic Programming |
| Abstract | As a promising candidate for next generation lithography, multiple e-beam lithography (MEBL) is able to improve manufacturing throughput using parallel beam printing. In MEBL, a layout is split into stripes and the layout patterns are cut by stripe boundaries, then all the stripes are printed in parallel.
If a via pattern or a vertical long wire is overlapping with a stitch, it may suffer from poor printing quality due to the so called stitch error, then the circuit performance may be degraded. In this paper, we propose a comprehensive study on the stitch aware detailed placement to simultaneously minimize the stitch error and optimize other traditional objectives, e.g., wirelength and density. Experimental results show that our algorithms are very effective on modified ICCAD 2014 benchmarks that zero stitch error is guaranteed while the scaled half-perimeter wirelength is very comparable to a state-of-the-art detailed placer. |
| Title | Minimum Implant Area-Aware Placement and Threshold Voltage Refinement |
| Author | Seong-I Lei, *Wai Kei Mak (National Tsing Hua University, Taiwan), Chris Chu (Iowa State University, U.S.A.) |
| Page | pp. 192 - 197 |
| Keyword | Detailed placement, Threshold Voltage Assignment, Implant area |
| Abstract | Threshold voltage assignment is a very effective
technique to reduce leakage power consumption in modern integrated
circuit (IC) design. As feature size continues to decrease,
the layout constraints (called MinIA constraints) on the
implant area, which determines the threshold voltage of a device,
are becoming increasingly difficult to satisfy. It is necessary
to take these constraints into consideration during the layout
stage. In this paper, we propose to resolve the MinIA constraint
violations by a simultaneous detailed placement and threshold
voltage refinement approach. We present an optimal and efficient
mixed integer-linear programming (MILP)-based algorithm
which guarantees to fix all MinIA constraint violations.
Experimental results demonstrate that our algorithm only perturbs
the original placement and threshold voltage assignment
solutions minimally to eliminate all violations and is fast in practice. |