| Title | An Automatic Place-and-Routed Two-Stage Fractional-N Injection-locked PLL Using Soft Injection |
| Author | *Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa (Tokyo Institute of Technology, Japan) |
| Page | pp. 1 - 2 |
| Keyword | Automatic Place-and-Routed, Synthesizable, Fractional-N, Soft Injection, DPLL |
| Abstract | This paper presents an automatic place-and-routed two-stage fractional-N injection-locked PLL (IL-PLL) using soft injection technique for on-chip clock generation. Fabricated in a 65nm CMOS process, this prototype demonstrates a 3.6-ps integrated jitter at 1.5222 GHz and consumes 3mW leading to an FoM of -224.6 dB while only occupying an area of 0.048 mm2. It realizes the first fully synthesized fractional-N injection-locked PLL up-to-date. |
| Title | Time-Domain I/Q-LOFT Compensator Using a Simple Envelope Detector for a Sub-GHz IEEE 802.11af WLAN Transmitter |
| Author | *Chak-Fong Cheang, Ka-Fai Un, Pui-In Mak, Rui Paulo da Silva Martins (University of Macau, Macau) |
| Page | pp. 3 - 4 |
| Keyword | envelope detector, I/Q imbalance, LO feedthrough, wideband |
| Abstract | This paper proposes a hardware-efficient time-domain scheme to digitally compensate the I/Q imbalance and LO feedthrough (LOFT) of a sub-GHz wideband transmitter for the IEEE 802.11af WLAN. A simple envelope detector is the only analog part. The parameters are updated by Least-Mean-Square and estimated efficiently in time domain by using COordinate Rotation DIgital Computer (CORDIC), saving the training time and power consumption. The measured wideband image-rejection ratio (IRR) and LO-leakage- rejection ratio (LRR) are improved from 18.9 to 41.3 dB, and 20.4 to 37.9 dB, respectively. |
| Title | A Noise Reduction Technique for Divider-Less Fractional-N Frequency Synthesizer using Phase-Interpolation Technique |
| Author | *Aravind Tharayil Narayanan, Makihiko Katsuragi, Kengo Nakata, Yuki Terashima, Kenichi Okada, Akira Matsuzawa (Tokyo Institute of Technology, Japan) |
| Page | pp. 5 - 6 |
| Keyword | PLL, Fractional, Sub-sampling, phase interpolator, DTC |
| Abstract | This paper proposes a noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. The phase interpolator helps reduce the jitter introduced into the system by the multi-phase generation mechanism used for the fractional operation. The proposed frequency synthesizer is fabricated in 65nm CMOS process and it is capable of working at frequencies ranging from 4.3GHz to 4.9GHz. The measured close-in phase noise is -113dBc/Hz at an offset of 200kHz from the carrier with 3.3mW power consumption, which results in a FoM of -246dB. |
| Title | A 2.2 uW 15b Incremental Delta-Sigma ADC with Output-Driven Input Segmentation |
| Author | *Bo Wang (Hong Kong University of Science and Technology, Hong Kong), Man-Kay Law (Macau University, Macau), Saqib Mohamad (Hong Kong University of Science and Technology, Hong Kong), Amine Bermak (Hamad Bin Khalifa University, Qatar) |
| Page | pp. 7 - 8 |
| Keyword | incremental delta-sigma ADC, integrator multiplexing, low power ADC |
| Abstract | A micro-power incremental delta-sigma ADC is presented. This ADC uses its decimation filter’s output to estimate the input signal level and dynamically adjusts the modulator feedback voltage, thereby reducing the integrator input range and power. For further power saving, integrator time-multiplexing is also employed. Fabricated in 0.18um CMOS, the 0.12 mm2 ADC consumes 2.16uW at a conversion speed of 85S/s, 15.3b resolution and -2/1.5LSB INL. |
| Title | A 200-MHz 4-Phase Fully Integrated Voltage Regulator With Local Ground Sensing Dual Loop ZDS Hysteretic Control Using 6.5nH Package Bondwire Inductors on 65nm Bulk CMOS |
| Author | Min Kyu Song, Joseph Sankman, Jayeol Lee, *Dongsheng Ma (The University of Texas at Dallas, U.S.A.) |
| Page | pp. 9 - 10 |
| Keyword | integrated voltage regulator, fast transient response, multiple-phase operation, dual-loop voltage regulation |
| Abstract | This paper presents a 200MHz 4-phase fully integrated voltage regulator (FIVR) with 6.5nH package bondwire inductors. With an on-chip delay-locked loop (DLL) for phase synchronization, the proposed FIVR employs a cost-effective local ground sensing feedforward control loop for high speed load transient sensing and a ZDS hysteretic feedback control loop for accurate voltage regulation, independently achieving a dual-loop compensated operation within each sub-converter. Implemented on a standard 65nm bulk CMOS process, the FIVR delivers a peak efficiency of 84.2% at 256mW, with a maximum power density of 670mW/mm2. In response to a 280mA/120ps load step, the FIVR settles within 11ns with 78mV droop. To our best knowledge, this is 2.7 times faster than the best design despite 1.8 times larger load step, while facilitating the use of 1.3 times smaller on-chip capacitor. |
| Title | An AC Powered Converter-Free LED Driver with Low Flicker |
| Author | *Yuan Gao, Lisong Li, Philip K.T. Mok (The Hong Kong University of Science and Technology, Hong Kong) |
| Page | pp. 11 - 12 |
| Keyword | LED driver, Flicker |
| Abstract | A 5.5W mains-powered converter-free LED driver for general lighting application is presented in this summary for the university design contest. The driver is superior to its switching converter based counterparts as it does not require any bulky and expense magnetics or electrolytic capacitors. In addition, the driver is able to significantly reduce the flicker at light output with a quasi-constant power control scheme. The measurement results show that the prototype driver achieves 88.2% efficiency and 0.92 power factor with only 18% flicker at 110V AC 60Hz input. |
| Title | A Variable-Voltage Low-Power Technique for Digital Circuit System |
| Author | *An-Tai Xiao, Yung-Siang Miao (Department of Electronics Engineering, National Chiao Tung University, Taiwan), Ching-Hwa Cheng (Department of Electronics Engineering, Feng Chia University, Taiwan), Jiun-In Guo (Department of Electronics Engineering, National Chiao Tung University, Taiwan) |
| Page | pp. 13 - 14 |
| Keyword | Low-Power, Variable-Voltage |
| Abstract | A swing variable voltage technique (CK-Vdd) is proposed to reduce power consume for generic digital circuit system. The proposed CK-Vdd generates a swing variable voltage, which is different from the conventional constant voltage (Vdd) to the digital circuit. The swing voltage is produced from using Voltage Frequency Adjustor (VFA) and Frequency Duty-Cycle Adjustor (FDCA) circuits. The clock rising and falling signals fanin FDCA to generate an adjustable high-low signal to control VFA generates high-low cycling swing voltage. When the clock is at positive-level, a generic positive-edge digital circuit will need large operation current. CK-Vdd supply high-voltage to the digital circuit at this time. On the other hand, when the clock signal transfers to the low-level, CK-Vdd can supply low-voltage to reduce power consumption. From reducing the supply current to the digital circuit at low-level clock, the digital circuit power consumption can be reduced. We implement the CK-Vdd technique in a H.264 video decoder test chip based on TSMC 90 nm CMOS process. The result shows that when CK-Vdd voltage is 0.7v ~ 0.9v it can save average 32% power consumption. To the maximum, decoder chip can save as high as 45% power consumption. |
| Title | Sub-threshold VLSI Logic Family Exploiting Unbalanced Pull-up/down Network, Logical Effort and Inverse-Narrow-Width Techniques |
| Author | *Ming-Zhong Li, Chio-In Ieong, Man-Kay Law, Pui-In Mak, Mang-I Vai, Sio-Hang Pun, Rui P. Martins (University of Macau, Macau) |
| Page | pp. 15 - 16 |
| Keyword | CMOS, device sizing, inverse narrow width (INW), logical effort, ultralow energy |
| Abstract | This paper presents a complete energy optimized sub-threshold standard cell library exploiting unbalanced pull-up/down (PU/PD) network, logical effort and inverse-narrow-width (INW) techniques. Individual logic cell is optimized for ultra-low-energy applications with low-to- moderate speed requirement. Three 14-tap 8-bit FIR filters are fabricated using a 0.18-μm CMOS technology, while one of them achieved the minimum energy/tap (0.0234 pJ) and 0.365 Figure-of-Merit (FoM) at 100 kHz, 0.31 V, which are well comparable with the state of the art. |
| Title | A Testable and Debuggable Dual-Core System with Thermal-Aware Dynamic Voltage and Frequency Scaling |
| Author | Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, *Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin (Department of Electrical Engineering, National Cheng Kung University, Taiwan) |
| Page | pp. 17 - 18 |
| Keyword | dynamic voltage and frequency scaling (DVFS), test and debug platform |
| Abstract | A sophisticated SoC chip that incorporates many design modules including 2 ARM-like CPUs, a dynamic voltage and frequency scaling (DVFS) design, a master/slave temperature sensing system, and an on-chip test/debug platform is developed and implemented with TSMC 90 nm technology. Measurement results validate the functions and efficiencies of the whole chip. |
| Title | Rapid Prototyping of Multi-Mode QC-LDPC Decoder for 802.11n/ac Standard |
| Author | *Qing Lu, Bruce C. W. Sham, Francis C. M. Lau (The Hong Kong Polytechnic University, Hong Kong) |
| Page | pp. 19 - 20 |
| Keyword | 802.11n/802.11ac, LDPC, multi-mode, FPGA |
| Abstract | A multi-mode QC-LDPC decoder is proposed to satisfy the 802.11n/802.11ac WiFi standard. With code-specific design technique, the overall performance of the decoder is enhanced through ensuring an on-the-fly reconfigurable ability. The proposed architecture has been synthesized using an FPGA for measurements. |
| Title | Sub-µW QRS Detection Processor Using Quadratic Spline Wavelet Transform and Maxima Modulus Pair Recognition for Power-Efficient Wireless Arrhythmia Monitoring |
| Author | *Chio-In Ieong, Pui-In Mak, Mang-I Vai, Rui P. Martins (University of Macau, Macau) |
| Page | pp. 21 - 22 |
| Keyword | ASIC Design, Electrocardiogram, Local Signal Processor, Low Power Sensor Signal Processing, System-on-Chip |
| Abstract | This paper describes a power-efficient processor for extracting the timing of QRS complex from digitized ECG, based on the hardware-efficient architecture of quadratic spline wavelet transform (QSWT) and maxima modulus pair recognition (MMPR). The processor succeeds in saving the wireless system’s power by 6×. |
| Title | Design of an Energy-Autonomous, Disposable, Supply-Sensing Biosensor Using Bio Fuel Cell and 0.23-V 0.25-µm Zero-Vth All-Digital CMOS Supply-Controlled Ring Oscillator with Inductive Transmitter |
| Author | *Kiichi Niitsu, Atsuki Kobayashi (Nagoya University, Japan), Yudai Ogawa, Matsuhiko Nishizawa (Tohoku University, Japan), Kazuo Nakazato (Nagoya University, Japan) |
| Page | pp. 23 - 24 |
| Keyword | energy-autonomous, biosensor, CMOS, all-digital, bio fuel cells |
| Abstract | An energy-autonomous, disposable supply-sensing biosensor based on bio fuel cells and a 0.23-V 0.25-um zero-Vth all-digital CMOS supply-controlled ring oscillator with a current-driven pulse-interval-modulated inductive-coupling transmitter was demonstrated. All-digital and current-driven architecture using zero-Vth transistors enables low-voltage operation and small footprint in cost-competitive legacy CMOS. Measured results with 0.25-um CMOS testchip successfully demonstrated operation under a 0.23-V supply, which is the lowest supply voltage among reported proximity transmitters. An energy-autonomous biosensing operation using organic bio fuel cells was also demonstrated. |